CN116759418A - Wafer splitting method and application - Google Patents
Wafer splitting method and application Download PDFInfo
- Publication number
- CN116759418A CN116759418A CN202310749504.2A CN202310749504A CN116759418A CN 116759418 A CN116759418 A CN 116759418A CN 202310749504 A CN202310749504 A CN 202310749504A CN 116759418 A CN116759418 A CN 116759418A
- Authority
- CN
- China
- Prior art keywords
- wafer
- interconnection element
- quantum
- quantum circuit
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000003825 pressing Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 61
- 229910052738 indium Inorganic materials 0.000 claims description 19
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 13
- 239000003566 sealing material Substances 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 176
- 239000000463 material Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 230000010365 information processing Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 230000005610 quantum mechanics Effects 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000007737 ion beam deposition Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses a wafer splitting method and application, wherein the application provides a wafer splitting method, which comprises the following steps: providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of first areas, each first area is internally provided with a first quantum circuit and a first interconnection element, the surface of the second wafer is provided with a plurality of second areas, and each second area is internally provided with a second quantum circuit and a second interconnection element; forming a protection structure between the first wafer and the second wafer; pressing the first wafer and the second wafer; dicing and cutting the first wafer and the second wafer. In the application, before dicing, a protection structure is formed between the first wafer and the second wafer to protect the first quantum element, the second quantum element, the first interconnection element and the second interconnection element, thereby effectively ensuring the product quality of the quantum chip.
Description
Technical Field
The application belongs to the technical field of quantum computation, and particularly relates to a wafer splitting method and application.
Background
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. The quantum computer has the characteristics of higher running speed, stronger information processing capability, wider application range and the like. Compared with a general computer, the more the information processing amount is, the more the quantum computer is beneficial to the operation, and the accuracy of the operation can be ensured. As the number of bits integrated on a quantum chip increases gradually, a stacked interconnection technology may be used to prepare a double-layered stacked quantum chip in order to realize large-scale expansion of the quantum bits.
When the stacked quantum chips are processed by the existing wafer splitting method, the quantum chips are easy to damage, and the quality of the manufactured quantum chips is difficult to guarantee.
It should be noted that the information disclosed in the background section of the present application is only for enhancement of understanding of the general background of the present application and should not be taken as an admission or any form of suggestion that this information forms the prior art already known to those skilled in the art.
Disclosure of Invention
The application aims to provide a wafer splitting method and application thereof, which are used for solving the defects in the prior art.
One embodiment of the present application provides a wafer dicing method comprising the steps of:
providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of first areas, each first area is internally provided with a first quantum circuit and a first interconnection element electrically connected with the first quantum circuit, the surface of the second wafer is provided with a plurality of second areas, and each second area is internally provided with a second quantum circuit and a second interconnection element electrically connected with the second quantum circuit;
forming a protection structure surrounding the first quantum circuit, the first interconnection element, the second quantum circuit and the second interconnection element between the first wafer and the second wafer;
pressing the first wafer and the second wafer to enable the first interconnection element and the second interconnection element to be fixedly connected;
dicing and cutting the first wafer and the second wafer to obtain the quantum chip.
The wafer dicing method as described above, wherein the step of forming a protective structure surrounding the first quantum circuit, the first interconnection element, the second quantum circuit, and the second interconnection element between the first wafer and the second wafer includes:
forming a first protection layer on the surface of the first wafer where the first interconnection element is located;
forming a second protection layer on the surface of the second wafer where the second interconnection element is located;
the thickness of the first protection layer is consistent with the height of the first interconnection element, the thickness of the second protection layer is consistent with the height of the second interconnection element, and the first protection layer and the second protection layer jointly form the protection structure.
The wafer dicing method as described above, wherein the step of forming the first protection layer on the surface of the first wafer where the first interconnection element is located includes:
depositing a dielectric material on the surface of the first wafer where the first interconnection element is located to obtain the first protection layer;
the first protective layer is polished to expose the first interconnect element.
The wafer dicing method as described above, wherein the step of forming the second protection layer on the surface of the second wafer where the second interconnection element is located includes:
depositing a dielectric material on the surface of the second wafer where the second interconnection element is located to obtain the second protection layer;
the second protection layer is polished to expose the second interconnection element.
The wafer dicing method as described above, wherein the step of forming a protective structure surrounding the first quantum circuit, the first interconnection element, the second quantum circuit, and the second interconnection element between the first wafer and the second wafer includes:
forming a mask layer with a closed pattern on one surface of the first wafer facing the second wafer, wherein the closed pattern exposes part of the first wafer, the closed pattern is positioned in each first area, and each closed pattern surrounds a first interconnection element in the first area;
depositing a sealing material on the mask layer;
and removing the mask layer and the sealing material covered on the surface of the mask layer to obtain the protection structure.
The wafer dicing method as described above, wherein the sealing material is indium.
The wafer breaking method as described above, wherein the first interconnection element and the second interconnection element are indium columns.
The wafer splitting method as described above, wherein the first regions are distributed in an array on the surface of the first wafer, and the second regions are correspondingly distributed in an array on the surface of the second wafer.
The wafer breaking method as described above, wherein the projection of the geometric center of the first region coincides with the projection of the geometric center of the corresponding second region along the direction perpendicular to the first wafer.
The wafer breaking method as described above, wherein the dicing the first and second wafers includes:
dicing the first wafer along an edge of the first region and dicing the second wafer along an edge of the second region.
In another embodiment of the present application, there is provided a wafer dicing method as described above for preparing quantum chips.
Compared with the prior art, the application provides a wafer splitting method, which comprises the following steps: providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of first areas, each first area is internally provided with a first quantum circuit and a first interconnection element electrically connected with the first quantum circuit, the surface of the second wafer is provided with a plurality of second areas, and each second area is internally provided with a second quantum circuit and a second interconnection element electrically connected with the second quantum circuit; forming a protection structure surrounding the first quantum circuit, the first interconnection element, the second quantum circuit and the second interconnection element between the first wafer and the second wafer; pressing the first wafer and the second wafer to enable the first interconnection element and the second interconnection element to be fixedly connected; dicing and cutting the first wafer and the second wafer to obtain the quantum chip. According to the application, the first area and the second area which are in one-to-one correspondence are respectively arranged on the first wafer and the second wafer, the first area and the second area are respectively provided with the first quantum circuit, the second quantum circuit, the first interconnection element and the second interconnection element, then the first wafer and the second wafer are pressed together, dicing is carried out, and thus double-layer stacked quantum chips are manufactured in batches.
Drawings
FIG. 1 is a flow chart of a wafer dicing method according to the present application;
FIG. 2 is a schematic diagram of a first wafer and a second wafer in the wafer dicing method according to the present application;
FIG. 3 is a schematic diagram of a bonding process of a first wafer and a second wafer according to the present application;
FIG. 4 is a schematic view of a first interconnect element, a second interconnect element in accordance with the present application;
FIG. 5 is a schematic view of an indium wall according to another embodiment of the present application;
fig. 6 is a schematic diagram of a bonding process of a first wafer and a second wafer according to another embodiment of the application.
Reference numerals illustrate:
1-a first wafer, 2-a second wafer and 3-an indium wall;
11-first region, 12-first quantum circuit, 13-first interconnect element, 14-first protective layer;
21-second region, 22-second quantum circuit, 23-second interconnect element, 24-second protective layer.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the claimed technical solution of the present application can be realized without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments can be mutually combined and referred to without contradiction.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. The quantum computer has the characteristics of higher running speed, stronger information processing capability, wider application range and the like. Compared with a general computer, the more the information processing amount is, the more the quantum computer is beneficial to the operation, and the accuracy of the operation can be ensured. As the number of bits integrated on a quantum chip increases gradually, a stacked interconnection technology may be used to prepare a double-layered stacked quantum chip in order to realize large-scale expansion of the quantum bits.
In the batch preparation process of the existing stacked quantum chips, the quantum chips are easy to damage, and impurities such as fragments generated by cutting are easy to remain between two substrates of the quantum chips in the wafer splitting process, so that the performance of the quantum chips is negatively affected, and the quality of the manufactured quantum chips is difficult to ensure.
Referring to fig. 1 to fig. 4, the wafer breaking method provided by the embodiment of the application includes the following steps:
s1, providing a first wafer 1 and a second wafer 2, wherein the surface of the first wafer 1 is provided with a plurality of first areas 11, each first area 11 is internally provided with a first quantum circuit 12 and a first interconnection element 13 electrically connected with the first quantum circuit 12, the surface of the second wafer 2 is provided with a plurality of second areas 21, and each second area 21 is internally provided with a second quantum circuit 22 and a second interconnection element 23 electrically connected with the second quantum circuit 22;
in implementation, the first wafer 1 and the second wafer 2 are provided, and illustratively, materials of the first wafer 1 and the second wafer 2 may be silicon, sapphire, a silicon dioxide substrate, a gallium nitride substrate, or the like. In different usage scenarios, the materials of the first wafer 1 and the second wafer 2 are selected correspondingly, which is not limited to the above example. In this embodiment, the first wafer 1 and the second wafer 2 may be made of a sapphire material, where the sapphire material has a certain transparency, so that when the relative positions of the first wafer 1 and the second wafer 2 are adjusted, it is helpful to observe the alignment condition of certain specific elements on the first wafer 1 and the second wafer 2;
determining a plurality of first areas 11 on the surface of the first wafer 1, and determining a plurality of second areas 21 on the surface of the second wafer 2, wherein the first areas 11 and the second areas 21 are in one-to-one correspondence, and when the method is implemented, the surface of the first wafer 1 is divided into a plurality of first areas 11, preferably, the shapes of the first areas 11 can be rectangular, the sizes of the first areas 11 are the same, the first areas 11 are distributed on the surface array of the first wafer 1, similarly, the second wafer 2 is divided into a plurality of second areas 21 relative to one surface of the first wafer 1, preferably, the shapes of the second areas 21 can be rectangular, the sizes of the second areas 21 are the same, and the second areas 21 are distributed on the surface array of the second wafer 2;
forming a first quantum circuit 12 in each first area 11, forming a second quantum circuit 22 in each second area 21, wherein a film plating process can be adopted, a layer of superconducting film is respectively plated on the surfaces of the first wafer 1 and the second wafer 2, and when the method is specifically implemented, the superconducting film can be an aluminum film, a niobium film and the like, in a low-temperature environment such as a dilution refrigerator, the superconducting film such as an aluminum film, a niobium film and the like can display superconducting characteristics, then a plurality of first quantum circuits 12 and a plurality of second quantum circuits 22 are respectively prepared on the superconducting films of the first wafer 1 and the second wafer 2 by utilizing an etching process, each first quantum circuit 12 is respectively positioned in the first area 11, the first quantum circuits 12 are respectively in one-to-one correspondence with the first area 11, each second quantum circuit 22 is respectively positioned in the second area 21, and when the method is specifically implemented, a photoresist layer is firstly coated on the surface of the first wafer 1, after exposure and development, a plurality of second quantum circuits 12 are respectively positioned in the second area 21, and a plurality of second quantum circuits are respectively etched in the second area 2, and a plurality of quantum circuits are respectively positioned in the second area 11, and a plurality of second quantum circuits are respectively etched in the second area 21;
forming first interconnection elements 13 in the first regions 11, forming second interconnection elements 23 in the second regions 21, wherein in implementation, a plurality of first interconnection elements 13 are formed in each first region 11, a plurality of second interconnection elements 23 are formed in each second region 21, the first interconnection elements 13 are in one-to-one correspondence with the second interconnection elements 23, a part of the first interconnection elements 13 are electrically connected with the first quantum circuits 12, a part of the second interconnection elements 23 are electrically connected with the second quantum circuits 22, and the first interconnection elements 13 and the second interconnection elements 23 are indium columns;
s2, forming a protection structure surrounding the first quantum circuit 12, the first interconnection element 13, the second quantum circuit 22 and the second interconnection element 23 between the first wafer 1 and the second wafer 2, specifically, forming a protection structure between the first wafer 1 and the second wafer 2 to protect the first interconnection element 13, the second interconnection element 23, the first quantum circuit 12 and the second quantum circuit 22 from damage, wherein when the protection structure is implemented, the protection structure may be a dielectric layer filled between the first wafer 1 and the second wafer 2, and the dielectric layer covers and wraps the first interconnection element 13, the second interconnection element 23, the first quantum circuit 12 and the second quantum circuit 22;
by forming the protection structure between the first wafer 1 and the second wafer 2 and surrounding the first interconnection element 13, the second interconnection element 23, the first quantum circuit 12 and the second quantum circuit 22 by the protection structure, the first interconnection element 13, the second interconnection element 23, the first quantum circuit 12 and the second quantum circuit 22 can be effectively protected from damage due to violent damage in the subsequent processing;
s3, pressing the first wafer 1 and the second wafer 2 to enable the first interconnection element 13 to be fixedly connected with the second interconnection element 23, enabling the first quantum circuit 12 to be electrically connected with the second quantum circuit 22 through the first interconnection element 13 and the second interconnection element 23, aligning the first interconnection element 13 with the second interconnection element 23 one by one when pressing the first wafer 1 and the second wafer 2, enabling the first interconnection element 13 and the second interconnection element to be fixedly thermally pressed by a wafer bonding machine, and enabling the first wafer 1 to be fixedly kept with the second wafer 2, and enabling the first quantum circuit 12 and the second quantum circuit 22 to be electrically connected through the first interconnection element 13 and the second interconnection element 23;
s4, dicing and cutting the first wafer 1 and the second wafer 2 to obtain quantum chips in batches.
In this embodiment, the first area 11 and the second area 21 are respectively disposed on the first wafer 1 and the second wafer 2 in a one-to-one correspondence manner, then the first quantum circuit 12 and the second quantum circuit 22 are respectively prepared in the first area 11 and the second area 21, then the first wafer 1 and the second wafer 2 are pressed together, dicing is performed, and thus double-layer stacked quantum chips are prepared in batches, and before dicing, the first quantum element, the second quantum element, the first interconnection element 13 and the second interconnection element 23 are protected by forming a protection structure between the first wafer 1 and the second wafer 2, so that the first quantum element, the second quantum element, the first interconnection element 13 and the second interconnection element 23 are prevented from being polluted or damaged in the dicing process, and the product quality of the quantum chips is effectively ensured.
In some embodiments of the present application, the step of forming a protective structure surrounding the first quantum circuit 12, the first interconnect element 13, the second quantum circuit 22, the second interconnect element 23 between the first wafer 1, the second wafer 2 comprises:
forming a first protection layer 14 on the surface of the first wafer 1 where the first interconnection element 13 is located, during implementation, depositing a dielectric material on the surface of the first wafer 1 where the first interconnection element 13 is located to obtain the first protection layer 14, and polishing the first protection layer 14 to expose the first interconnection element 13;
forming a second protection layer 24 on the surface of the second wafer 2 where the second interconnection element 23 is located, during implementation, depositing a dielectric material on the surface of the first wafer 1 where the first interconnection element 13 is located to obtain the first protection layer 14, and polishing the first protection layer 14 to expose the first interconnection element 13, where the first protection layer 14 and the second protection layer 24 may be made of insulating materials;
the thickness of the first protective layer 14 is consistent with the height of the first interconnection element 13, the thickness of the second protective layer 24 is consistent with the height of the second interconnection element 23, the first protective layer 14 and the second protective layer 24 together form the protective structure, and in a specific manner, an insulating material may be deposited on opposite sides of the first wafer 1 and the second wafer 2 respectively to obtain the first protective layer 14 and the second protective layer 24, and then the first protective layer 14 and the second protective layer 24 are polished by a CMP polishing process to expose the first interconnection element 13 and the second interconnection element 23, and the insulating material may be silicon nitride, silicon dioxide, boron nitride, or the like, where the ends of the first interconnection element 13 and the second interconnection element 23 are flush with the surfaces of the first protective layer 14 and the second protective layer 24 respectively after polishing.
In this embodiment, by forming the first protection layer 14 on the surface of the first wafer 1, forming the second protection layer 24 on the surface of the second wafer 2, and polishing the first protection layer 14 and the second protection layer 24 by using a CMP polishing process to expose the first interconnection element 13 and the second interconnection element 23, the first interconnection element 13 and the second interconnection element 23 can be in physical contact during the pressing process of the first wafer 1 and the second wafer 2, so that the electrical connection between the first interconnection element 13 and the second interconnection element 23 can be achieved.
Referring to fig. 5 and 6, in other embodiments of the present application, the step of forming a protection structure surrounding the first quantum circuit 12, the first interconnect element 13, the second quantum circuit 22, and the second interconnect element 23 between the first wafer 1 and the second wafer 2 includes:
forming a mask layer with a closed pattern on one surface of the first wafer 1 facing the second wafer 2, wherein the closed pattern exposes a part of the first wafer 1, the closed pattern is located in each first area 11, each closed pattern surrounds a first interconnection element 13 in the first area 11, when the method is implemented, photoresist is coated on one surface of the first wafer 1 facing the second wafer 2 in a spinning manner so as to obtain a photoresist layer on the surface of the first wafer 1, and then the photoresist layer is subjected to processes such as exposure and development to obtain the closed pattern on the photoresist layer, wherein the closed pattern can be in a shape of a rectangle, a circle, a polygon and the like, the closed pattern has a plurality of closed patterns, the closed patterns are in one-to-one correspondence with the first areas 11, each first area 11 is internally provided with a closed pattern, each closed pattern is located in the first area 11, and part of the surface of the first wafer 1 is exposed by the closed pattern;
then, a deposition process is utilized to deposit sealing materials on the mask layer, part of the sealing materials are deposited on the surface of the mask layer, and part of the sealing materials are deposited on the surface of the first wafer 1 exposed by the closed graph;
the masking layer and the sealing material covering the surface of the masking layer are removed, so that the sealing material deposited on the surface of the first wafer 1 is retained, so as to obtain the protection structure, and illustratively, the protection structure is a rectangular wall structure formed on the surface of the first wafer 1, and the rectangular wall structure encloses the first interconnection element 13 and the first quantum circuit 12 in the same first area 11, so as to protect the first quantum circuit 12 and the first interconnection element 13.
The height of the indium wall 3 is equal to the sum of the heights of the first interconnection element 13 and the second interconnection element 23, the sealing material may be indium, the indium is used to construct a closed indium wall 3 in each first region 11, the first interconnection element 13 and the second interconnection element 23 are all indium columns, when the first wafer 1 and the second wafer 2 are pressed together, the indium wall 3 is connected with the surface of the second wafer 2, a closed space is formed between the first region 11 and the second region 21 by using the indium wall 3, and the first quantum circuit 12, the second quantum circuit 22, the first interconnection element 13 and the second interconnection element 23 are all located in the closed space, so that the first quantum circuit 12, the second quantum circuit 22, the first interconnection element 13 and the second interconnection element 23 in each first region 11 and each second region 21 are protected.
In this embodiment, an indium wall 3 is constructed on the surface of the first wafer 1 to serve as a protection structure, the indium wall 3 corresponds to the first areas 11 one by one, an indium wall 3 is formed in each first area 11, and then the first wafer 1 and the second wafer 2 are connected together by using a wafer bonding machine, so that a closed space is constructed between the first area 11 and the second area 21 by using the indium wall 3, thereby protecting the first quantum circuit 12, the second quantum circuit 22, the first interconnection element 13 and the second interconnection element 23 in each first area 11 and the second area 21, avoiding damage to the quantum circuits caused by mixing impurities generated by the first wafer 1 and the second wafer 2 between the first area 11 and the second area 21 during splitting, and further improving bonding strength between the first wafer 1 and the second wafer 2 by using the indium wall 3, effectively ensuring normal splitting operation and ensuring product quality of the manufactured quantum chip.
It should be noted that, in order to facilitate dicing and cutting the first wafer 1 and the second wafer 2, the first areas 11 are distributed on the surface array of the first wafer 1, and the second areas 21 are correspondingly distributed on the surface array of the second wafer 2, so that when dicing and cutting the first wafer 1 and the second wafer 2, a plurality of first areas 11 or second areas 21 can be cut in one feeding process, thereby improving the cutting efficiency.
Further, as an example, the dimensions of the respective first and second regions 11, 21 are uniform, and the projection of the geometric center of the first region 11 coincides with the projection of the geometric center of the corresponding second region 21 in the direction perpendicular to the first wafer 1, so as to cut the first and second wafers 1, 2.
In some embodiments of the present application, the dicing the first and second wafers 1, 2 includes:
dicing the first wafer 1 along the edge of the first area 11, dicing the second wafer 2 along the edge of the second area 21, and illustratively, using a laser dicing machine to cut the first wafer 1 and the second wafer 2 respectively, and precisely adjusting the dicing depth, when dicing the first wafer 1, ensuring that the second wafer 2 is not damaged, and when dicing the second wafer 2, ensuring that the first wafer 1 is not damaged.
In another embodiment of the present application, there is provided a wafer dicing method as described above for preparing quantum chips.
By combining the embodiments, the wafer splitting method provided by the application can realize batch preparation of the quantum chips and can effectively ensure the product quality of the quantum chips when being applied to preparing double-layer quantum chips.
As described herein, the terms "deposition process" and/or "deposition process" may refer to any process of growing, coating, depositing, and/or otherwise transferring one or more first materials onto one or more second materials. Exemplary deposition processes may include, but are not limited to: physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), atomic layer deposition ("ALD"), low pressure chemical vapor deposition ("LPCVD"), plasma enhanced chemical vapor deposition ("PECVD"), high density plasma chemical vapor deposition ("HDPCVD"), sub-atmospheric pressure chemical vapor deposition ("SACVD"), rapid thermal chemical vapor deposition ("RTCVD"), in situ radical assisted deposition, high temperature oxide deposition ("HTO"), low temperature oxide deposition ("LTO"), limited reaction process CVD ("LRPCVD"), ultra-high vacuum chemical vapor deposition ("UHVCVD"), metalorganic chemical vapor deposition ("MOCVD"), physical vapor deposition ("PVD"), chemical oxidation, sputtering, electroplating, evaporation, spin coating, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, combinations thereof, and/or the like.
While the foregoing is directed to embodiments of the present application, other and further embodiments of the application may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A wafer dicing method, comprising the steps of:
providing a first wafer (1) and a second wafer (2), wherein the surface of the first wafer (1) is provided with a plurality of first areas (11), each first area (11) is internally provided with a first quantum circuit (12) and a first interconnection element (13) electrically connected with the first quantum circuit (12), the surface of the second wafer (2) is provided with a plurality of second areas (21), and each second area (21) is internally provided with a second quantum circuit (22) and a second interconnection element (23) electrically connected with the second quantum circuit (22);
forming a protective structure surrounding the first quantum circuit (12), the first interconnection element (13), the second quantum circuit (22) and the second interconnection element (23) between the first wafer (1) and the second wafer (2);
pressing the first wafer (1) and the second wafer (2) to enable the first interconnection element (13) and the second interconnection element (23) to be fixedly connected;
dicing the first wafer (1) and the second wafer (2) to obtain quantum chips.
2. The wafer dicing method according to claim 1, characterized in that the step of forming a protective structure surrounding the first quantum circuit (12), first interconnect element (13), second quantum circuit (22), second interconnect element (23) between the first wafer (1), the second wafer (2) comprises:
forming a first protection layer (14) on the surface of the first wafer (1) where the first interconnection element (13) is located;
forming a second protection layer (24) on the surface of the second wafer (2) where the second interconnection element (23) is located;
wherein the thickness of the first protective layer (14) is consistent with the height of the first interconnection element (13), the thickness of the second protective layer (24) is consistent with the height of the second interconnection element (23), and the first protective layer (14) and the second protective layer (24) together form the protective structure.
3. Wafer dicing method according to claim 2, characterized in that the step of forming a first protective layer (14) on the surface of the first wafer (1) on which the first interconnect element (13) is located comprises:
depositing a dielectric material on the surface of the first wafer (1) on which the first interconnect element (13) is located to obtain the first protection layer (14);
the first protection layer (14) is polished to expose the first interconnect element (13).
4. A wafer dicing method according to claim 3, characterized in that the step of forming a second protective layer (24) on the surface of the second wafer (2) on which the second interconnect element (23) is located comprises:
depositing a dielectric material on the surface of the second wafer (2) on which the second interconnect element (23) is located to obtain the second protection layer (24);
the second protection layer (24) is polished to expose the second interconnect element (23).
5. The wafer dicing method according to claim 1, characterized in that the step of forming a protective structure surrounding the first quantum circuit (12), first interconnect element (13), second quantum circuit (22), second interconnect element (23) between the first wafer (1), the second wafer (2) comprises:
forming a mask layer with a closed pattern on one surface of the first wafer (1) facing the second wafer (2), wherein the closed pattern exposes part of the first wafer (1), the closed pattern is positioned in each first area (11), and each closed pattern surrounds a first interconnection element (13) in the first area (11);
depositing a sealing material on the mask layer;
and removing the mask layer and the sealing material covered on the surface of the mask layer to obtain the protection structure.
6. The wafer dicing method of claim 5, wherein the sealing material is indium.
7. Wafer cleaving method according to any of the claims 1-6, wherein the first interconnect element (13) and the second interconnect element (23) are indium columns.
8. Wafer breaking method according to claim 7, characterized in that the first areas (11) are distributed in an array on the surface of the first wafer (1) and the corresponding second areas (21) are distributed in an array on the surface of the second wafer (2).
9. Wafer breaking method according to claim 8, characterized in that the projection of the geometric centre of the first region (11) coincides with the projection of the geometric centre of the corresponding second region (21) in a direction perpendicular to the first wafer (1).
10. Use of a wafer cleaving method according to any of claims 1-9 for the preparation of quantum chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310749504.2A CN116759418A (en) | 2023-06-21 | 2023-06-21 | Wafer splitting method and application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310749504.2A CN116759418A (en) | 2023-06-21 | 2023-06-21 | Wafer splitting method and application |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116759418A true CN116759418A (en) | 2023-09-15 |
Family
ID=87951139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310749504.2A Pending CN116759418A (en) | 2023-06-21 | 2023-06-21 | Wafer splitting method and application |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116759418A (en) |
-
2023
- 2023-06-21 CN CN202310749504.2A patent/CN116759418A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6624505B2 (en) | Packaged integrated circuits and methods of producing thereof | |
| US6864534B2 (en) | Semiconductor wafer | |
| US5691248A (en) | Methods for precise definition of integrated circuit chip edges | |
| US6693358B2 (en) | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device | |
| US6946384B2 (en) | Stacked device underfill and a method of fabrication | |
| US8039314B2 (en) | Metal adhesion by induced surface roughness | |
| KR20220036996A (en) | Diffusion barrier collar for interconnects | |
| EP0828288A2 (en) | Energy relieving crack stop | |
| US7544605B2 (en) | Method of making a contact on a backside of a die | |
| CN109390305B (en) | Bonding wafer and preparation method thereof | |
| JP2005167190A (en) | Method of dicing semiconductor wafer | |
| US10818556B2 (en) | Method for forming a semiconductor structure | |
| WO2002051217A2 (en) | Packaged integrated circuits and methods of producing thereof | |
| EP3214643A2 (en) | Overmolded chip scale package | |
| CN111564362B (en) | Wafer edge processing method | |
| KR20000047991A (en) | Method and apparatus for preventing formation of black silicon on edges of wafers | |
| CN116759418A (en) | Wafer splitting method and application | |
| US20230065248A1 (en) | Polymer coated semiconductor devices and hybrid bonding to form semiconductor assemblies | |
| CN111968985B (en) | Method for manufacturing three-dimensional memory | |
| CN115763237A (en) | Wafer cutting method | |
| US20230163039A1 (en) | Double patterned microcooler having alternating fin widths | |
| US11710661B2 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| CN116403890A (en) | Packaging method | |
| CN116913773B (en) | Semiconductor chip and forming method thereof | |
| CN115579282B (en) | Wafer processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |