CN115763237A - Wafer cutting method - Google Patents
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- CN115763237A CN115763237A CN202211587049.2A CN202211587049A CN115763237A CN 115763237 A CN115763237 A CN 115763237A CN 202211587049 A CN202211587049 A CN 202211587049A CN 115763237 A CN115763237 A CN 115763237A
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- 238000000034 method Methods 0.000 title claims abstract description 88
- 238000005520 cutting process Methods 0.000 title claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 197
- 239000011241 protective layer Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims description 57
- 238000003698 laser cutting Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 153
- 239000000758 substrate Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009623 Bosch process Methods 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The embodiment of the disclosure discloses a wafer cutting method, which comprises the following steps: providing a wafer to be cut; the wafer to be cut comprises a front surface and a back surface which are opposite along a first direction, wherein the first direction is the thickness direction of the wafer to be cut; forming a stop layer on the back of the wafer to be cut; forming a protective layer on the stop layer; cutting the wafer to be cut from the front surface to form a first groove, wherein the stop layer is exposed out of the first groove; and removing part of the stop layer from the first groove to form a second groove, wherein the second groove exposes the protective layer.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a wafer cutting method.
Background
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor Integrated Circuit, and various Circuit element structures can be manufactured on the silicon wafer to form an Integrated Circuit (IC) device having a specific electrical function. A wafer is often integrated with a plurality of chips, and when a single chip needs to be separated, the wafer needs to be cut.
In the process of cutting the wafer, a protective layer for fixing the chips is adhered to the back surface of the wafer, wherein the protective layer generally adopts a UV film, and the protective layer can prevent the chips from being scattered after the wafer is cut. However, in the process of dicing a wafer, a certain damage may be caused to the UV film, and how to protect the UV film during the dicing process and reduce the damage to the UV film is an urgent problem to be solved.
Disclosure of Invention
In view of this, an embodiment of the present disclosure provides a wafer cutting method, including:
providing a wafer to be cut; the wafer to be cut comprises a front surface and a back surface which are opposite along a first direction, wherein the first direction is the thickness direction of the wafer to be cut;
forming a stop layer on the back of the wafer to be cut;
forming a protective layer on the stop layer;
cutting the wafer to be cut from the front surface to form a first groove, wherein the stop layer is exposed out of the first groove;
and removing part of the stop layer from the first groove to form a second groove, wherein the second groove exposes the protective layer.
In the above scheme, the etching selection ratio of the stop layer to the protection layer is greater than a first preset value.
In the above scheme, the first preset value is 10:1.
in the above scheme, the stop layer is made of silicon oxide or silicon nitride, and the protective layer is made of a UV film or a blue film.
In the above scheme, the etching selection ratio of the edge of the wafer to be cut to the stop layer is greater than a second preset value.
In the above scheme, the second preset value is 50:1.
in the above scheme, the thickness of the stop layer along the first direction is T, and T is greater than or equal to 0.5 μm and less than or equal to 5 μm.
In the above solution, the removing a portion of the stop layer from the first groove includes:
and removing part of the stop layer from the first groove by using an etching process.
In the above scheme, the method further comprises:
before a stop layer is formed on the back of the wafer to be cut, a bearing layer is formed on the front of the wafer to be cut;
and removing the bearing layer after forming the protective layer on the stop layer.
In the above scheme, the method further comprises:
before a stop layer is formed on the back of the wafer to be cut, thinning the back of the wafer to be cut from the back of the wafer to be cut.
In the above scheme, the method further comprises:
before a stop layer is formed on the back surface of the wafer to be cut, a rewiring layer is formed on the front surface of the wafer to be cut;
before the wafer to be cut is cut from the front surface, removing part of the rewiring layer from the front surface to form a third groove; the third groove exposes the wafer to be cut;
the dicing the wafer to be diced from the front side comprises:
and cutting the wafer to be cut from the third groove on the front surface.
In the above scheme, a scribe line is formed in the redistribution layer; the removing a portion of the redistribution layer from the front side includes:
and removing part of the rewiring layer along the cutting path of the rewiring layer.
In the foregoing solution, the removing a portion of the redistribution layer from the front surface includes:
and removing part of the rewiring layer from the front surface by using a laser cutting process.
The embodiment of the disclosure provides a wafer cutting method, which includes: providing a wafer to be cut; the wafer to be cut comprises a front surface and a back surface which are opposite along a first direction, wherein the first direction is the thickness direction of the wafer to be cut; forming a stop layer on the back of the wafer to be cut; forming a protective layer on the stop layer; cutting the wafer to be cut from the front surface to form a first groove, wherein the stop layer is exposed out of the first groove; and removing part of the stop layer from the first groove to form a second groove, wherein the second groove exposes the protective layer. In the embodiment of the disclosure, the stop layer is formed between the wafer to be cut and the protective layer, so that the wafer to be cut can be stopped on the stop layer during cutting, the problem that the protective layer is damaged due to over etching when the wafer to be cut is solved, and the success rate of film expansion in the process of taking out a chip can be improved.
Drawings
Fig. 1 is a schematic flow chart of wafer dicing according to an embodiment of the disclosure;
fig. 2-11 are schematic cross-sectional views illustrating a wafer dicing process according to an embodiment of the disclosure.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated with reference to the drawings and the embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
It is to be understood that the meaning of "on … …", "above … …" and "above … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.
Further, spatially relative terms such as "on … …," "over … …," "over … …," "up," etc., may be used herein to describe one element or feature's relationship to another element or feature as shown for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In embodiments of the present disclosure, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, arsenic, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
As the feature size of memory devices decreases and the density of interconnections increases, memory devices have evolved in three dimensions. Wherein, the hybrid bonding technology can realize three-dimensional integration of two different functional chips (also called dies). For example, a memory array chip is hybrid bonded with a peripheral circuit chip, and a three-dimensional memory with a smaller size, higher interconnection density, and lower power consumption can be realized.
The hybrid bonding process may be distinguished by bonding objects, including Wafer to Wafer (W2W, wafer to Wafer) bonding, chip to Wafer (C2W, chip to Wafer) bonding, and Chip to Chip (C2C, chip to Chip). Regardless of the bonding, the wafer needs to be diced so that the chips on the wafer are diced to form individual chips.
At present, before a wafer to be cut is cut, a protective layer for fixing a chip is adhered to the back surface of the wafer to be cut, and then the wafer to be cut is cut, the protective layer generally adopts a UV film or a blue film, for example, a UV film is adopted, after the UV film is irradiated by laser, the viscosity of the UV film is rapidly reduced, and the chip is easily taken down. Since the distance between the cut chips is only the width of the cutting line or the score line, the chips are not easily removed from the UV film, and therefore, the wafer needs to be mounted on a film expander for expansion, so that the distance between the chips is expanded and then taken out. However, the UV film has low temperature resistance, the temperature generally cannot exceed 100 ℃, the cleaning condition is poor under special solvents such as strong acid, strong alkali and the like, and the wafer cutting of the device is influenced due to the dissolution of the UV film caused by overhigh temperature or the influence of the special solvents; and the UV film is damaged during plasma cutting, so that the success rate of film expansion in the subsequent process is influenced.
Accordingly, to solve the above problems, an embodiment of the present disclosure provides a wafer dicing method, and fig. 1 is a schematic flow chart of the wafer dicing method according to the embodiment of the present disclosure. As shown in fig. 1, a wafer dicing method provided by the embodiment of the present disclosure includes the following steps:
s1100: providing a wafer to be cut; the wafer to be cut comprises a front surface and a back surface which are opposite along a first direction, wherein the first direction is the thickness direction of the wafer to be cut;
s1200: forming a stop layer on the back of the wafer to be cut;
s1300: forming a protective layer on the stop layer;
s1400: cutting the wafer to be cut from the front surface to form a first groove, wherein the stop layer is exposed out of the first groove;
s1500: and removing part of the stop layer from the first groove to form a second groove, wherein the second groove exposes the protective layer.
It should be understood that the steps shown in FIG. 1 are not exclusive, and that other steps may be performed before, after, or between any of the steps in the operations shown; the steps shown in fig. 1 may be sequentially adjusted according to actual needs.
In step S1100, as shown in fig. 2, a wafer 101 to be cut is provided.
In some specific examples, the wafer 101 to be cut includes a substrate, and the substrate may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific examples, the substrate is a silicon substrate.
In some specific examples, the substrate has device structures (not shown in fig. 2) formed therein, including, but not limited to, MOS devices, sensing devices, memory devices, and/or other passive devices.
Here, the wafer 101 to be cut includes a front surface, which may be understood as a surface on which the substrate is generally used to form a device structure, and a back surface, which may be understood as a surface on which the substrate is generally used to be placed on a susceptor.
In some specific examples, the wafer to be cut 101 includes a plurality of chips, and a dicing street is disposed between two adjacent chips.
In step S1200, a stop layer is formed on the back side of the wafer to be cut.
In some embodiments, as shown in fig. 3, the method further comprises:
and before a stop layer is formed on the back surface of the wafer to be cut, a rewiring layer is formed on the front surface of the wafer to be cut.
As shown in fig. 3, the redistribution layer 107 covers the front surface of the wafer 101 to be cut, an interconnection structure 110 is formed in the redistribution layer 107, the interconnection structure 110 may be interconnected with a device structure in a substrate, the interconnection structure 110 may be one or more metal layers, and different metal layers may be interconnected through electrical connectors such as contact plugs, interconnection layers, and/or vias. In some specific examples, the material of the interconnect structure 110 includes, but is not limited to, a metal material, and the material of the interconnect structure 110 may be, for example, tungsten, aluminum, copper, or a combination thereof.
In some embodiments, as shown in fig. 3, a scribe line is also formed in the redistribution layer 107, and a scribe line pad 111 is formed in the scribe line.
In some specific examples, the scribe line formed in the wafer 101 to be diced overlaps with the scribe line pad 111 in the redistribution layer 107 in a projection of a first plane, where the first plane is perpendicular to a first direction, where the first direction is a thickness direction of the wafer 101 to be diced. The first direction here may be specifically the Y-axis direction shown in fig. 1 to 11.
In some embodiments, as shown in fig. 4, the method further comprises:
before forming the stop layer 102 on the back side of the wafer 101 to be cut, a carrier layer 106 is formed on the front side of the wafer 101 to be cut.
In some specific examples, the carrier layer 106 includes a substrate on the front side of the wafer 101 to be diced and on the redistribution layer 107. The method for forming the carrier layer 106 on the front surface of the wafer 101 to be cut includes, but is not limited to, a bonding process.
It can be understood that, the forming of the carrier layer 106 on the front side of the wafer 101 to be diced mainly considers that the back side of the wafer 101 to be diced is required to face upward and the front side thereof faces downward during the process operation performed on the back side of the wafer 101 to be diced in the subsequent process, and the carrier layer 106 is provided here to prevent the device structure formed on the front side of the wafer to be diced from being damaged when the front side of the wafer 101 to be diced is placed on the carrier table.
In some embodiments, as shown in fig. 5, the method further comprises:
before forming the stop layer 102 on the back surface of the wafer 101 to be cut, thinning the back surface of the wafer 101 to be cut from the back surface of the wafer 101 to be cut.
In some specific examples, the method for thinning the back surface of the wafer 101 to be cut from the back surface of the wafer 101 to be cut includes, but is not limited to, chemical Mechanical Polishing (CMP), wet etching, and dry etching.
It can be understood that the thinning process performed on the wafer 101 to be cut herein mainly enables the thickness of the wafer 101 to be cut to be relatively thin when the first groove 104 is formed by cutting the wafer 101 to be cut in the subsequent process, so that the cutting time of the wafer 101 to be cut can be reduced when cutting is performed.
Here, when thinning the wafer 101 to be cut from the back side of the wafer 101 to be cut, the thinned thickness needs to be controlled within a certain range, and at least the device structure in the wafer 101 to be cut is not damaged.
In some specific examples, the wafer 101 to be diced may be subjected to a flip process such that the front side of the wafer 101 to be diced faces downward, thereby making it possible to perform a thinning process on the wafer 101 to be diced.
Next, as shown in fig. 6, a stop layer 102 is formed on the back surface of the wafer 101 to be diced.
In some specific examples, the wafer 101 to be diced may be faced down, thereby forming the stop layer 102 on the back side of the wafer 101 to be diced.
In some specific examples, the method of forming the stop Layer 102 includes, but is not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, and the like.
In some embodiments, the etch selectivity of the stop layer 102 to the protective layer is greater than a first predetermined value.
In some embodiments, the first preset value is 10:1.
it can be understood that, in the embodiment of the present disclosure, the etching selection ratio of the stop layer 102 to the protection layer 103 is greater than the first preset value, so that when a part of the stop layer 102 is removed by using an etching process in a subsequent process, the stop layer can be stopped on the protection layer 103 in time, the influence on the protection layer 103 in the etching process is reduced, and the protection layer 103 is prevented from being damaged.
It should be noted that the first preset value given here is only an exemplary example and is not used to limit the etching selection ratio of the stop layer 102 to the protection layer 103 in the embodiments of the present disclosure. In practical applications, the influence on the protection layer 103 only needs to be within an acceptable range when the partial stop layer 102 is removed.
In some embodiments, the etching selection ratio of the wafer to be cut to the stop layer is greater than a second preset value.
In some embodiments, the second preset value is 50:1.
it can be understood that, in the embodiment of the present disclosure, the etching selection ratio between the wafer to be cut and the stop layer is greater than the second preset value, so that when the wafer to be cut is etched by using the etching process in the subsequent process, the wafer to be cut can be stopped on the stop layer in time, and the etching of the stop layer is reduced.
It should be noted that the second preset value given herein is only an exemplary demonstration and is not used to limit the etching selection ratio between the wafer to be cut and the stop layer in the embodiment of the present disclosure. In practical application, the etching selection ratio of the wafer to be cut and the stop layer is only required to be controlled, so that the influence on the stop layer when the wafer to be cut is etched is within an acceptable range.
In some embodiments, the stop layer has a thickness T along the first direction, and 0.5 μm ≦ T ≦ 5 μm.
Here, the thickness of the stop layer in the first direction may be understood as a thickness in the Y-axis direction shown in the drawings of the present disclosure.
It can be understood that, since there is a certain degree of Over-etching (OE, over Etch) during the etching process, and the amount of Over-etching during the etching process is related to the thickness of the film to be etched, specifically: under the condition that the ratio R of the over-etching amount to the thickness of the etched film layer is a certain value, the thicker the thickness of the etched film layer is, the larger the over-etching amount is; and the thinner the thickness of the etched film layer is, the smaller the over-etching amount is. In some specific examples, the thickness of the wafer to be cut in the first direction is much greater than the thickness of the stop layer in the first direction. Under the condition that the R of the wafer to be cut is controlled to be equal to the R of the stop layer, the over-etching amount of the wafer to be cut is far larger than that of the stop layer because the thickness of the wafer to be cut is far larger than that of the stop layer, namely the over-etching time of the wafer to be cut is far larger than that of the stop layer. Under the condition of no stop layer, due to the fact that the over-etching amount of the wafer to be cut is large, the over-etching time is long, under the protection of the stop layer, the protective layer can be exposed in the plasma atmosphere for a long time due to the long-time over-etching of the wafer to be cut, and the protective layer is damaged greatly; in the embodiment of the disclosure, the stop layer is added, and the thickness of the stop layer is much smaller than that of the wafer to be cut, because the thickness of the stop layer is relatively smaller, the over-etching amount of the stop layer is relatively smaller, so that the over-etching time of the stop layer is relatively shorter, the time of the protective layer exposed in the plasma atmosphere can be shortened, and the influence of the over-etching on the protective layer can be reduced.
It should be noted that the thickness range of the stop layer along the first direction given above is only an exemplary example, and is not used to limit the thickness range of the stop layer along the first direction in the present disclosure. In setting the thickness of the stop layer in the first direction, two factors need to be considered: on one hand, the thickness of the stop layer along the first direction cannot be too thick, if the thickness of the stop layer is too thick, under the condition that R is certain, the over-etching amount of the stop layer is larger, the over-etching time is longer, and thus the protective layer is exposed in the plasma atmosphere for a longer time, and the protective layer is damaged greatly; on the other hand, the thickness of the stop layer along the first direction cannot be too thin, the over-etching time of the wafer to be cut is longer due to the thicker thickness of the wafer to be cut on the stop layer, and if the stop layer is too thin, the stop layer may be cut through in the over-etching process of the wafer to be cut. In practical applications, the above two factors may be considered together, so that the thickness of the stop layer along the first direction is set within an acceptable range.
In some embodiments, the material of the stop layer 102 includes silicon oxide, silicon nitride.
In step S1300, as shown in fig. 7, the protective layer 103 is mainly formed on the stop layer 102.
In some embodiments, the material of the protective layer 103 includes a UV film, a blue film.
Here, the protection layer 103 may prevent chips from being scattered while the cut wafer 101 is completely separated after the cut wafer 101 is cut. Here, the protective layer 103 is an organic material.
In some specific examples, as shown in fig. 7, a metal frame 113 surrounding the wafer to be cut is formed at the bottom of the wafer to be cut, and the metal frame 113 can be used for supporting the wafer to be cut. The wafer to be cut is carried on the upper portion of the metal frame 113, and the bottom of the metal frame 113 is adhered with the protective layer 103. The material of the metal frame 113 includes, but is not limited to, iron.
In some embodiments, as shown in fig. 7, the method further comprises: after forming the protection layer 103 on the stop layer 102, the carrier layer 106 is removed.
In some specific examples, the formation of the protection layer 103 may be performed with the wafer 101 to be cut facing upward, and the removal of the carrier layer 106 may be performed after the formation of the metal frame 113 and the formation of the protection layer 103, which may improve the problem that the wafer is not well supported and damaged.
In some specific examples, the method for removing the carrier layer 106 includes, but is not limited to, chemical mechanical polishing, wet etching, and dry etching.
In step S1400, the wafer 101 to be cut is cut mainly from the front side.
In some specific examples, as shown in fig. 8, before the wafer 101 to be cut is cut from the front side, the method further includes: forming a laser protection liquid 112 on the redistribution layer 107 of the wafer 101 to be cut from the front surface, where the laser protection liquid 112 is used to protect the redistribution layer 107 and the wafer 101 to be cut from being damaged by laser in a subsequent laser cutting process, the protection liquid may absorb heat, for example, absorb heat generated in the laser cutting process, and the laser protection liquid 112 may be liquid glue.
In some specific examples, as shown in fig. 8, when the laser protection solution 112 is formed on the redistribution layer 107 of the wafer 101 to be cut, the laser protection solution 112 is also formed on the protection layer 103 with the exposed surface between the stop layer 102 and the metal frame 113, so that the protection layer 103 is not damaged by laser in the subsequent laser cutting process.
In some embodiments, as shown in fig. 9, the method further comprises: removing part of the redistribution layer 107 from the front side to form a third groove 108 before dicing the wafer to be diced 101 from the front side; the third groove 108 exposes the wafer 101 to be cut.
In some embodiments, the redistribution layer 107 has dicing streets formed therein; the removing of the portion of the redistribution layer 107 from the front side includes:
along the cutting path of the redistribution layer 107, a part of the redistribution layer 107 is removed.
In some specific examples, a dicing street pad 111 is formed in a dicing street in the redistribution layer 107; the removing of the portion of the redistribution layer 107 from the front side includes:
and removing part of the rewiring layer 107 along the cutting path pad 111 of the rewiring layer 107.
It should be noted that the specific position of the removed partial redistribution layer 107 provided above is merely an exemplary example, and is not used to limit the specific cutting position of the redistribution layer 107 in the embodiment of the present disclosure, and the specific position of the removed partial redistribution layer mentioned in the embodiment of the present disclosure may be any position of a cutting street in the redistribution layer, and for example, the cutting may also be performed from a dielectric layer in the cutting street in the redistribution layer.
In some embodiments, said removing a portion of said redistribution layer 107 from said front side comprises:
a laser cutting process is used to remove portions of the redistribution layer 107 from the front side.
In some specific examples, after the redistribution layer 107 is cut by the laser cutting process, a residue, which is a dross formed in the third groove 108 after the laser cutting process, may be formed in the third groove 108, where the residue may affect the cleanliness and flatness of the hybrid bond section. In some specific examples, the method further comprises: and removing residues formed in the third groove 108 by adopting a wet etching process, a grinding process or a dry etching process so as to improve the flatness of the mixed bonding interface and facilitate the subsequent mixed bonding. Illustratively, the etchant used in the wet etching process has a high etching selectivity, i.e., the etching rate of the residues is much higher than the etching rate of the wafer to be cut, so as to avoid a large influence on the wafer to be cut 101.
Next, as shown in fig. 10, the wafer 101 to be cut is cut from the front surface to form a first groove 104, and the first groove 104 exposes the stop layer 102.
In some embodiments, the dicing the wafer to be diced 101 from the front side includes:
the wafer 101 to be cut is cut from the third groove 108 of the front side.
In some specific examples, the projections of the first groove 104 and the third groove 108 in the first plane coincide.
In some specific examples, the dicing the wafer to be diced 101 from the front side includes:
the wafer 101 to be diced is diced from the front side using a plasma dicing process.
In some specific examples, a scribe line is formed in the wafer 101 to be diced, and when the wafer 101 to be diced is diced from the front side, a scribe line of the wafer 101 to be diced is cut along to form a first groove 104.
In some specific examples, when the wafer to be cut is cut, a patterned photoresist layer may be formed on the front surface of the wafer to be cut, the patterned photoresist layer has an opening, and the position of the opening coincides with the projection of the third groove on the first plane.
In some specific examples, the plasma dicing process may be a Bosch process, which refers to a process that seeks to deposit an etch film on the etched lateral sidewalls in order to prevent or reduce lateral etching in integrated circuit manufacturing. The Bosch process firstly adopts fluorine-based active groups to etch silicon, then carries out side wall passivation, and the two processes of etching and passivation are alternately carried out. It realizes etching and edge wall passivation by alternately converting etching gas and passivation gas. Illustratively, the etching gas may be SF 6 The passivation gas may be C 4 F 8 。C 4 F 8 The carbon fluoride high molecular polymer can be formed in the plasma, and the formed carbon fluoride high molecular polymer can prevent the reaction of fluorine ions and silicon when deposited on the silicon surface. The etching and passivation are switched every 5 s-10 s for a period, and the silicon surface which is just etched is passivated after the isotropic etching in a short time. The passive film can be kept due to the physical sputtering bombardment of ions in the depth direction, so that the lateral etching cannot occur in the etching of the next period. By the periodic 'etching-passivation-etching', the width of a cutting path can be smaller, and the chip is favorable for micro-shrinkage.
In step S1500, as shown in fig. 11, a portion of the stop layer 102 is removed from the first groove 104 to form a second groove 105.
In some embodiments, the removing the portion of the stop layer 102 from the first recess 104 includes:
a portion of the stop layer 102 is removed from the first recess 104 using an etching process.
Here, the etching process includes, but is not limited to, dry etching, wet etching.
In some specific examples, the dry etching process may be a dry plasma etching process. The etch gas may be selected based on the particular material of the stop layer 102. For example, when the material of the stop layer 102 is silicon oxide or silicon nitride, the etching gas may be CF 4 Etc., or other etching gases known in the art that may be used to etch silicon oxide, silicon nitride.
In selecting the etching gas, it is necessary to consider that the etching rate of the etching gas etch stop layer 102 is much larger than that of the etching protective layer 103, so that the influence on the protective layer 103 can be reduced.
In some specific examples, the second groove 105 may be formed by continuing the dry etching process using the photoresist layer during the plasma cutting to form the first groove 104, and after the second groove 105 is formed, removing the patterned photoresist layer.
The embodiment of the disclosure provides a wafer cutting method, which includes: providing a wafer 101 to be cut; the wafer 101 to be cut comprises a front surface and a back surface which are opposite along a first direction, wherein the first direction is the thickness direction of the wafer 101 to be cut; forming a stop layer 102 on the back of the wafer 101 to be cut; forming a protective layer 103 on the stop layer 102; cutting the wafer 101 to be cut from the front surface to form a first groove 104, wherein the first groove 104 exposes the stop layer 102; a portion of the stop layer 102 is removed from the first recess 104 to form a second recess 105, and the second recess 105 exposes the protection layer 103. In the embodiment of the disclosure, the stop layer 102 is formed between the wafer 101 to be cut and the protective layer 103, so that the wafer 101 to be cut can stop on the stop layer when being cut, the problem that the protective layer 103 is damaged due to over-etching when the wafer 101 to be cut is solved, and the success rate of film expansion in the process of taking out a chip can be improved.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.
The scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (13)
1. A method of dicing a wafer, comprising:
providing a wafer to be cut; the wafer to be cut comprises a front surface and a back surface which are opposite along a first direction, wherein the first direction is the thickness direction of the wafer to be cut;
forming a stop layer on the back of the wafer to be cut;
forming a protective layer on the stop layer;
cutting the wafer to be cut from the front surface to form a first groove, wherein the stop layer is exposed out of the first groove;
and removing part of the stop layer from the first groove to form a second groove, wherein the second groove exposes the protective layer.
2. The method of claim 1, wherein an etch selectivity of the stop layer to the protective layer is greater than a first predetermined value.
3. The method according to claim 2, wherein the first preset value is 10:1.
4. the method of claim 1, wherein the stop layer comprises silicon oxide or silicon nitride, and the protective layer comprises UV film or blue film.
5. The method as claimed in claim 1, wherein the etching selection ratio of the wafer to be cut to the stop layer is greater than a second preset value.
6. The method according to claim 5, characterized in that said second preset value is 50:1.
7. the method of claim 1, wherein the stop layer has a thickness T in the first direction and 0.5 μm ≦ T ≦ 5 μm.
8. The method of claim 1, wherein said removing a portion of the stop layer from the first recess comprises:
and removing part of the stop layer from the first groove by using an etching process.
9. The method of claim 1, further comprising:
before a stop layer is formed on the back of the wafer to be cut, a bearing layer is formed on the front of the wafer to be cut;
and removing the bearing layer after forming the protective layer on the stop layer.
10. The method of claim 1, further comprising:
before a stop layer is formed on the back of the wafer to be cut, thinning the back of the wafer to be cut from the back of the wafer to be cut.
11. The method of claim 1, further comprising:
before a stop layer is formed on the back surface of the wafer to be cut, a rewiring layer is formed on the front surface of the wafer to be cut;
before the wafer to be cut is cut from the front surface, removing part of the rewiring layer from the front surface to form a third groove; the third groove exposes the wafer to be cut;
the dicing the wafer to be diced from the front side comprises:
and cutting the wafer to be cut from the third groove on the front surface.
12. The method of claim 11, wherein a dicing street is formed in the redistribution layer; the removing a portion of the redistribution layer from the front side includes:
and removing part of the rewiring layer along the cutting path of the rewiring layer.
13. The method of claim 11, wherein said removing a portion of said redistribution layer from said front side comprises:
and removing part of the rewiring layer from the front surface by using a laser cutting process.
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| CN117198915A (en) * | 2023-11-07 | 2023-12-08 | 粤芯半导体技术股份有限公司 | Method for monitoring wafer back surface process and method for preparing monitoring wafer |
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