CN111489966A - Method for cutting wafer - Google Patents
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- CN111489966A CN111489966A CN202010546548.1A CN202010546548A CN111489966A CN 111489966 A CN111489966 A CN 111489966A CN 202010546548 A CN202010546548 A CN 202010546548A CN 111489966 A CN111489966 A CN 111489966A
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- 238000005520 cutting process Methods 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000002313 adhesive film Substances 0.000 claims abstract description 54
- 239000003292 glue Substances 0.000 claims description 19
- 238000005498 polishing Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 9
- 238000003698 laser cutting Methods 0.000 claims description 7
- 239000002390 adhesive tape Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 162
- 239000010410 layer Substances 0.000 description 85
- 238000010586 diagram Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 239000012528 membrane Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021536 Zeolite Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- HNPSIPDUKPIQMN-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Al]O[Al]=O HNPSIPDUKPIQMN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910003471 inorganic composite material Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010457 zeolite Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for cutting a wafer. The method for cutting the wafer comprises the following steps of firstly, cutting the wafer along the precutting mark on the front surface of the wafer by using laser, wherein the depth of a cutting path cut by using the laser exceeds the final thickness of the wafer, then attaching a grinding adhesive film layer to the front surface of the wafer, grinding the back surface of the wafer attached with the grinding adhesive film layer, grinding the wafer to the final target thickness to separate chips from each other, attaching the adhesive film layer to the back surface of the ground wafer, fixing the ground wafer on a wafer frame through the adhesive film layer, and then removing the grinding adhesive film layer on the front surface of the wafer. And then, continuously cutting along the longitudinal and transverse cutting channels between the chips by using laser, cutting the adhesive film layer on the back of the wafer, and finally separating the adhesive film layer from the chips at a low temperature. The cutting method is used for cutting the ultrathin wafer, the problem of breakage is avoided during wafer cutting, and the yield of wafer cutting is improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for cutting a wafer.
Background
Integrated circuit chips are continuously developed towards high density, light weight and thin shape, and in order to meet the requirements, wafers need to be thinned and cut. The wafer thinning technology is a key technology for packaging the stacked chips, and the thickness of the chips is gradually thinned as the number of stacked layers of the chips is continuously increased.
At present, the traditional process flow of wafer thinning and cutting includes the process steps of blade half-cutting, front film pasting, back grinding, back film pasting, front film uncovering, wafer cutting and the like, wherein a cutting tool used in the wafer cutting process is a blade.
The inventor of the present application finds that, in the prior art, when a mechanical blade directly acts on the surface of a wafer to cut the wafer, stress damage is caused inside the wafer, and the wafer is prone to chipping during blade cutting.
Disclosure of Invention
The invention aims to provide a wafer cutting method, which is used in the cutting process of an ultrathin wafer, can effectively solve the problem of breakage during wafer cutting, and improves the yield of chips obtained by cutting the wafer.
The embodiment of the invention provides a method for cutting a wafer, which comprises the following steps:
s10 providing a wafer, the wafer comprising: the upper surface of the circuit layer is provided with a plurality of longitudinal pre-cutting marks and a plurality of transverse pre-cutting marks which are staggered in a # -shape;
s20, cutting the back of the wafer along the longitudinal pre-cuts and the transverse pre-cuts by using laser to obtain a plurality of longitudinal cutting channels and a plurality of transverse cutting channels, wherein the depths of the longitudinal cutting channels and the transverse cutting channels are greater than the final thickness of the wafer;
s30, attaching a grinding adhesive film layer on the upper surface of the cut circuit layer;
s40, grinding the back of the wafer attached with the grinding glue film layer to enable the wafer to reach the final thickness, and thus obtaining separated chips;
s50 attaching a film layer on the back of the ground wafer;
s60, fixing the wafer on the wafer frame through the adhesive film layer, and removing the grinding adhesive film layer on the circuit layer;
s70, cutting the adhesive film layer along the plurality of longitudinal cutting lanes and the plurality of transverse cutting lanes by using laser;
s80 separating the chip from the adhesive film layer at a low temperature.
In a possible solution, the material of the circuit layer is a material with a low dielectric constant.
In a possible solution, in the step S40, the method specifically includes:
s41, roughly grinding the back side of the wafer attached with the grinding glue film layer until the thickness of the wafer reaches the final wafer thickness of +60 μm;
s42, finely grinding the back surface of the roughly ground wafer until the thickness of the wafer reaches the final wafer thickness of +20 μm;
s43 polishing the back side of the wafer after finish grinding until the thickness of the wafer reaches the final wafer thickness.
In one possible scheme, the grinding adhesive film layer is a UV adhesive film;
the adhesive film layer is a cutting adhesive tape or a blue film.
In one possible embodiment, in the step S20, the power of the laser cutting is 1W to 3W.
In a possible scheme, the step S80 specifically includes: the chip is placed in a low-temperature container, and the temperature of the low-temperature container is-20 ℃ to-40 ℃.
In one possible approach, the final thickness of the wafer is 35 μm to 60 μm.
Based on the scheme, the wafer cutting method provided by the invention is characterized in that the wafer cutting process is improved, firstly, laser is used for cutting along pre-cutting marks on the front surface of the wafer, the depth of a cutting channel cut by the laser exceeds the final thickness of the wafer, then, a grinding glue film layer is attached to the front surface of the wafer, the back surface of the wafer attached with the grinding glue film layer is ground, the wafer is ground to the final target thickness, chips are separated from each other, the glue film layer is attached to the back surface of the ground wafer, the ground wafer is fixed on a wafer frame through the glue film layer, and then, the grinding glue film layer on the front surface of the wafer is removed. And then, continuously cutting along the longitudinal and transverse cutting channels between the chips by using laser, cutting the adhesive film layer on the back of the wafer, and finally separating the adhesive film layer from the chips at a low temperature. The method for cutting the wafer is used for cutting the ultrathin wafer, the problem of breakage cannot be caused during wafer cutting, and the yield of wafer cutting is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a process flow diagram of a method for dicing a wafer according to an embodiment of the invention;
FIG. 2 is a schematic view of a wafer according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a wafer according to an embodiment of the invention;
FIG. 4 is a schematic illustration of laser cutting in an embodiment of the present invention;
FIG. 5 is a diagram illustrating a wafer with a polishing pad layer attached thereon according to an embodiment of the present invention;
FIG. 6 is a schematic view of a polished wafer according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a wafer with an adhesive film layer attached thereon according to an embodiment of the invention;
fig. 8 is a schematic diagram of a wafer after the adhesive film layer is cut off in the embodiment of the invention.
Reference numbers in the figures:
100. a wafer; 101. a chip; 110. a circuit layer; 120. a semiconductor layer; 130. laser; 140. grinding the adhesive film layer; 150. a glue film layer; 160. and a wafer rack.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," and the like are used in the indicated orientations and positional relationships based on the drawings for convenience in describing and simplifying the description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention.
In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication connection; either directly or indirectly through intervening media, either internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a process flow diagram of a method for cutting a wafer according to an embodiment of the present invention, fig. 2 is a schematic diagram of a wafer according to an embodiment of the present invention, fig. 3 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention, fig. 4 is a schematic diagram of laser cutting according to an embodiment of the present invention, fig. 5 is a schematic diagram of a wafer with a polishing adhesive film layer attached thereto according to an embodiment of the present invention, fig. 6 is a schematic diagram of a polished wafer according to an embodiment of the present invention, fig. 7 is a schematic diagram of a wafer with an adhesive film layer attached thereto according to an embodiment of the present invention, and fig. 8 is a schematic diagram.
As shown in fig. 1, in the method for cutting a wafer according to the embodiment of the present invention, a process flow of wafer cutting includes the following steps:
s10, providing a wafer, the wafer comprising: the upper surface of the circuit layer is provided with a plurality of longitudinal pre-cutting marks and a plurality of transverse pre-cutting marks, the longitudinal pre-cutting marks are arranged on the wafer at equal intervals, the transverse pre-cutting marks are arranged on the wafer at equal intervals, and the longitudinal pre-cutting marks and the transverse pre-cutting marks are arranged in a staggered mode in a shape like a Chinese character jing.
Specifically, as shown in fig. 2 and fig. 3, the wafer 100 in the embodiment includes a circuit layer 110 and a semiconductor layer 120, wherein one side of the circuit layer 110 is a front side of the wafer 100, one side of the semiconductor layer 120 is a back side of the wafer 100, the thickness of the circuit layer 110 is about 10 μm, the semiconductor layer 120 is made of high-purity silicon, a plurality of longitudinal pre-cuts and a plurality of transverse pre-cuts are preset on an upper surface of the circuit layer 110 (i.e., the front side of the wafer 100), the longitudinal pre-cuts and the transverse pre-cuts are perpendicular to each other, that is, the plurality of longitudinal pre-cuts and the plurality of transverse pre-cuts are staggered in a zigzag manner on the upper surface of the circuit layer 110, and a plurality of uniformly distributed square chips 101 to be separated are formed on the front side of the wafer 100.
And S20, cutting the back of the wafer along the longitudinal pre-cuts and the transverse pre-cuts by using laser to obtain a plurality of longitudinal cutting lines and a plurality of transverse cutting lines, wherein the depths of the longitudinal cutting lines and the transverse cutting lines are greater than the final thickness of the wafer.
Specifically, as shown in fig. 4, a laser machine is used to cut the wafer 100 from the front surface of the wafer 100 along a plurality of longitudinal pre-cuts and a plurality of transverse pre-cuts to the back surface of the wafer 100 by a laser 130, so as to obtain a plurality of longitudinal streets and a plurality of transverse streets on the front surface of the wafer 100, and the depths of the longitudinal streets and the transverse streets are greater than the final thickness of the wafer 100 (chips). The cutting speed of the laser is fast, which is about 350mm/s on average, and the cutting stress generated when the wafer 100 is cut is extremely small due to the fast cutting speed of the laser, so that the defect of wafer breakage generated when the wafer is cut can be avoided.
S30, a grinding glue film layer is attached to the front surface of the cut wafer.
As shown in fig. 5, the polishing adhesive film layer 140 is attached to the surface of the circuit layer 110 on the front surface of the wafer 100, and the polishing adhesive film has a certain viscosity and is attached to the circuit layer 110 of the wafer, so as to prevent the wafer 100 from damaging the front surface of the wafer 100 in the subsequent polishing and thinning processes. When adhering, it is necessary to ensure that the polishing adhesive film layer 140 and the circuit layer 110 are tightly adhered, and no air bubbles exist between the polishing adhesive film layer 140 and the circuit layer 110.
S40, the back surface of the wafer with the adhesive film layer is polished to a final thickness, so as to obtain separated chips.
As shown in fig. 6, the back surface of the wafer 100 is ground by using a full-automatic thinning machine, so that the wafer 100 is gradually thinned until the final thickness of the wafer 100 (chip) is reached, and since the depths of the longitudinal streets and the transverse streets on the wafer 100 are greater than the final thickness of the wafer 100 (chip), after the wafer 100 is ground, the longitudinal streets and the transverse streets penetrate through the ground wafer, that is, the back surface of the ground wafer 100 is separated from each other, and at this time, the front surfaces of the wafer 100 are adhered together by the grinding glue film layer 140.
S50 a glue film layer is attached to the back surface of the polished wafer.
As shown in fig. 7, the adhesive film layer 150 is attached to the back surface of the wafer, i.e., the back surface of the semiconductor layer 120, and when the adhesive film layer 150 is attached to the semiconductor layer 120, the adhesive film layer 150 and the semiconductor layer 120 are tightly attached without bubbles and impurities, and the back surfaces of the wafers 100 separated from each other are bonded together again through the adhesive film layer 150.
S60 the wafer is fixed on the wafer rack through the film layer, and the grinding film layer on the front surface of the wafer is removed.
Specifically, the wafer 100 is fixed on the wafer frame 160 through the adhesive film layer 150, and since the polishing adhesive film layer 140 has a certain viscosity with the front surface of the wafer 100, when the polishing adhesive film layer 140 is removed, the polishing adhesive film layer 140 needs to be slowly lifted from one side of the polishing adhesive film layer 140, so as to avoid damage to the wafer.
And S70, cutting along the longitudinal cutting channels and the transverse cutting channels by using laser to cut off the adhesive film layer on the back of the wafer.
Specifically, as shown in fig. 8, the wafer 100 is cut again by the laser 130 from the front surface of the wafer 100 along the plurality of vertical streets and the plurality of horizontal streets to the back surface of the wafer 100 by using the laser machine, and the adhesive film layer 150 attached to the back surface of the wafer 100 is cut to obtain the chips (wafers) 101 separated from each other.
S80 separating the chip from the adhesive film layer at a low temperature.
Specifically, when the chips 101 separated from each other are placed in a low temperature environment, the adhesive layer 150 on the back surface of the chip 101 shrinks and becomes brittle at a low temperature and loses its adhesiveness, so that the adhesive layer 150 is easily peeled off from the chip 101, and a final chip is obtained.
It is not difficult to find that, in the method for cutting a wafer according to the embodiment, the wafer cutting process is improved, the wafer is firstly cut along the pre-cut mark on the front surface of the wafer by using laser, the depth of the cutting channel of the laser cutting exceeds the final thickness of the wafer, then the grinding glue film layer is attached to the front surface of the wafer, the back surface of the wafer attached with the grinding glue film layer is ground, the wafer is ground to the final target thickness, the chips are separated from each other, the glue film layer is attached to the back surface of the ground wafer, the ground wafer is fixed on the wafer frame through the glue film layer, and then the grinding glue film layer on the front surface of the wafer is removed. And then, continuously cutting along the longitudinal and transverse cutting channels between the chips by using laser, cutting the adhesive film layer on the back of the wafer, and finally separating the adhesive film layer from the chips at a low temperature. The method for cutting the wafer is used for cutting the ultrathin wafer, the problem of breakage cannot be caused during wafer cutting, and the yield of wafer cutting is improved.
Optionally, in the method for dicing a wafer in this embodiment, the material of the circuit layer on the front surface of the wafer is a material with a low dielectric constant (L ow K).
The circuit layer 110 on the front side of the wafer 100 is made of L ow K material, such as inorganic silicon oxide, silicon nitride, or organic polyimide, polyethylene, or even organic/inorganic composite materials such as silsesquioxane-based composite material, zeolite-based polyimide composite material, etc., L ow K material is used to replace silicon dioxide on the surface of the chip, which can further increase the speed of the chip, and the laser cutting L ow K circuit layer is adopted, so that the surface of the wafer will not be cracked or layered.
Optionally, in the step S40, the method for cutting a wafer in this embodiment specifically includes:
s41, rough grinding the back surface of the wafer with the polishing glue film layer until the thickness of the wafer reaches the final wafer thickness +60 μm, that is, the thickness of the wafer is roughly ground to have a margin of about 60 μm.
And S42, finely grinding the back surface of the wafer after rough grinding until the thickness of the wafer reaches the final wafer thickness of +20 μm, namely, the wafer is finely ground until the thickness of the wafer has a margin of about 20 μm.
S43 polishing the back surface of the wafer after finish grinding until the thickness of the wafer reaches the final wafer thickness, i.e. the wafer is made to reach the thickness of the final size by polishing.
Optionally, in the method for cutting a wafer in this embodiment, the polishing adhesive film layer attached to the front surface of the wafer is a UV adhesive film.
The adhesive film layer attached to the back of the wafer is a dicing tape or a blue film.
Adopt the UV glued membrane, can carry out UV (ultraviolet) to the UV membrane through the ultraviolet lamp when getting rid of and shine, the UV glued membrane after shining loses adhesive force, conveniently grinds the glued membrane layer and gets rid of from the circuit layer.
The adhesive film layer can be selected from a cutting adhesive tape or a blue film according to the size of the wafer to be cut.
Optionally, in the method for cutting a wafer in this embodiment, in step S20, the power of laser cutting is 1W to 3W.
Optionally, in the step S80, the method for cutting a wafer in this embodiment specifically includes: the chips which are separated from each other are placed in a low-temperature container, such as a deep cooling box, the temperature of the low-temperature container is controlled to be minus 20 ℃ to minus 40 ℃, and the adhesive film layer is completely separated from the chips after being shrunk and embrittled.
Optionally, in the method for cutting a wafer in this embodiment, the final thickness of the wafer is 35 μm to 60 μm.
By adopting the cutting method, the ultrathin wafer with the final thickness of 35-60 mu m can be cut, and the yield of the cut chips is ensured.
In the present invention, unless otherwise explicitly specified or limited, the first feature "on" or "under" the second feature may be directly contacting the first feature and the second feature or indirectly contacting the first feature and the second feature through an intermediate.
Also, a first feature "on," "above," and "over" a second feature may mean that the first feature is directly above or obliquely above the second feature, or that only the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lower level than the second feature.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for cutting a wafer is characterized by comprising the following steps:
s10 providing a wafer, the wafer comprising: the upper surface of the circuit layer is provided with a plurality of longitudinal pre-cutting marks and a plurality of transverse pre-cutting marks which are staggered in a # -shape;
s20, cutting the back of the wafer along the longitudinal pre-cuts and the transverse pre-cuts by using laser to obtain a plurality of longitudinal cutting channels and a plurality of transverse cutting channels, wherein the depths of the longitudinal cutting channels and the transverse cutting channels are greater than the final thickness of the wafer;
s30, attaching a grinding adhesive film layer on the upper surface of the cut circuit layer;
s40, grinding the back of the wafer attached with the grinding glue film layer to enable the wafer to reach the final thickness, and thus obtaining separated chips;
s50 attaching a film layer on the back of the ground wafer;
s60, fixing the wafer on the wafer frame through the adhesive film layer, and removing the grinding adhesive film layer on the circuit layer;
s70, cutting the adhesive film layer along the plurality of longitudinal cutting lanes and the plurality of transverse cutting lanes by using laser;
s80 separating the chip from the adhesive film layer at a low temperature.
2. The method as claimed in claim 1, wherein the circuit layer is made of a material with a low dielectric constant.
3. The method as claimed in claim 1, wherein the step S40 includes:
s41, roughly grinding the back side of the wafer attached with the grinding glue film layer until the thickness of the wafer reaches the final wafer thickness of +60 μm;
s42, finely grinding the back surface of the roughly ground wafer until the thickness of the wafer reaches the final wafer thickness of +20 μm;
s43 polishing the back side of the wafer after finish grinding until the thickness of the wafer reaches the final wafer thickness.
4. The method for cutting the wafer according to claim 1, wherein the polishing adhesive film layer is a UV adhesive film;
the adhesive film layer is a cutting adhesive tape or a blue film.
5. The method as claimed in claim 1, wherein in the step S20, the laser cutting power is 1W-3W.
6. The method as claimed in claim 1, wherein the step S80 includes: the chip is placed in a low-temperature container, and the temperature of the low-temperature container is-20 ℃ to-40 ℃.
7. The method as claimed in claim 1, wherein the final thickness of the wafer is 35 μm to 60 μm.
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| CN202010546548.1A CN111489966A (en) | 2020-06-15 | 2020-06-15 | Method for cutting wafer |
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| CN202010546548.1A CN111489966A (en) | 2020-06-15 | 2020-06-15 | Method for cutting wafer |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380613A (en) * | 2021-05-31 | 2021-09-10 | 紫光宏茂微电子(上海)有限公司 | Wafer thinning processing method |
| CN113410164A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Single-chip DAF adhesive tape die bonding method |
| CN113764267A (en) * | 2021-08-02 | 2021-12-07 | 苏州通富超威半导体有限公司 | Wafer thinning method |
| CN113764288A (en) * | 2021-08-02 | 2021-12-07 | 苏州通富超威半导体有限公司 | Chip packaging method and packaging structure |
| CN115050645A (en) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | Method for improving adhesive film residue on surface of wafer |
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