CN113764288A - Chip packaging method and packaging structure - Google Patents
Chip packaging method and packaging structure Download PDFInfo
- Publication number
- CN113764288A CN113764288A CN202110883836.0A CN202110883836A CN113764288A CN 113764288 A CN113764288 A CN 113764288A CN 202110883836 A CN202110883836 A CN 202110883836A CN 113764288 A CN113764288 A CN 113764288A
- Authority
- CN
- China
- Prior art keywords
- wafer
- chip
- layer
- circuit substrate
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
Abstract
The application discloses a chip packaging method and a chip packaging structure, wherein the chip packaging method comprises the following steps: providing a wafer, forming a cutting groove on the front surface of the wafer to form a plurality of packaging units, and forming a plurality of blind holes on the packaging units; forming a metal connecting wire in the blind hole; arranging a plurality of first salient points on the front surface of the wafer, wherein the first salient points are connected to one end of the metal connecting wire; providing a circuit substrate, inverting the front surface of the wafer, and connecting the front surface of the wafer and the circuit substrate through the first salient points; grinding the back of the wafer, wherein the grinding depth is the difference between the thickness of the wafer and the depth of the blind hole; and arranging a plurality of second salient points on the back surface of the wafer, wherein the second salient points are connected to the other end of the metal connecting line. According to the invention, the grinding layer of the wafer is accurately ground, so that the chip layer with a complete structure is formed, and the chip layer and the circuit substrate are favorably packaged.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip packaging method and a chip packaging structure.
Background
The wafer comprises a chip layer and a grinding layer, and the wafer thinning process is to grind the grinding layer material of the wafer and remove the material with a certain thickness.
In the related art, the wafer thinning process includes steps of forming a thinning line on the front surface and back grinding, and during the back grinding, the problem of hidden cracking of the chip layer exists because the chip layer is thin.
Therefore, in the chip packaging process, a large amount of defective products exist in the chip packaging due to the hidden cracking of the chip layer.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a chip packaging method and a chip packaging structure.
The application provides a chip packaging method, which comprises the following steps:
providing a wafer, forming a cutting groove on the front surface of the wafer to form a plurality of packaging units, and forming a plurality of blind holes on the packaging units;
forming a metal connecting wire in the blind hole;
arranging a plurality of first salient points on the front surface of the wafer, wherein the first salient points are connected to one end of the metal connecting wire;
providing a circuit substrate, inverting the front surface of the wafer, and connecting the front surface of the wafer and the circuit substrate through the first salient points;
grinding the back of the wafer, wherein the grinding depth is the difference between the thickness of the wafer and the depth of the blind hole;
and arranging a plurality of second salient points on the back surface of the wafer, wherein the second salient points are connected to the other end of the metal connecting line.
As an optional scheme, the providing a wafer, forming a cutting groove on the front surface of the wafer to form a plurality of packaging units, and forming a plurality of blind holes in the packaging units includes:
coating an etching layer on the front side of the wafer;
scribing an etching line on the etching layer;
forming a preset cutting groove along the etching line, wherein the etching layer is divided into a plurality of preset units by the preset cutting groove, and preset holes are formed in the preset units;
cutting along the preset cutting groove by using a laser process, wherein the preset unit forms the packaging unit;
and forming a blind hole along the preset hole by using a TVS process.
As an alternative, the cutting grooves comprise transverse cutting grooves and longitudinal cutting grooves which are perpendicular to each other, and the transverse cutting lines and the longitudinal cutting lines are arranged in a # -shaped manner.
As an optional scheme, the step of grinding the back side of the wafer to a grinding depth that is a difference between the thickness of the wafer and the depth of the blind via includes:
carrying out rough grinding on the grinding layer of the wafer;
carrying out fine grinding on the grinding layer of the wafer;
and polishing the grinding layer until the grinding layer is completely removed.
As an optional scheme, a plastic package protective layer is arranged between the circuit substrate and the front surface of the wafer, and a gap between the circuit substrate and the back surface of the wafer is filled with a plastic package protective layer material.
Optionally, the depth of the cutting groove is equal to the depth of the blind hole.
Alternatively, the metal connection line is formed by a deposition process.
The application provides a chip packaging structure, includes:
a circuit substrate; and
the chip layer is connected with the chip layer of the circuit substrate, the chip layer is provided with a plurality of chips, the surface of the chip facing the circuit substrate is provided with first salient points, the chip is connected with the circuit substrate through the first salient points, and the surface of the chip, which faces away from the circuit substrate, is provided with second salient points.
As an optional scheme, the wafer structure further comprises a plastic package protective layer arranged between the circuit substrate and the chip layer, and the plastic package protective layer is filled in a gap between the circuit substrate and the back of the wafer.
According to the invention, the grinding layer of the wafer is accurately ground, so that the subfissure of the chip layer is avoided, and the chip layer with a complete structure is formed, thereby being beneficial to the packaging of the chip layer and the circuit substrate; in addition, the second salient points are arranged on the chip layer and are used for being connected with other chips, so that the package in the vertical direction is increased, the structure is simple, and the manufacturing cost is low.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a flowchart of a chip packaging method according to an embodiment of the present invention;
fig. 2 to fig. 8 are schematic diagrams illustrating steps of a chip packaging method according to an embodiment of the present invention;
fig. 9 is a top view of a chip package structure according to an embodiment of the invention.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
As shown in fig. 1, an embodiment of the present application provides a flowchart of a chip packaging method, where the method includes the following steps:
s10, providing a wafer 10, forming a cutting groove 11 on the front surface of the wafer 10 to form a plurality of packaging units B, and forming a plurality of blind holes 12 on the packaging units B;
referring to fig. 2, it should be noted that the wafer 10 includes a chip layer 101 and a polishing layer 102, the wafer 10 has a thickness of at least 100 μm, and the chip layer 101 has a thickness of a desired chip thickness, typically 30 to 100 μm. The surface of the chip layer 101 facing away from the polishing layer 102 is defined as the front surface of the wafer 10, and the surface of the polishing layer 102 facing away from the chip layer 101 is defined as the back surface of the wafer 10. In some embodiments, a protective layer 20 may be applied to the front side of the wafer 10, as shown in fig. 2.
Step S10, specifically including the steps of:
s11, referring to fig. 2, an etching layer 30 is coated on the front surface of the wafer 10;
s12, scribing an etching line (not shown) on the etching layer 30;
the etching lines include vertical etching lines and horizontal etching lines perpendicular to each other, and the vertical etching lines and the horizontal etching lines are arranged in a cross shape.
S13, etching along the etching line to form a preset cutting groove 31, wherein the preset cutting groove divides the etching layer 30 into a plurality of preset units A, and preset holes 32 are formed in the preset units A;
referring to fig. 2, it should be noted that, according to the etching process, the etching layer 30 is etched along the horizontal etching line and the vertical etching line, a predetermined cutting groove 31 is formed on the etching layer 30, the predetermined cutting groove 31 includes a horizontal predetermined cutting groove (not shown) and a vertical predetermined cutting groove (not shown) that are perpendicular to each other, and the horizontal predetermined cutting groove and the vertical predetermined cutting groove divide the etching layer 30 into a plurality of predetermined units a. Meanwhile, a preset hole 32 is formed in the preset unit a. The depth of the predetermined cutting groove 31 and the predetermined hole 32 is the thickness of the etching layer 30.
S14, cutting along the preset cutting groove 31 by using a laser process to form a plurality of packaging units;
referring to fig. 3, it should be noted that, by using a laser machine, the dicing groove 11 is formed on the chip layer 101 by cutting along the preset dicing groove 31 with a laser. Specifically, the chip layer 101 is cut along the transverse preset cutting groove and the longitudinal preset cutting groove, so as to form the transverse cutting groove and the longitudinal cutting groove, and the preset unit a becomes the packaging unit B. Wherein, the depth of the cutting groove 11 is the required chip thickness. The chip layer 101 is cut by laser, so that cutting stress is small, and the packaging unit B is prevented from being hidden and cracked.
And S15, forming the blind holes 12 along the preset holes by using a TVS process.
Referring to fig. 3, it should be noted that, by using the TVS technology, the processing is continued along the position of the preset hole 32, that is, a plurality of blind holes 12 are formed in the package unit B, and the depth of the blind holes 12 is equal to the depth of the cutting groove 11, which is beneficial to realizing mutual independence between the package units B in subsequent steps. The blind hole 12 and the cut groove 11 can be processed simultaneously.
S20, forming a metal connecting line 41 in the blind hole 12;
referring to fig. 4, it is noted that the metal connection line 41 may be formed by a physical vapor deposition method or a chemical vapor deposition method. The melted metal material forms a conductive layer 40 on the front surface of the wafer 10, fills the blind holes 12, and forms metal connecting wires 41 after condensation. The metal material may be one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
S30, disposing a plurality of first bumps 50 on the front surface of the wafer 10, wherein the first bumps 50 are connected to one end of the metal connecting wires 41;
referring to fig. 5, it is to be noted that the first bump 50 is formed by a ball-mounting reflow process. The first bump 50 may be a ball or a block, and the material of the first bump 50 may be one or a mixture of copper, aluminum, nickel, gold, silver and titanium. One first bump 50 corresponds to one metal connection line 41, and the first bump 50 is connected to one end of the metal connection line 41.
S40, providing a circuit substrate 70, inverting the front surface of the wafer 10, and connecting the front surface of the wafer 10 and the circuit substrate 70 through the first bumps 50;
referring to fig. 6, the circuit board 70 is provided with a circuit. The first bumps 50 electrically connect the front side of the wafer 10 to the circuit substrate 70 by a flip chip bonding process.
S50, grinding the back of the wafer 10 to the depth of the difference between the thickness of the wafer 10 and the depth of the blind hole 12;
referring to fig. 6 and 7, it should be noted that the polishing depth is the thickness of the wafer 10 minus the depth of the blind via 12, i.e. the polishing layer 102 completely disappears and the blind via 12 becomes a through via. Adopting a grinding process, firstly, roughly grinding the grinding layer 102 of the wafer 10; then, the polishing layer 102 of the wafer 10 is finely polished; finally, the polishing process polishes the polishing layer 102 until the polishing layer 102 is completely removed. At this time, the package units B are independent of each other.
S60, a plurality of second bumps 80 are disposed on the back surface of the wafer 10, and the second bumps 80 are connected to the other ends of the metal connection lines 41.
Referring to fig. 8, it is to be noted that the second bump 80 is formed by a ball-mounting reflow process. The second bump 80 may be a ball or a block, and the material of the second bump 80 may be one or a mixture of copper, aluminum, nickel, gold, silver and titanium. One second bump 80 corresponds to one metal connection line 41, and the second bump 80 is connected to the other end of the metal connection line 41. The arrangement of the second salient points 80 is beneficial to connecting other chips, increasing the package in the vertical direction and realizing a three-dimensional package structure.
In another embodiment, between step S40 and step S50, there is further included the step of: and a plastic sealing protective layer 60 is arranged between the circuit substrate 70 and the front surface of the wafer 10, and the plastic sealing protective layer 60 is filled in a gap between the circuit substrate 70 and the front surface of the wafer 10.
Referring to fig. 7, it should be noted that the material of the plastic protection layer 60 may be polyimide, silicon gel, epoxy resin, curable polymer-based material, or curable resin-based material. The plastic-sealing protective layer 60 can be smoothly and rapidly filled in the gap between the circuit substrate 70 and the front surface of the wafer 10, and can effectively protect the electricity and the machinery.
Fig. 8 illustrates a front view of a chip packaging structure, and fig. 9 illustrates a top view of the chip packaging structure.
The 3D package structure includes a circuit substrate 70 and a chip layer 101 connected to the circuit substrate 70.
The chip layer 101 is formed by thinning the wafer 10. The chip layer 101 includes a plurality of packaging units B arranged in a matrix, one surface of each packaging unit B is electrically connected to the circuit substrate 70 through a first bump 50, and the other surface of each packaging unit B is provided with a second bump 80 for connecting to other chips, thereby realizing a three-dimensional packaging structure.
Based on the chip packaging method and the packaging structure, the grinding layer of the wafer is accurately ground, so that the hidden crack of the chip layer is avoided, the chip layer with a complete structure is formed, and the chip layer and the circuit substrate are favorably packaged; in addition, the second salient points are arranged on the chip layer and are used for being connected with other chips, so that the package in the vertical direction is increased, the structure is simple, and the manufacturing cost is low.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (9)
1. A chip packaging method is characterized by comprising the following steps:
providing a wafer, forming a cutting groove on the front surface of the wafer to form a plurality of packaging units, and forming a plurality of blind holes on the packaging units;
forming a metal connecting wire in the blind hole;
arranging a plurality of first salient points on the front surface of the wafer, wherein the first salient points are connected to one end of the metal connecting wire;
providing a circuit substrate, inverting the front surface of the wafer, and connecting the front surface of the wafer and the circuit substrate through the first salient points;
grinding the back of the wafer, wherein the grinding depth is the difference between the thickness of the wafer and the depth of the blind hole;
and arranging a plurality of second salient points on the back surface of the wafer, wherein the second salient points are connected to the other end of the metal connecting line.
2. The chip packaging method according to claim 1, wherein the step of providing a wafer, forming a cutting groove on the front surface of the wafer to form a plurality of packaging units, and forming a plurality of blind holes on the packaging units comprises:
coating an etching layer on the front side of the wafer;
scribing an etching line on the etching layer;
forming a preset cutting groove along the etching line, wherein the etching layer is divided into a plurality of preset units by the preset cutting groove, and preset holes are formed in the preset units;
cutting along the preset cutting groove by using a laser process, wherein the preset unit forms the packaging unit;
and forming a blind hole along the preset hole by using a TVS process.
3. The chip packaging method according to claim 2, wherein the dicing grooves comprise transverse dicing grooves and longitudinal dicing grooves perpendicular to each other, and the transverse dicing lines and the longitudinal dicing lines are arranged in a matrix.
4. The chip packaging method according to claim 1, wherein the step of grinding the back side of the wafer to a grinding depth which is a difference between the thickness of the wafer and the depth of the blind via comprises:
carrying out rough grinding on the grinding layer of the wafer;
carrying out fine grinding on the grinding layer of the wafer;
and polishing the grinding layer until the grinding layer is completely removed.
5. The chip packaging method according to claim 1, wherein a plastic protection layer is disposed between the circuit substrate and the front surface of the wafer, and a material of the plastic protection layer is filled in a gap between the circuit substrate and the back surface of the wafer.
6. The chip packaging method according to claim 1, wherein the depth of the cutting groove is equal to the depth of the blind hole.
7. The chip packaging method according to claim 1, wherein the metal connection line is formed by a deposition process.
8. A chip package structure, comprising:
a circuit substrate; and
the chip layer is connected with the chip layer of the circuit substrate, the chip layer is provided with a plurality of chips, the surface of the chip facing the circuit substrate is provided with first salient points, the chip is connected with the circuit substrate through the first salient points, and the surface of the chip, which faces away from the circuit substrate, is provided with second salient points.
9. The chip package structure according to claim 8, further comprising a plastic package protective layer disposed between the circuit substrate and the chip layer, wherein a gap between the circuit substrate and the back surface of the wafer is filled with a plastic package protective layer material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110883836.0A CN113764288A (en) | 2021-08-02 | 2021-08-02 | Chip packaging method and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110883836.0A CN113764288A (en) | 2021-08-02 | 2021-08-02 | Chip packaging method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113764288A true CN113764288A (en) | 2021-12-07 |
Family
ID=78788366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110883836.0A Pending CN113764288A (en) | 2021-08-02 | 2021-08-02 | Chip packaging method and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113764288A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226058A1 (en) * | 2022-05-23 | 2023-11-30 | 常州银河世纪微电子股份有限公司 | Chip size package process |
Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101002307A (en) * | 2004-07-16 | 2007-07-18 | 株式会社瑞萨科技 | Method for manufacturing semiconductor integrated circuit device |
| CN101587842A (en) * | 2008-05-21 | 2009-11-25 | 欣兴电子股份有限公司 | Chip packaging support plate and manufacture method thereof |
| US7863092B1 (en) * | 2008-09-30 | 2011-01-04 | Xilinx, Inc. | Low cost bumping and bonding method for stacked die |
| US20110068444A1 (en) * | 2009-09-23 | 2011-03-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP |
| US20120309130A1 (en) * | 2011-06-02 | 2012-12-06 | Infineon Technologies Ag | Method of Manufacturing a Semiconductor Device |
| CN103000542A (en) * | 2011-09-16 | 2013-03-27 | 南茂科技股份有限公司 | Solder cap bump in semiconductor package and method of manufacturing the same |
| US20140084456A1 (en) * | 2012-09-27 | 2014-03-27 | Myun-sung Kang | Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages |
| US20150270220A1 (en) * | 2014-03-19 | 2015-09-24 | SK Hynix Inc. | Semiconductor devices having through electrodes and methods of manufacturing the same |
| US20150279798A1 (en) * | 2014-03-28 | 2015-10-01 | SK Hynix Inc. | Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same |
| US20160086902A1 (en) * | 2014-09-24 | 2016-03-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and manufacturing method thereof |
| US9514988B1 (en) * | 2015-07-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and packaging methods thereof |
| CN106876333A (en) * | 2017-03-28 | 2017-06-20 | 华进半导体封装先导技术研发中心有限公司 | The preparation method and wafer level packaging structure of a kind of wafer level packaging structure |
| CN107240552A (en) * | 2017-05-24 | 2017-10-10 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer packaging method and structure |
| CN107579042A (en) * | 2016-07-04 | 2018-01-12 | 株式会社迪思科 | The processing method of chip |
| CN109599380A (en) * | 2013-07-10 | 2019-04-09 | 台湾积体电路制造股份有限公司 | Die assemblies and its manufacturing method on intermediary layer with dam structure |
| CN110364445A (en) * | 2019-06-03 | 2019-10-22 | 苏州通富超威半导体有限公司 | Bonding semiconductor packaging method |
| CN111489966A (en) * | 2020-06-15 | 2020-08-04 | 紫光宏茂微电子(上海)有限公司 | Method for cutting wafer |
| WO2021119924A1 (en) * | 2019-12-16 | 2021-06-24 | 华为技术有限公司 | Chip stack structure and manufacturing method therefor |
-
2021
- 2021-08-02 CN CN202110883836.0A patent/CN113764288A/en active Pending
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101002307A (en) * | 2004-07-16 | 2007-07-18 | 株式会社瑞萨科技 | Method for manufacturing semiconductor integrated circuit device |
| CN101587842A (en) * | 2008-05-21 | 2009-11-25 | 欣兴电子股份有限公司 | Chip packaging support plate and manufacture method thereof |
| US7863092B1 (en) * | 2008-09-30 | 2011-01-04 | Xilinx, Inc. | Low cost bumping and bonding method for stacked die |
| US20110068444A1 (en) * | 2009-09-23 | 2011-03-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP |
| US20120309130A1 (en) * | 2011-06-02 | 2012-12-06 | Infineon Technologies Ag | Method of Manufacturing a Semiconductor Device |
| CN103000542A (en) * | 2011-09-16 | 2013-03-27 | 南茂科技股份有限公司 | Solder cap bump in semiconductor package and method of manufacturing the same |
| US20140084456A1 (en) * | 2012-09-27 | 2014-03-27 | Myun-sung Kang | Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages |
| CN109599380A (en) * | 2013-07-10 | 2019-04-09 | 台湾积体电路制造股份有限公司 | Die assemblies and its manufacturing method on intermediary layer with dam structure |
| US20150270220A1 (en) * | 2014-03-19 | 2015-09-24 | SK Hynix Inc. | Semiconductor devices having through electrodes and methods of manufacturing the same |
| US20150279798A1 (en) * | 2014-03-28 | 2015-10-01 | SK Hynix Inc. | Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same |
| US20160086902A1 (en) * | 2014-09-24 | 2016-03-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and manufacturing method thereof |
| US9514988B1 (en) * | 2015-07-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and packaging methods thereof |
| CN107579042A (en) * | 2016-07-04 | 2018-01-12 | 株式会社迪思科 | The processing method of chip |
| CN106876333A (en) * | 2017-03-28 | 2017-06-20 | 华进半导体封装先导技术研发中心有限公司 | The preparation method and wafer level packaging structure of a kind of wafer level packaging structure |
| CN107240552A (en) * | 2017-05-24 | 2017-10-10 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer packaging method and structure |
| CN110364445A (en) * | 2019-06-03 | 2019-10-22 | 苏州通富超威半导体有限公司 | Bonding semiconductor packaging method |
| WO2021119924A1 (en) * | 2019-12-16 | 2021-06-24 | 华为技术有限公司 | Chip stack structure and manufacturing method therefor |
| CN111489966A (en) * | 2020-06-15 | 2020-08-04 | 紫光宏茂微电子(上海)有限公司 | Method for cutting wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226058A1 (en) * | 2022-05-23 | 2023-11-30 | 常州银河世纪微电子股份有限公司 | Chip size package process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8030769B2 (en) | Grooving bumped wafer pre-underfill system | |
| US8803332B2 (en) | Delamination resistance of stacked dies in die saw | |
| US8557684B2 (en) | Three-dimensional integrated circuit (3DIC) formation process | |
| JP2008235401A (en) | Semiconductor device and manufacturing method therefor | |
| KR100738730B1 (en) | Semiconductor device production method and semiconductor | |
| US10515837B2 (en) | Method of wafer bonding of dissimilar thickness die | |
| EP1094511A2 (en) | Low profile integrated circuit packages | |
| WO2001015223A1 (en) | Semiconductor device and method of manufacture thereof | |
| US6309954B1 (en) | Methods of forming flip chip bumps and related flip chip bump constructions | |
| JP4342832B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20170294367A1 (en) | Flat No-Leads Package With Improved Contact Pins | |
| CN113764288A (en) | Chip packaging method and packaging structure | |
| US8652939B2 (en) | Method and apparatus for die assembly | |
| CN106531638B (en) | Semiconductor device including stacked semiconductor bare chip and method of manufacturing the same | |
| KR102261309B1 (en) | Electronic component and its manufacturing method and electronic component manufacturing apparatus | |
| GB2362759A (en) | Non Planar Surface for Semiconductor Chips | |
| JP4528758B2 (en) | Transfer tape and semiconductor device manufacturing method using the transfer tape | |
| CN112908935A (en) | Method for producing an electronic chip | |
| CN110416141A (en) | The method for forming semiconductor package body | |
| US11551973B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US11610855B2 (en) | Chip packaging method and package structure | |
| US20170011979A1 (en) | Chip Scale Package | |
| CN112786542A (en) | Semiconductor package and method of manufacturing the same | |
| JP3917121B2 (en) | Manufacturing method of semiconductor device | |
| JP2002299547A (en) | Laminated semiconductor device and manufacturing method thereor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |