WO2021119924A1

WO2021119924A1 - Chip stack structure and manufacturing method therefor

Info

Publication number: WO2021119924A1
Application number: PCT/CN2019/125668
Authority: WO
Inventors: 张晓东; 李珩; 王思敏; 戚晓芸; 王正波; 牛瑞
Original assignee: 华为技术有限公司
Priority date: 2019-12-16
Filing date: 2019-12-16
Publication date: 2021-06-24
Also published as: CN114762103A

Abstract

A chip stack structure and a manufacturing method therefor, the chip stack structure comprising a first die (100) and a second die (200), a first re-wiring layer (130) of the first die being provided with an exposed first bonding pad (133), the first re-wiring layer (130) and the first bonding pad (133) of the first die (100) being directly bonded to a passive plane (220) of the second die (200) without the need to prepare an additional dielectric layer on the bonding surface, reducing the thickness of the first die (100) and second die (200) after stacking such that the size of the chip after encapsulation is smaller, lighter, and thinner. The thermal resistance of the first die (100) and second die (200) after direct stacking is lower, improving the heat dissipation performance of the chip. In addition, the second die (200) is also provided with a through-silicon via (233) connected to the first bonding pad (133), enabling the first die (100) and the second die (200) to be directly electrically interconnected by means of the through-silicon via, the reliability of the connection being strong. The provided method for manufacturing the chip stack structure has simple processing steps and has no etching selectivity ratio problem, greatly increasing the achievability.

Description

Chip stack structure and manufacturing method thereof

Technical field

This application relates to the technical field of chip packaging, and in particular to a chip stacking structure and a manufacturing method thereof.

Background technique

Chip packaging, also known as integrated circuit packaging, is a process of placing the produced wafer Die on a substrate that plays a role of bearing, leading out the pins, and then fixing the package as a whole. Among them, the three-dimensional integrated circuit (3D IC) packaging technology is the vertical stacking of multi-layer wafers in three-dimensional space to form a single integrated packaging technology. 3D IC packaging technology can cope with the electronic and material impact of the semiconductor manufacturing process. The problem of physical limitations saves chip space.

At present, in 3D IC packaging technology, the vertical stacking of chips generally requires an additional dielectric layer to be prepared on the surfaces of the two wafers that are in contact with each other, and the two wafers are integrated through the silicon fusion bonding of the dielectric layer. Then, through silicon vias through the wafer and the dielectric layer are prepared to electrically connect the two wafers. Generally speaking, the thickness of the dielectric layer for bonding additionally prepared for each wafer can reach 1 micron to 5 microns. Therefore, the stacking of two layers of wafers will increase the thickness of the chip by an additional 2 microns to 10 microns. Micron, when the number of layers of the wafer stack increases, the additional thickness of the chip will also increase, and finally the package size of the chip will become larger.

Summary of the invention

The present application provides a chip stack structure and a manufacturing method thereof, which can reduce the stack thickness of the chip, improve the reliability of the electrical connection of the wafer and the heat dissipation performance, and the manufacturing process is simple.

In order to achieve the above objectives, the following technical solutions can be adopted in this application:

In a first aspect, the present application provides a chip stack structure, which includes: a first wafer, the active surface of the first wafer is provided with a first rewiring layer; a plurality of first bonding pads, a plurality of second A bonding pad is exposed on the surface of the first rewiring layer parallel to the first wafer, a plurality of first bonding pads are electrically connected to the metal wiring of the first rewiring layer; the second wafer, the second wafer and The first wafer is stacked, and the passive surface of the second wafer is bonded to the first rewiring layer and a plurality of first bonding pads; the second wafer is provided with a plurality of through silicon vias, each through silicon via One end of the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads.

The chip stack structure provided by the present application includes a first wafer and a second wafer. The first rewiring layer of the first wafer is provided with a bare first bonding pad, the first rewiring layer of the first wafer and The first bonding pad and the passive surface of the second wafer are directly bonded and connected, without the need to prepare an additional dielectric layer on the bonding surface, which reduces the thickness of the first wafer and the second wafer after stacking, so that After the chip is packaged, the size is smaller, lighter and thinner.

With reference to the first aspect, in a possible design manner, the structure further includes: a plurality of second bonding pads, the plurality of second bonding pads are exposed on the surface of the first rewiring layer parallel to the first wafer , The plurality of second bonding pads are bonded to the passive surface of the second wafer, and the plurality of second bonding pads are electrically connected to the metal wiring of the first rewiring layer. According to the above structure, the first rewiring layer and the first bonding pad of the first wafer are directly bonded to the passive surface of the second wafer, so that the thermal resistance between the first wafer and the second wafer is increased. Small, heat can be directly transferred between the first wafer and the second wafer; and the second bonding pad can also be used as a heat conduction structure between wafers in this application, which can further reduce the heat between the wafers. It can improve the heat transfer efficiency between wafers and improve the heat dissipation performance after chip packaging.

In combination with the first aspect, in a possible design, the active surface of the second wafer is provided with a second rewiring layer, and the second rewiring layer is provided with a plurality of metal pads, a plurality of metal pads and a second rewiring layer. The metal wiring of the secondary wiring layer is electrically connected; one end of each silicon through hole located on the active surface of the second wafer is connected to at least one of the plurality of metal pads. As a result, the through silicon via is directly connected to the first bonding pad and the metal pad without passing through the dielectric layer, avoiding the problem of etching selection ratio, and improving the reliability of the electrical connection between the first wafer and the second wafer Sex.

In combination with the first aspect, in a possible design manner, each through silicon hole is filled with a metal filler, and the metal filler is used to electrically connect the first bonding pad to which it is connected to the metal pad.

In combination with the first aspect, in a possible design method, the metal filler is obtained by sputtering on the inner surface of the through silicon hole to form a seed layer connected to the first bonding pad, and performing metal electroplating on the surface of the seed layer .

With reference to the first aspect, in a possible design, the passive surface of the second wafer is provided with a first dielectric layer, and the passive surface of the second wafer passes through the first dielectric layer and the first rewiring layer , The plurality of first bonding pads and the plurality of second bonding pads are connected by bonding. The first dielectric layer can be made of high thermal conductivity materials, such as silicon carbide, diamond, graphene or silicon nitride, etc., to reduce the thermal resistance between the first wafer and the second wafer, and improve the heat dissipation performance after the chip is packaged .

In a second aspect, the present application provides a method for manufacturing a chip stack structure. The method includes: preparing a first rewiring layer and a plurality of first bonding pads on an active surface of a first wafer, and a plurality of first bonds The bonding pads are exposed on the surface of the first rewiring layer parallel to the first wafer, and a plurality of first bonding pads are electrically connected with the metal wiring of the first rewiring layer; the passive surface of the second wafer is connected to the first rewiring layer. The repeated wiring layer is bonded and connected to a plurality of first bonding pads; a plurality of through silicon vias are formed by etching on the second wafer, and one end of each through silicon via located on the passive surface of the second wafer is connected to a plurality of At least one of the first bonding pads is connected.

The manufacturing method of the chip stack structure provided in the present application directly bonds and connects the first rewiring layer of the first wafer and the passive surface of the second wafer, so there is no need to prepare an additional dielectric layer on the bonding surface or The use of solder balls can reduce the thickness of the first wafer and the second wafer after stacking at least by the thickness of the additional dielectric layer, so that the size of the chip after packaging is smaller, lighter and thinner.

With reference to the second aspect, in a possible design method, preparing the first rewiring layer and the plurality of first bonding pads on the active surface of the first wafer includes: preparing the active surface of the first wafer The first rewiring layer whose thickness is greater than the preset target thickness, and the multiple first bonding pads hidden in the first rewiring layer; through material removal processing, the first rewiring layer is thinned to the target thickness to make multiple The first bonding pad is exposed on the surface of the first rewiring layer parallel to the first wafer. Since the first bonding pad in this application does not need to be connected to the solder balls, there is no need to precisely control the depth of the dish in the process of removing material, as long as the expansion margin is retained, thereby improving the process control Feasibility, so that production costs are reduced.

With reference to the second aspect, in a possible design manner, the method further includes: preparing a plurality of second bonding pads hidden in the first rewiring layer on the active surface of the first wafer; When the wiring layer is thinned to the target thickness, the plurality of second bonding pads are exposed on the surface of the first rewiring layer. According to the above method, the first rewiring layer and the first bonding pad of the first wafer are directly bonded to the passive surface of the second wafer, so that the thermal resistance between the first wafer and the second wafer is improved. Small, heat can be directly transferred between the first wafer and the second wafer; and the second bonding pad can also be used as a heat conduction structure between wafers in this application, which can further reduce the heat between the wafers. It can improve the heat transfer efficiency between wafers and improve the heat dissipation performance after chip packaging.

In combination with the second aspect, in a possible design method, a plurality of through silicon vias are formed in the second wafer by etching, and an end of each through silicon via located on the passive surface of the second wafer is connected with the plurality of first through silicon vias. At least one connection in the bonding pad includes: determining the projection position of at least one first bonding pad on the active surface of the second wafer; perpendicular to the active surface of the second wafer, starting from the projection position to the first The through silicon hole is formed by etching in the direction of the bonding pad until the through silicon hole is in contact with the at least one first bonding pad. Therefore, the method provided by the present application does not generate additional dielectric etching during the process of etching through silicon vias, and only etches the silicon of the wafer body, and does not need to select the etching selection ratio for different materials, and avoids The problem of the formation of fin-shaped etching morphology and drum-shaped etching morphology in the dielectric layer due to the inappropriate etching selection ratio, so that the continuity of the seed layer and the metal filler is ensured, and the first wafer and the first wafer are improved. The reliability of the connection between the two wafers.

With reference to the second aspect, in a possible design manner, the method further includes: preparing a second rewiring layer on the active surface of the second wafer, and the second rewiring layer is provided with a plurality of metal pads, and The metal pads are electrically connected to the metal wiring of the second rewiring layer; one end of each through silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pads. Therefore, the through silicon via is directly connected to the first bonding pad and the metal pad without passing through the dielectric layer, which improves the electrical connection reliability of the first wafer and the second wafer.

With reference to the second aspect, in a possible design manner, the method further includes: forming a seed layer connected to the first bonding pad by surface sputtering on the inner surface of the through silicon hole; and performing metal plating on the surface of the seed layer A metal filler is formed, and the metal filler electrically connects the first bonding pad with the metal pad. According to the above method, the TSV does not need to pass through the dielectric layer during etching, and the fin-shaped etching morphology and the drum-shaped etching morphology will not be generated due to the problem of the etching selection ratio. Therefore, the through-silicon hole does not need to pass through the dielectric layer. The seed layer on the surface can have good coverage continuity, so that the metal filler can be continuously and fully filled into the through silicon hole, and the metal filler can ensure that the first wafer and the second wafer can form a reliable electrical connection.

In combination with the second aspect, in a possible design method, bonding the passive surface of the second wafer to the first rewiring layer and multiple first bonding pads includes: A first dielectric layer is prepared on the source surface; the first dielectric layer is bonded and connected with the first rewiring layer, the first bonding pad and the second bonding pad. The first dielectric layer can be made of a material with high thermal conductivity, such as silicon carbide, diamond, graphene, or silicon nitride. In order to reduce the thermal resistance between the first wafer and the second wafer, the heat dissipation performance after the chip packaging is improved.

In a third aspect, the present application provides an electronic device that includes a printed circuit board (PCB) and at least one computer chip provided on the printed circuit board, wherein part of the at least one computer chip is Or all have the chip stack structure as in the above-mentioned first aspect and any design manner thereof.

Description of the drawings

Figure 1 is a schematic diagram of a chip stacking structure;

Figure 2 Schematic diagram of fin-type etching morphology and drum-type etching morphology;

Figure 3 is a schematic diagram of another chip stacking structure;

4 is an exploded view of the chip stack structure provided by Embodiment 1 of the present application;

5 is a cross-sectional view of the stacked state of the first wafer and the second wafer;

FIG. 6 is an exploded view of another chip stack structure provided by Embodiment 1 of the present application;

FIG. 7 is a cross-sectional view of the stacked state of the first wafer and the second wafer;

FIG. 8 is an exploded view of another chip stack structure provided by Embodiment 1 of the present application;

FIG. 9 is an exploded view of a multi-layer chip stack structure shown in an embodiment of the present application;

10 is a cross-sectional view of a multi-layer chip stack structure shown in an embodiment of the present application;

FIG. 11 is a schematic structural diagram of an integrated chip shown in an embodiment of the present application;

FIG. 12 is a schematic diagram of step S101 of a manufacturing method of a chip stack structure provided by an embodiment of the present application; FIG.

FIG. 13 is a schematic diagram of step S101 of a method for manufacturing a chip stack structure according to an embodiment of the present application;

FIG. 14 is a schematic diagram of step S102 of a method for manufacturing a chip stack structure according to an embodiment of the present application;

15 is a schematic diagram of step S103 of a method for manufacturing a chip stack structure provided by an embodiment of the present application;

FIG. 16 is a schematic diagram of step S104 of a method for manufacturing a chip stack structure provided by an embodiment of the present application; FIG.

FIG. 17 is a schematic diagram of step S102 of a method for manufacturing a chip stack structure provided by an embodiment of the present application.

Detailed ways

Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present embodiment, unless otherwise specified, "plurality" means two or more.

Chips are important components in various electronic devices, and the product performance of electronic devices largely depends on the performance of the chip. In order to adapt to the rapid development of graphics computing, neural network (NN), artificial intelligence (AI), cloud computing, high-performance computing cluster (HPCC) and other technologies, in recent years In the past, the process of the chip has been continuously improved, and the number of transistors has been continuously increased. Therefore, the performance of the chip has been continuously enhanced, and the operating power consumption has also increased accordingly. However, due to the development trend of high-performance, multi-function, high reliability, high integration, miniaturization, and thinning of electronic equipment, the integration of electronic equipment is getting higher and higher, and the space in the fuselage becomes more and more inches. Inch gold, which makes all kinds of chips need to have high performance while also having a smaller volume. This demand poses a challenge to chip packaging.

Chip packaging, also known as integrated circuit packaging, is a process of placing the produced wafer Die on a substrate that plays a role of bearing, leading out the pins, and then fixing the package as a whole. In the embodiments of this application, a wafer may also be called a bare die, a bare chip, or a bare chip. It is a small unpackaged integrated circuit body made of semiconductor materials. The established function of the integrated circuit is in this Realized on a small piece of semiconductor. At present, in order to improve chip integration and reduce chip volume, some more advanced chip packaging methods have been proposed. Among them, three-dimensional integrated circuit (3D IC) packaging technology uses multi-layer wafers in three-dimensional space. Vertical integration, forming a single integrated packaging technology, 3D IC packaging technology can cope with the problem that the semiconductor manufacturing process is restricted by the physical limits of electronics and materials, and save chip space.

In 3D IC packaging technology, the vertically arranged multi-layer wafer Die can first form a stacked structure by means of fusion bonding (FB), etc., and then can be formed by wire bonding (WB) or Through silicon via (TSV) and other technologies realize electrical interconnection between different layers of wafers. Finally, the above-mentioned stacked structure is plastic-encapsulated to obtain a packaged chip.

Among them, silicon fusion bonding is a low-cost 3D stacking method applicable to 3D IC packaging technology. The silicon fusion bonding process is simple, the production speed is fast, and the parasitic capacitance is small, the integration density is high, and the short channel effect is small. The 3D stacked structure is particularly suitable for the SOI (silicon on insulator, silicon on insulating substrate) structure of low-voltage and low-power circuits.

Among them, TSV is also called TSV, which is a vertical electrical connection technology that penetrates the device layer of the silicon wafer. Specifically, through-silicon vias are through-holes that connect the upper and lower sides of the wafer, and conductors (that is, through-hole metal) are poured into the through-holes to form conductive connections. The infused conductor can be determined according to its specific process, such as conductive materials such as copper, tungsten, and polysilicon, and an insulating layer (usually silicon dioxide) is used to isolate the through-silicon via conductive material from the substrate.

Figure 1 is a schematic diagram of a chip stacking structure. As shown in FIG. 1, the chip stack structure includes an upper wafer 10 and a lower wafer 20 stacked on each other. Among them, the active surface of the upper wafer 10 (the upper surface of the upper wafer 10 in FIG. 1) and the active surface of the lower wafer 20 (the upper surface of the lower wafer 20 in FIG. 1) are respectively prepared with

rewiring Layers

11 and 21. The passive surface of the upper wafer 10 (the lower surface of the upper wafer 10 in FIG. 1) and the surface of the rewiring layer 21 of the lower wafer 20 are respectively prepared with additional

dielectric layers

12 and 22, the upper wafer 10 and the lower crystal The circle 20 is bonded together by the silicon fusion of the

dielectric layers

12 and 22 to achieve stacking. In addition, the stacked structure also includes through-silicon vias 30 penetrating the bulk silicon of the upper wafer 10 and the

dielectric layers

12 and 22, so that the upper wafer 10 and the lower wafer 20 are electrically interconnected. The rewiring layer of the upper wafer 10 is provided with solder balls 13 which are used to form an electrical connection with an external substrate or a printed circuit board PCB.

What needs to be added here is that the active surface of the wafer refers to the surface of the wafer that has active devices, and the surface of the wafer that does not have active devices. , It is called a passive surface. For example, the lower surface of the upper wafer 10 and the lower surface of the lower wafer 20 in FIG. 1 are both passive surfaces; the redistribution layer (RDL) refers to the surface of the wafer The metal wiring pattern is formed by depositing the metal layer and the dielectric layer to realize the re-layout of the I/O ports of the chip. The rewiring layer is usually deposited on the active surface of the wafer. For example, in the structure shown in FIG. 1, the rewiring layer 21 of the lower wafer 20 is deposited on the active surface of the lower wafer 20, and the rewiring of the upper wafer 10 is The layer 11 is deposited on the active surface of the upper wafer 10.

In order to realize the silicon fusion bonding of the upper wafer 10 and the lower wafer 20, the structure shown in FIG. 1 additionally prepares a dielectric layer 12 and a rewiring layer 21 on the passive surface of the upper wafer 10 and the rewiring layer 21 of the lower wafer 20 22. The thickness of the

dielectric layers

12 and 22 can currently reach 1 micrometer to 5 micrometers, which will increase the thickness of the stacked chip, especially when the number of stacked wafer layers of the chip is large, the thickness of the

dielectric layers

12 and 22 For example, the number of stacked layers of 3D NAND flash memory wafers can reach 96 or even 128 layers, resulting in a very significant increase in the thickness of the dielectric layer, which is not conducive to the lightness and thinness of the chip. In addition, since silicon fusion bonding needs to meet certain surface flatness and roughness requirements, before silicon fusion bonding is performed on the dielectric layer, the surface of the dielectric layer needs to be accurately chemically mechanically polished (chemical mechanical polis, CMP). ), additional process steps and costs are added, and the packaging efficiency is reduced.

In addition, since the TSV 30 of the structure shown in FIG. 1 passes through the bulk silicon of the upper wafer 10 and the

dielectric layers

12 and 22, it is not only necessary to etch the bulk silicon of the upper wafer 10 when preparing the TSV 30. , The dielectric layers 12 and 22 need to be etched. Generally speaking, if only the wafer body silicon is etched, the Bosch process can be used; among them, the Bosch process is deep reactive ion etching (DRIE), which is a high aspect ratio silicon etching based on fluorine-based gas. Etching technology, which alternately converts etching gas and passivation gas, so that the reactive ion etching process continuously deposits an anti-etching layer or a side wall passivation layer on the side wall of the etching hole. The etching gas of the Bosch process is sulfur hexafluoride SF ₆ , and the passivation gas is octafluorocyclobutane C ₄ F ₈ . C ₄ F ₈ can form fluorinated carbon polymer in the plasma, which can be deposited on the silicon surface to prevent the reaction of fluoride ions with silicon. However, the gas used in deep reactive ion etching can only etch or passivate silicon, while the dielectric layer is generally oxide or nitride. Therefore, if you want to etch the silicon and the dielectric layer of the wafer body, you cannot With the Bosch process, only reactive ion etching (RIE) can be used. However, because it is difficult to select a suitable etching selection ratio for the wafer body silicon and the dielectric layer, even if the reactive ion etching process is used, the etching selection ratio will not be suitable and the dielectric layer will be formed such as Fig. 2 shows the fin-type (Fin) etching morphology and the drum-type etching morphology. Fin-type etching morphology and drum-type etching morphology will cause the sidewall shape of the etched hole to fluctuate greatly, which affects the coverage continuity of the seed layer during the preparation process of the through silicon via, and discontinuous coverage The seed layer will cause subsequent core metal filling failures, resulting in failure of electrical interconnections between stacked wafers.

Moreover, the chip stack structure shown in FIG. 1 needs to completely cover the

dielectric layers

12 and 22 on the upper wafer 10 and the lower wafer 20, so that the upper wafer 10 and the lower wafer 20 have a larger thermal resistance, which hinders The through-silicon vias 30 are only distributed in a small area of the wafer, and the heat dissipation effect of the wafer is very limited. Therefore, the structure of FIG. 1 may also cause heat dissipation problems in the chip, which affects the performance of the chip.

Figure 3 is a schematic diagram of another chip stacking structure. As shown in FIG. 3, the chip stack structure includes an upper wafer 10 and a lower wafer 20 stacked on each other. The active surface of the upper wafer 10 (the upper surface of the upper wafer in FIG. 3) and the active surface of the lower wafer 20 (the upper surface of the lower wafer in FIG. 3) are prepared with a large number of

metal pads

14 and 24. The positions of the metal pads 14 of the upper wafer 10 and the metal pads 24 of the lower wafer correspond to each other, and are connected by solder balls 40 to realize the stack interconnection of the upper wafer 10 and the lower wafer 20. In order for the solder balls 40 to accurately connect the metal pads 14 of the upper wafer 10 and the metal pads 24 of the lower wafer 20, the stacked structure shown in FIG. 3 needs to strictly control the positions of the

metal pads

14 and 24 during preparation. The precision and the strict control of the precision of the butterfly profile (dish) formed during the chemical mechanical polishing of the

metal pads

14 and 24 during the chemical mechanical polishing CMP make the production process difficult and low achievability. Moreover, due to the use of solder balls 40 for interconnection between the wafers, due to the limitation of the diameter of the solder balls 40, there are limits to the spacing between the wafers and the pad pitch between the

metal pads

14 and 24, which cannot be further reduced. , So that the height and horizontal size of the chip stack structure shown in FIG. 3 are relatively large, and the size of the chip after subsequent packaging is increased.

It can be seen that various chip stacking structures currently used in chip 3D IC packaging technology generally have the problems of large stacking thickness and unsatisfactory heat dissipation performance.

The embodiments of the present application provide a chip stack structure and a manufacturing method thereof to solve the technical problems existing in the above solutions. It should be noted that the chip stack structure described in the embodiments of the present application can have multiple different forms and can be implemented in multiple ways. The chip stack structure and manufacturing method discussed below are only some preferred implementations, used to illustrate the feasibility of the structure described in the embodiments of the present application, and do not limit the protection scope of the embodiments of the present application. It is also within the protection scope of the embodiments of the present application to implement the stacked package structure described in the embodiments of the present application by other methods or procedures.

Example one

The first embodiment of the present application provides a chip stack structure, which can be applied to the 3D IC packaging technology of the chip, so as to reduce the thickness of the chip stack and improve the heat dissipation performance of the chip. FIG. 4 is an exploded view of the chip stack structure provided by Embodiment 1 of the present application. As shown in Figure 4, the chip stack structure includes:

The first wafer 100 and the second wafer 200, and the first wafer 100 and the second wafer 200 are stacked on top of each other. The first wafer 100 and the second wafer 200 may be silicon wafers made of silicon material, for example. Both the first wafer 100 and the second wafer 200 include an active surface and a passive surface. The active surface 110 of the first wafer 100 corresponds to the upper surface of the first wafer 100 in FIG. The passive surface 120 of the circle 100 corresponds to the lower surface of the first wafer 100 in FIG. 4, the active surface 210 of the second wafer 200 corresponds to the upper surface of the second wafer 200 in FIG. The passive surface 220 of FIG. 4 corresponds to the lower surface of the second wafer 200, and the active surface 110 of the first wafer 100 and the passive surface 220 of the second wafer 200 are arranged opposite to each other.

The active surface 110 of the first wafer 100 is provided with a first rewiring layer 130. The first rewiring layer 130 includes a dielectric layer 131 and metal wiring 132. Wherein, the dielectric layer 131 covers the active surface 110 of the first wafer 100, and the dielectric layer 131 is used as an insulating material between the metal wirings 132, and can be made of an insulator material that can be polarized, for example, in the first wafer The active surface 110 of the wafer 100 uses plasma enhanced chemical vapor deposition (PECVD) to deposit materials such as silicon dioxide to form the dielectric layer 131. The metal wiring 132 is used as the lead wire of the I/O port of the chip to shuttle through the dielectric layer 131. The metal wiring 132 can be realized by using copper or other metal materials. For example, a Damascus process is used to etch the metal wiring 132 on the dielectric layer 131. The film is then filled with metal to form the metal wiring 132, or the metal wiring 132 is formed on the dielectric layer 131 by electroplating. It is easy to understand that since the chip usually has multiple I/O ports, the metal wiring 132 in the embodiment of the present application includes multiple metal wires for the leads of each I/O port.

In the embodiment of the present application, the first rewiring layer 130 is further provided with a plurality of first bonding pads 133, and the first bonding pads 133 are exposed on the surface of the first rewiring layer 130 parallel to the first wafer 100, namely ：The first bonding pad 133 is disposed facing the passive surface 220 of the second wafer 200. The plurality of first bonding pads 133 are electrically connected to the metal wiring 132 of the first rewiring layer 130. The first bonding pad 133 can be realized by using copper or other metal materials, and is prepared together with the first rewiring layer 130 by using Damascus or electroplating. It should be supplemented that, due to the requirements of wafer circuit design, the first rewiring layer 130 may include one or more layers of metal wiring 132, and each layer of metal wiring 132 may be connected to the first bonding pad 133. Therefore, the first bonding pad 133 indicated in FIG. 4 may be understood as including only one first bonding pad 133, or may be understood as including a stack of a plurality of first bonding pads 133.

As further shown in FIG. 4, the active surface 210 of the second wafer 200 is provided with a second rewiring layer 230. The second rewiring layer 230 is composed of a dielectric layer 231 and a metal wiring 232. The implementation of the dielectric layer 231 and the metal wiring 232 of the second rewiring layer 230 can refer to the dielectric layer 131 and the metal wiring 232 of the first rewiring layer 130. Implementation of the metal wiring 132. It is easy to understand that, depending on the design of the integrated circuit of the wafer, the dielectric and metal wiring of the first rewiring layer 130 and the second rewiring layer 230 can be implemented in the same way or in different ways. For example, the layout of the metal wiring is different, and the implementation of the second rewiring layer 230 in the embodiment of the present application will not be repeated.

As further shown in FIG. 4, the second wafer 200 is further provided with a plurality of through silicon vias 233, and the plurality of through silicon vias 233 penetrate from the active surface 210 of the second wafer 200 to the passive surface of the second wafer 200.面220. The second rewiring layer 230 of the second wafer 200 is also provided with a plurality of metal pads 234 which are electrically connected to the metal wiring 232 in the second rewiring layer 230. The metal pad 234 may be implemented using copper or other metal materials, for example, prepared in the second rewiring layer 230 using a Damascus process or an electroplating method. It should be supplemented that, according to the requirements of wafer circuit design, the second rewiring layer 230 may include one or more layers of metal wiring 232, and each layer of metal wiring 232 may be connected to a metal pad 234. Therefore, The metal shim plate 234 indicated in FIG. 4 can be understood as including only one metal shim plate 234, or can be understood as including a stack of a plurality of metal shim plates 234.

FIG. 5 is a cross-sectional view of the stacked state of the first wafer and the second wafer. As shown in FIG. 5, the passive surface 220 of the second wafer 200 is bonded to the first rewiring layer 130 of the first wafer 100, so that the first wafer 100 and the second wafer 200 are stacked. A special feature of the embodiment of the present application is that the first bonding pad 133 is exposed on the surface of the first rewiring layer 130, so that the first bonding pad 133 can also be bonded to the passive surface 220 of the second wafer 200. Together. Therefore, the "passive surface 220 of the second wafer 200 and the first rewiring layer 130 of the first wafer 100 are bonded and connected" in the embodiment of the present application is actually the passive surface 220 of the second wafer 200 The bonding connection is achieved with the first rewiring layer 130 of the first wafer 100 and the plurality of first bonding pads 133.

As further shown in FIG. 5, one end of each through silicon via 233 located on the active surface 210 of the second wafer 200 is connected to at least one metal pad 234, and each through silicon via 233 is located on the second wafer 200. One end of the passive surface 220 is connected to at least one first bonding pad 133. The through silicon via 233 is also filled with a metal filler 235, such as electroplated copper. The metal filler 235 can be formed by sputtering on the inner surface of the through silicon hole 233 to form a seed layer connected to the first bonding pad 133, and then performing metal plating on the surface of the seed layer. The metal filler 235 is used to make the metal pad 234 at one end of the through silicon hole 233 and the first bonding pad 133 at the other end of the through silicon hole 233 form an electrical connection to realize the connection between the first wafer 100 and the second wafer 200 Electrical interconnection.

It should be supplemented that if the second wafer 200 is the uppermost wafer of the chip, the second rewiring layer 230 may also be provided with solder balls 236 as shown in FIG. The chip is connected to an external substrate or printed circuit board, so that the chip and the external substrate or printed circuit board PCB form an electrical connection.

The chip stack structure provided by the embodiment of the present application directly bonds and connects the first rewiring layer 130 of the active surface 110 of the first wafer 100 and the passive surface 220 of the second wafer 200, so there is no need to connect the bonding surface Preparing an additional dielectric layer or using solder balls can make the thickness of the first wafer 100 and the second wafer 200 after stacking at least reduce the thickness of the additional dielectric layer and solder balls, so that the size of the chip after packaging can be more reduced. Smaller and thinner. In addition, after the additional dielectric layer is omitted, the thermal resistance after the first wafer 100 and the second wafer 200 are stacked is reduced, which facilitates the transfer of heat between the wafers and improves the heat dissipation performance of the chip. In addition, the first rewiring layer 130 of the first wafer 100 is also provided with a bare first bonding pad 133, and the second wafer 200 is also provided with a through silicon via 233 connected to the first bonding pad 133, so that the first The first wafer 100 and the second wafer 200 can be directly electrically interconnected through the through silicon vias 233, without the use of solder balls or etching the dielectric layer, so the structure is simple, the process steps are simplified, and the connection reliability is high.

In an alternative implementation manner, as shown in FIG. 6, the chip stack structure provided by the embodiment of the present application further includes: a plurality of second bonding pads 134. The second bonding pad 134 is exposed and disposed on the surface of the first rewiring layer 130 parallel to the active surface 110 of the first wafer 100, that is, the second bonding pad 134 faces the passive surface 220 of the second wafer 200 Set up. The plurality of second bonding pads 134 are electrically connected to the metal wiring 132 of the first rewiring layer 130. The second bonding pad 134 can be realized by using copper or other metal materials, and prepared together with the first rewiring layer 130 by using Damascus or electroplating.

FIG. 7 is a cross-sectional view of the stacked state of the first wafer and the second wafer. As shown in FIG. 7, since the second bonding pad 134 is exposed on the surface of the first rewiring layer 130, the second bonding pad 134 can also be bonded to the passive surface 220 of the second wafer 200. Therefore, the “passive surface 220 of the second wafer 200 and the first rewiring layer 130 of the first wafer 100 are bonded and connected” in the embodiment of the present application may also be the passive surface 220 of the second wafer 200 The bonding connection is achieved with the first rewiring layer 130 of the first wafer 100, the plurality of first bonding pads 133, and the plurality of second bonding pads 134.

In the embodiment of the present application, the first bonding pad 133 and the second bonding pad 134 may be the same bonding pad or different bonding pads. The main difference between the two is that the first bonding pad 133 is used It is connected to the through silicon via 233 of the second wafer 200, so that the first wafer 100 and the second wafer 200 are electrically interconnected; and the second bonding pad 134 is only connected to the passive surface 220 of the second wafer 200 It is not connected to the through silicon via 233. Therefore, the second bonding pad 134 is used as a heat conduction structure between wafers in the embodiment of the present application, which can further reduce the thermal resistance between the wafers and increase the heat on the wafers. The transfer efficiency between the chips improves the heat dissipation performance after the chip is packaged.

In an embodiment, as shown in FIG. 8, the passive surface 220 of the second wafer 200 in the embodiment of the present application is further provided with a first dielectric layer 237. When the passive surface 220 of the second wafer 200 is provided with the first dielectric layer 237, the "passive surface 220 of the second wafer 200 and the first rewiring layer of the first wafer 100" in the embodiment of the present application 130 bonding connection" can also be the first dielectric layer 237 of the second wafer 200 and the first rewiring layer 130 of the first wafer 100, a plurality of first bonding pads 133, and a plurality of second bonding The disk 134 realizes the bond connection.

In the embodiment of the present application, the first dielectric layer 237 may be made of a high thermal conductivity material, such as silicon carbide, diamond, graphene, or silicon nitride. In order to reduce the thermal resistance between the first wafer 100 and the second wafer 200, the heat dissipation performance after the chip packaging is improved.

It should be supplemented that a chip packaged with 3D IC technology may include two or more layers of wafers stacked on each other, and the stacked structure of the first wafer 100 and the second wafer 200 shown in the embodiment of the present application may be A stack structure used by any adjacent two layers of wafers in the chip. In a chip with multi-layer wafers, any two adjacent layers of wafers can adopt the same or different stacking structure, for example: all adjacent two layers of wafers use the first wafer 100 and the second wafer. The stacked structure of the circle 200, or the stacked structure of the first wafer 100 and the second wafer 200 with only part of adjacent two-layer wafers, does not exceed the protection scope of the embodiments of the present application.

9 and 10 are an exploded view and a cross-sectional view of a multi-layer chip stack structure shown in an embodiment of the present application.

As shown in FIG. 9 and FIG. 10, the chip stack structure includes: multiple layers of mutually stacked wafers, such as wafer 1, wafer 2, wafer 3, ..., wafer N. Wherein, any two adjacent wafers can be used as the first wafer and the second wafer in the embodiment of the present application, and have a stacked structure of the first wafer and the second wafer in the embodiment of the present application.

For example, wafer1 can be implemented as a first wafer, and the rewiring layer RDL1 of wafer1 can be implemented as a first rewiring layer accordingly; wafer2 can be implemented as a second corresponding to wafer1 For the wafer, the rewiring layer RDL2 of wafer2 can be implemented as a second rewiring layer accordingly. The passive surface 322 of the wafer 2 is bonded to the rewiring layer RDL1 of the wafer 1, the plurality of first bonding pads 133 and the plurality of second bonding pads 134. Wafer2 is provided with multiple through silicon vias 233, one end of each through silicon via 233 is connected to at least one of the multiple first bonding pads 133 of wafer1, and the other end is connected to the rewiring layer RDL2 of wafer2 The metal wiring 132 is connected to realize the electrical interconnection between wafer wafer1 and wafer wafer2.

For example, wafer2 can be implemented as the first wafer, and the rewiring layer RDL2 of wafer2 can be implemented as the first rewiring layer accordingly; wafer3 can be implemented as the second corresponding to wafer2 For the wafer, the rewiring layer RDL3 of wafer3 can be implemented as a second rewiring layer accordingly. The passive surface 332 of the wafer 3 is bonded to the rewiring layer RDL2 of the wafer 2, the plurality of first bonding pads 133 and the plurality of second bonding pads 134. Wafer3 is provided with multiple through silicon vias 233, one end of each through silicon via 233 is connected to at least one of the multiple first bonding pads 133 of wafer2, and the other end is connected to the rewiring layer RDL3 of wafer3 The metal wiring 132 is connected to realize the electrical interconnection of wafer2 and wafer3.

Between other wafers, for example, a stack structure of wafer m and wafer m+1 (m is a natural number, m+1≤N) can also be implemented with reference to the stack structure shown in FIG. 9 and FIG. 10. Wherein, when the wafer (m) is implemented as the first wafer, the wafer (m+1) may be implemented as the second wafer, which will not be repeated in the embodiment of the present application.

The chip stack structure shown in FIG. 9 and FIG. 10 can be applied to stacked dynamic random access memory (stacked DRAM), 3D NAND flash memory, and other chips that require wafers to be stacked and packaged.

Among them, the stacked DRAM can be, for example, high-bandwidth memory (HBM). When the chip stack structure shown in FIG. 9 and FIG. 10 is applied to HBM, the thickness of the wafer stack of HBM can be effectively reduced, making HBM in More wafers can be stacked with the same thickness, which enables HBM to provide higher bandwidth and larger capacity with a smaller volume; the chip stacking structure shown in Figure 9 and Figure 10 can also improve the heat dissipation performance of HBM, which is beneficial for improvement The frequency of HBM enables HBM to play a higher performance.

When the chip stack structure shown in Figure 9 and Figure 10 is applied to 3D NAND flash memory, the wafer stack thickness of 3D NAND flash memory can be effectively reduced, so that 3D NAND flash memory can stack more wafers with the same thickness, for example, from The existing 96-layer and 128-layer wafers are stacked to more layers, enabling 3D NAND flash memory to provide larger capacity with a smaller volume; the chip stacking structure shown in Figure 9 and Figure 10 can also improve the performance of 3D NAND flash memory. The heat dissipation performance is conducive to improving the continuous read and write performance of 3D NAND flash memory.

It should be supplemented that, as shown in FIG. 10, in a multilayer wafer stack structure, the rewiring layer RDL N of the uppermost wafer wafer N can be provided with solder balls 236, through which the package can be packaged. The latter chip is integrated on the external substrate or printed circuit board, so that the chip and the external substrate or printed circuit board PCB form an electrical connection.

11 is a schematic structural diagram of an integrated chip shown in an embodiment of the present application. The integrated chip includes a substrate and at least one chip. A part of the chips (hereinafter referred to as chip 1) may have the chip stack shown in FIGS. 9 and 10 Structure, another part of the chip (hereinafter referred to as chip 2) may have other forms of chip stacking structure. Wherein, the chip 1 may be electrically connected to the substrate 238 through solder balls 236, and the chip 2 may include a multi-layer wafer. The multi-layer wafer can be packaged using the chip stack structure provided in the embodiment of the present application, or other chip stacks can be used. The structure, for example, a connection structure such as the interposer 239, is packaged.

As an example, the integrated chip shown in FIG. 11 may be a graphics processing unit (GPU), where chip 1 may be the video memory chip of the graphics processor, such as an HBM video memory chip, and chip 2 may be the graphics processing unit. The system chip (syetem on chip, SOC) of the processor, a graphics processor may include at least one system chip and multiple HBM video memory chips. The chip stack structure provided by the embodiments of the present application can enable the HBM video memory chip to provide higher bandwidth and larger capacity with a smaller volume, which is beneficial to improving the performance of the graphics processor.

Example two

The second embodiment of the present application provides a method for fabricating a chip stack structure, and the method can be used to fabricate the chip stack structure of the first embodiment of the present application and various embodiments thereof. The method may include the following steps S101 to S104:

Step S101, preparing a first rewiring layer and a plurality of first bonding pads on the active surface of the first wafer, and the plurality of first bonding pads are exposed on the surface of the first rewiring layer parallel to the first wafer. , The plurality of first bonding pads are electrically connected to the metal wiring of the first rewiring layer.

The first rewiring layer includes a dielectric layer and metal wiring. Among them, the dielectric layer can be formed by depositing silicon dioxide and other materials on the active surface of the first wafer using the PECVD method; the metal wiring can be prepared together with the first bonding pad, for example, using a Damascus process to etch metal on the dielectric layer The pattern film for wiring and the first bonding pad is then filled with metal to form the metal wiring and the first bonding pad, or electroplating is used to prepare the metal wiring and the first bonding pad on the dielectric layer. It should be noted that the final prepared first bonding pad needs to be exposed on the surface of the first rewiring layer.

In order to obtain the first bonding pad exposed on the surface of the first rewiring layer, step S101 can be implemented through step S201 to step S202 as shown in FIG. 12:

In step S201, a first rewiring layer 130 with a thickness greater than a predetermined target thickness H and a plurality of first bonding pads 133 hidden in the first rewiring layer 130 are prepared on the active surface 110 of the first wafer 100.

The target thickness H refers to the thickness of the first rewiring layer determined during chip design. The target thickness H can be determined according to design rules. The design rules can be, for example, parameters provided by semiconductor manufacturers to ensure the target thickness. H meets the parameter requirements required by manufacturing.

In the first rewiring layer 130 whose thickness is greater than the target thickness H, the metal wiring 132 and the first bonding pad 133 are both hidden in the dielectric layer 131 of the first rewiring layer 130, wherein the first bonding pad 133 is The direction perpendicular to the active surface 110 of the first wafer 100 has a certain depth, and the distance L between the end of the first bonding pad 133 away from the active surface 110 and the active surface 110 is greater than the target thickness H.

In step S202, the first rewiring layer 130 is thinned to a target thickness H through material removal processing, so that the plurality of first bonding pads 133 are exposed on the surface of the first rewiring layer 130 parallel to the first wafer 100.

In specific implementation, the CMP process can be used to remove material from the first rewiring layer 130, so that the first rewiring layer 130 is thinned to a target thickness, and the first bonding pad 133 is changed from the hidden state after step S201. It is naked. During the CMP process, an oxide layer may be generated on the exposed surface of the first bonding pad 133. Therefore, after CMP, chemical cleaning or plasma cleaning can also be used to remove the oxide layer. Among them, chemical cleaning methods such as formic acid cleaning, plasma cleaning The method is for example argon plasma cleaning, which will not be repeated here.

In addition, during the CMP process, the first bonding pad 133 will be subjected to a dish effect to form a dish-shaped contour dish on the exposed surface. Since the first bonding pad 133 is inconsistent with the material of the surrounding dielectric 131, this The dish-shaped profile will form a shallow groove, which can be used as an expansion allowance for metal creep and plastic deformation in the subsequent bonding process. It should be supplemented that since the first bonding pad 133 in the embodiment of the present application does not need to be connected to the solder balls, there is no need to precisely control the depth of the dish during the CMP process, as long as the expansion margin is retained. Therefore, the method of the embodiment of the present application improves the feasibility of process control, and reduces the production cost.

In an achievable embodiment, the surface of the first rewiring layer is also provided with a bare second bonding pad. Then, in order to prepare the second bonding pad, step S101 can also pass through step S301 shown in FIG. 13 And step S302 is implemented:

Step S301, preparing a first rewiring layer 130 larger than a preset target thickness H on the active surface 110 of the first wafer 100, and a plurality of first bonding pads 133 and multiple layers hidden in the first rewiring layer 130 A second bonding pad 134.

In the first rewiring layer 130 whose thickness is greater than the target thickness H, the metal wiring 132, the first bonding pad 133, and the second bonding pad 134 are all hidden in the dielectric layer 131 of the first rewiring layer 130, wherein, The first bonding pad 133 and the second bonding pad 134 each have a certain depth along the direction perpendicular to the active surface 110 of the first wafer 100, and the distance between the first bonding pad 133 and the second bonding pad 134 The distance between one end of the active surface 110 and the active surface 110 is greater than the target thickness H.

In step S302, the first rewiring layer 130 is thinned to a target thickness H by removing the material, so that the plurality of first bonding pads 133 and the plurality of second bonding pads 134 are exposed in parallel with the first rewiring layer 130 On the surface of the first wafer 100.

In the embodiment of the present application, the first bonding pad 133 and the second bonding pad 134 may be the same bonding pad or different bonding pads. The main difference between the two is that the first bonding pad 133 is used It is connected to the through-silicon via of the second wafer, so that the first wafer 100 and the second wafer are electrically interconnected; and the second bonding pad 134 is only connected to the passive surface of the second wafer, not to the silicon Through-hole connection, therefore, the second bonding pad 134 is used as a heat conduction structure between wafers in the embodiment of the present application, which can reduce the thermal resistance between the wafers, improve the heat transfer efficiency between the wafers, and improve The heat dissipation performance after the chip is packaged.

Step S102, bonding the passive surface of the second wafer to the first rewiring layer and the plurality of first bonding pads.

In specific implementation, as shown in FIG. 14, the passive surface 220 of the second wafer 200 and the first rewiring layer 130 can be activated first, and then the silicon fusion bonding method is used to make the second wafer 200 non-volatile. The source plane 220 is connected to the first rewiring layer 130. Since the first rewiring layer 130 is also provided with the exposed first bonding pad 133, the first bonding pad 133 can also be bonded to the passive surface 220 of the second wafer 200. In addition, if the first rewiring layer is also provided with the exposed second bonding pad 134, the second bonding pad 134 can also be bonded to the passive surface 220 of the second wafer 200. Therefore, the connection method of the first wafer 100 and the second wafer 200 in the embodiment of the present application is between silicon fusion bonding and hybrid bonding.

In step S103, a plurality of through silicon vias are formed by etching on the second wafer, and an end of each through silicon via located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads.

In specific implementation, as shown in FIG. 15, the projection position of the TSV 233 can be determined on the active surface 210 of the second wafer 200 according to the position of the first bonding pad 133; then, the projection position of the TSV 233 is perpendicular to the second wafer 200 The active surface 210 is etched from the determined projection position to the direction of the first bonding pad 133 to form the through silicon hole 233. During the etching process, the etching depth can be controlled to make the bottom of the through silicon hole 233 gradually move toward the first bonding pad. A bonding pad 133 is approached until the first bonding pad 133 is exposed; next, a seed layer connected to the first bonding pad 133 is sputtered on the inner surface of the through silicon hole 233; finally, on the surface of the seed layer Metal plating is performed to prepare a metal filler 235 for electrically interconnecting the first wafer 100 and the second wafer 200. In the method of the embodiment of the present application, no additional dielectric etching is generated during the etching of the through-silicon via 233, only the wafer body silicon is etched, and there is no need to select the etching selection ratio for different materials, which avoids Because of the improper etching selection ratio, the fin-type (Fin) etching morphology and drum-type etch morphology are formed in the dielectric layer, so that the continuity of the seed layer and the metal filler 235 is ensured, and the first crystal is improved. The reliability of the connection between the circle 100 and the second wafer 200.

In the embodiment of the present application, the through-silicon via 233 can be prepared by different processes such as via-first, via-middle, or via-last; among them, the via-first process It means that the through silicon via 233 is prepared before the second rewiring layer of the second wafer 200 is prepared. The middle through hole process refers to the preparation of the through silicon via 233 in the process of preparing the second rewiring layer; the back through hole process refers to After preparing the second rewiring layer, the through silicon via 233 is prepared; the embodiment of the present application does not specifically limit the manufacturing process of the above through silicon via 233.

Step S104, preparing a second rewiring layer on the active surface of the second wafer, the second rewiring layer is provided with a plurality of metal pads, and the plurality of metal pads are electrically connected to the metal wiring of the second rewiring layer; One end of the through silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pads.

As shown in FIG. 16, the second rewiring layer 230 is composed of a dielectric layer 231 and metal wiring 232. Wherein, the dielectric layer 231 can be formed by depositing silicon dioxide and other materials on the active surface 210 of the second wafer 200 using a PECVD method; the metal wiring 232 can be prepared together with the metal pad 234, for example, a Damascus process is used on the dielectric layer. The pattern film for the metal wiring 232 and the metal pad 234 is etched on the 231, and then metal filler is used to form the metal wiring 232 and the metal pad 234, or the metal wiring 232 and the metal pad 234 are prepared on the dielectric layer by electroplating. It should be noted that the final prepared metal pad 234 needs to be connected to the metal filler 235 prepared in step S103. So far, the first bonding pad 133 and the metal pad 234 are electrically connected through the metal filler 235 to make the first wafer 100 An electrical interconnection channel is established with the second wafer 200.

It should be supplemented that if the second wafer 200 is the uppermost wafer of the chip, the second rewiring layer 230 may be provided with solder balls 236, through which the packaged chip can be mounted on an external substrate or printed On the circuit board, the chip is electrically connected to an external substrate or a printed circuit board PCB.

In the method of manufacturing the chip stack structure of the embodiment of the present application, the first rewiring layer 130 of the first wafer 100 and the passive surface 220 of the second wafer 200 are directly bonded and connected, so there is no need to prepare additional bonding surfaces on the bonding surface. The dielectric layer or the use of solder balls can reduce the thickness of the first wafer 100 and the second wafer 200 after stacking at least the thickness produced by the additional dielectric layer and solder balls, so that the package size of the chip is smaller. Thinner and lighter. In addition, after the additional dielectric layer is omitted, the thermal resistance after the first wafer 100 and the second wafer 200 are stacked is reduced, which facilitates the transfer of heat between the wafers and improves the heat dissipation performance of the chip. In addition, the first rewiring layer 130 of the first wafer 100 is also provided with a bare first bonding pad 133, and the second wafer 200 is also provided with a through silicon via 233 connected to the first bonding pad 133, so that the first The first wafer 100 and the second wafer 200 can be directly electrically interconnected through the through silicon vias 233, without the use of solder balls and etched dielectric layers, so the structure is simple, the process steps are simplified, and the connection reliability is high.

In an alternative embodiment, as shown in FIG. 17, the passive surface 220 of the second wafer 200 may also be prepared with a first dielectric layer 237. When the passive surface 220 of the second wafer 200 is prepared with the first dielectric layer 237, step S102 is specifically implemented as: the first dielectric layer 237 of the second wafer 200 and the rewiring layer of the first wafer 100 130. The first bonding pad 133 and the second bonding pad 134 are bonded and connected. The first dielectric layer 237 can be made of a high thermal conductivity material, such as silicon carbide, diamond, graphene, or silicon nitride, etc., to reduce the thermal resistance between the first wafer 100 and the second wafer 200, and improve the chip package after the chip is packaged. The heat dissipation performance.

In the example of the present application, steps S101 to S104 are used as basic steps to prepare a two-layer chip stack structure. It is easy to understand that the above-mentioned basic steps can also be repeated in whole or in part, or repeated in combination and split to prepare a multi-layer chip stack structure, and these implementations do not exceed the protection scope of the embodiments of the present application. .

The embodiment of the present application also provides a computer chip. The computer chip includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a system chip on chip, SOC), 3D NAND chips, stacked dynamic random access memory (stacked DRAM), high-bandwidth memory (HBM), etc., the above-mentioned computer chip may include a substrate, and many packages are A multi-layer wafer, wherein part or all of the multi-layer wafer includes the chip stack structure of one of the embodiments of the present application.

The embodiment of the application also provides an electronic device, which includes but is not limited to a graphics card (graphics card), a solid-state drive (SSD), a flash drive (USB flash drive), a mobile phone, a personal computer, Servers, workstations, etc. The electronic device includes at least one printed circuit board PCB, and at least one computer chip arranged on the at least one printed circuit board, wherein part or all of the at least one computer chip includes the chip of one of the embodiments of the present application Stacked structure.

Claims

A chip stacking structure, characterized in that it comprises:

A first wafer, the active surface of the first wafer is provided with a first rewiring layer;

A plurality of first bonding pads, the plurality of first bonding pads are exposed on the surface of the first rewiring layer parallel to the first wafer, and the plurality of first bonding pads are connected to the The metal wiring of the first rewiring layer is electrically connected;

The second wafer, the second wafer and the first wafer are stacked, and the passive surface of the second wafer is bonded to the first rewiring layer and the plurality of first bonding pads Bonding connection; the second wafer is provided with a plurality of through silicon vias, and the first end of each of the through silicon vias located on the passive surface of the second wafer and the plurality of first bonding pads At least one of the connections.
The chip stack structure according to claim 1, further comprising:

A plurality of second bonding pads, the plurality of second bonding pads are exposed on the surface of the first rewiring layer parallel to the first wafer, and the plurality of second bonding pads are connected to the The passive surface bonding of the second wafer is connected, and the plurality of second bonding pads are electrically connected to the metal wiring of the first rewiring layer.
The chip stack structure according to claim 1, wherein:

The active surface of the second wafer is provided with a second rewiring layer, the second rewiring layer is provided with a plurality of metal pads, the plurality of metal pads and the metal of the second rewiring layer The wiring is electrically connected; one end of each of the through silicon vias located on the active surface of the second wafer is connected to at least one of the plurality of metal pads.
The chip stack structure according to claim 3, wherein:

Each of the through silicon vias is filled with a metal filler, and the metal filler is used to electrically connect the first bonding pad to which it is connected to the metal pad.
The chip stack structure according to claim 4, wherein:

The metal filler is obtained by sputtering on the inner surface of the through silicon hole to form a seed layer connected to the first bonding pad, and performing metal electroplating on the surface of the seed layer.
The chip stack structure according to claim 2, wherein:

The passive surface of the second wafer is provided with a first dielectric layer, and the passive surface of the second wafer passes through the first dielectric layer, the first rewiring layer, and the plurality of second wafers. A bonding pad is bonded to the plurality of second bonding pads.
A manufacturing method of a chip stack structure, characterized in that it comprises:

A first rewiring layer and a plurality of first bonding pads are prepared on the active surface of the first wafer, and the plurality of first bonding pads are exposed and disposed on the first rewiring layer parallel to the first On the surface of the wafer, the plurality of first bonding pads are electrically connected to the metal wiring of the first rewiring layer;

Bonding the passive surface of the second wafer to the first rewiring layer and the plurality of first bonding pads;

The second wafer is etched to form a plurality of through silicon holes, and one end of each of the through silicon holes located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads. A connection.
8. The method of claim 7, wherein the preparing a first rewiring layer and a plurality of first bonding pads on the active surface of the first wafer comprises:

Preparing the first rewiring layer larger than a preset target thickness on the active surface of the first wafer, and the plurality of first bonding pads hidden in the first rewiring layer;

Through material removal processing, the first rewiring layer is thinned to the target thickness, so that the plurality of first bonding pads are exposed on the first rewiring layer parallel to the first wafer surface.
The method according to claim 8, further comprising:

A plurality of second bonding pads hidden in the first rewiring layer are prepared on the active surface of the first wafer, and when the first rewiring layer is thinned to the target thickness, the A plurality of second bonding pads are exposed on the surface of the first rewiring layer.
8. The method of claim 7, wherein the second wafer is etched to form a plurality of through silicon vias, and each of the through silicon vias is located on the passive surface of the second wafer One end of is connected with at least one of the plurality of first bonding pads, including:

Determining the projection position of at least one first bonding pad on the active surface of the second wafer;

Perpendicular to the active surface of the second wafer, the through silicon via is etched from the projection position in the direction of the first bonding pad until the through silicon via and the at least one first The bonding pads are in contact.
The method according to any one of claims 7-10, further comprising:

A second rewiring layer is prepared on the active surface of the second wafer, the second rewiring layer is provided with a plurality of metal pads, and the metal of the second rewiring layer is The wiring is electrically connected; one end of each of the through silicon vias located on the active surface of the second wafer is connected to at least one of the plurality of metal pads.
The method according to claim 11, further comprising:

Forming a seed layer connected to the first bonding pad on the inner surface of the through silicon via by surface sputtering;

Metal plating is performed on the surface of the seed layer to form a metal filler, and the metal filler electrically connects the first bonding pad with the metal pad.
8. The method according to claim 8, wherein the bonding and connecting the passive surface of the second wafer with the first rewiring layer and the plurality of first bonding pads comprises:

Preparing a first dielectric layer on the passive surface of the second wafer;

Bonding the first dielectric layer to the first rewiring layer, the first bonding pad and the second bonding pad.
An electronic device, characterized by comprising a printed circuit board PCB, and at least one computer chip arranged on the printed circuit board, and part or all of the at least one computer chip has any one of claims 1 to 6 The chip stack structure.