CN210052731U - Semiconductor structure - Google Patents

Abstract

The embodiment of the utility model provides a semiconductor structure is related to, include: the semiconductor device comprises a first semiconductor unit and a first TSV structure positioned in the first semiconductor unit, wherein the first TSV structure is exposed out of the top surface of the first semiconductor unit; an interlayer bonding layer located on the top surface of the first semiconductor unit, wherein an interconnection structure is arranged in the interlayer bonding layer, the interconnection structure comprises at least one conductive layer, the interconnection structure is provided with a top end and a bottom end opposite to the top end, and the first TSV structure is in contact with the bottom end of the interconnection structure; and the second semiconductor unit and the first semiconductor unit are respectively positioned at two opposite sides of the interlayer junction layer, a second TSV structure is arranged in the second semiconductor unit, and the second TSV structure is in contact with the top end of the interconnection structure. The embodiment of the utility model provides a semiconductor structure's whole thickness is thin, and is favorable to reducing semiconductor structure's resistance value, improves semiconductor structure's performance.

Description

Semiconductor structure

Technical Field

The embodiment of the utility model provides a relate to the semiconductor technology field, in particular to semiconductor structure.

Background

With the continuous development of the design and manufacturing level of integrated circuits, in the field of packaging technology, the problem of too long circuit is caused by a common 2DIC packaging structure, so that the operation speed of the circuit is reduced and the power consumption is increased, and a 3D packaging structure comes along. The 3D packaging structure can effectively reduce the length of a line, improve the operation speed and reduce the power consumption.

In the 3D package structure, a plurality of chips are mainly placed in a vertical direction to reduce a planar area of the chips, and interconnection between different layers may be realized through a TSV (through-Silicon Via) structure between multiple layers of chips (die) or wafers (wafers). The TSV structure mainly comprises the following functions: on one hand, the interconnection between an upper layer chip or wafer and a lower layer chip or wafer is realized through the TSV structure; on the other hand, since the thermal conductivity of the material of the TSV structure is generally higher than that of the semiconductor material such as silicon, the provision of the TSV structure in the 3D package structure has the effect of dissipating heat such as a circuit.

However, the performance of the existing package structure with TSV still needs to be improved.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a technical problem who solves provides a semiconductor structure, provides a brand-new semiconductor structure, improves the semiconductor structure performance.

In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the device comprises a first semiconductor unit and a first TSV structure positioned in the first semiconductor unit, wherein the first TSV structure is exposed out of the top surface of the first semiconductor unit; an interlayer bonding layer on the top surface of the first semiconductor unit, wherein the interlayer bonding layer is internally provided with an interconnection structure, the interconnection structure comprises at least one conductive layer, the interconnection structure is provided with a top end and a bottom end opposite to the top end, and the first TSV structure is in contact with the bottom end of the interconnection structure; the second semiconductor unit and the first semiconductor unit are respectively positioned on two opposite sides of the interlayer bonding layer, a second TSV structure is arranged in the second semiconductor unit, and the second TSV structure is in contact with the top end of the interconnection structure.

Compared with the prior art, the embodiment of the utility model provides a technical scheme has following advantage:

the embodiment of the utility model provides a semiconductor structure that structural performance is superior has first TSV structure in the first semiconductor unit, has second TSV structure in the second semiconductor unit, and has the interlayer tie between second semiconductor unit and the first semiconductor unit, has the interconnect structure including at least one deck conducting layer in the interlayer tie; the bottom end of the interconnection structure is in contact with the first TSV structure, and the top end of the interconnection structure is in contact with the second TSV structure. The embodiment of the utility model provides an in, borrow and electrically connect first TSV structure and second TSV structure by means of the interconnect structure including the conducting layer, be favorable to reducing the equivalent resistance value between first TSV structure and the second TSV structure, and reduce semiconductor structure's whole thickness.

In addition, the thickness of the interconnect structure is in the range of 0.4 μm to 10 μm in a direction pointing along the first semiconductor unit toward the second semiconductor unit. Within the range, the thickness of the semiconductor structure is reduced while excellent electrical connection performance between the first TSV structure and the second TSV structure is guaranteed.

In addition, the interconnection structure comprises a top conductive layer and a middle interconnection structure besides a bottom conductive layer, and the requirements of different lengths of the second TSV structure are met by reasonably setting the number of layers of the conductive layers of the interconnection structure.

In addition, the thickness of the interlayer bonding layer is equal to the thickness of the interconnection structure in the direction pointing from the first semiconductor unit to the second semiconductor unit, and the thickness of the interlayer bonding layer is minimized, thereby facilitating further reduction in the thickness of the semiconductor structure.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the present invention;

fig. 3 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

fig. 5 to 7 are SEM images of a semiconductor structure according to an embodiment of the present invention and a conventional semiconductor structure in a partial cross-section;

fig. 8 to 10 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

fig. 11 to 13 are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As can be seen from the background art, the performance of the package structure with TSVs in the prior art needs to be improved, wherein the 3D semiconductor structure may be a single wafer or a single chip, or may be a stacked structure of a wafer and a chip, a stacked structure of a wafer and a wafer, or a stacked structure of a chip and a chip.

Taking the 3D package structure as an example of a stacked structure of chips, a lower chip has a first TSV structure, an upper chip has a second TSV structure, and a solder ball (bump) or a copper Pillar (pilar) is disposed between the top of the first TSV structure and the bottom of the second TSV structure, so that the first TSV structure and the second TSV structure are electrically connected through the solder ball or the copper Pillar.

However, due to the limitation of the forming process of the solder balls and the copper pillars, the thickness of the solder balls or the copper pillars is relatively thick along the stacking direction of the chip, and a dielectric structure layer with a relatively thick thickness is also formed around the solder balls or the copper pillars, and the thickness of the dielectric structure layer is usually over 10 μm. The first TSV structure and the second TSV structure are long in distance by utilizing a mode of realizing electric connection through the solder balls or the copper columns, so that the resistance value of the packaging structure is large, and the whole thickness of the packaging structure is thick.

In order to solve the above problem, an embodiment of the present invention provides a semiconductor structure, which connects the first TSV structure and the second TSV structure electrically through the interconnection structure, and compared with the solder ball or the copper pillar, the vertical thickness of the interconnection structure is smaller, so that the overall thickness of the semiconductor structure is favorably reduced, and the resistance value between the first TSV structure and the second TSV structure is reduced, thereby reducing the resistance value of the semiconductor structure.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the present invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

A first semiconductor unit 10 and a first TSV structure 101 located in the first semiconductor unit 10, wherein the first TSV structure 101 is exposed on the top surface of the first semiconductor unit 10; an interlayer bonding layer 20 located on the top surface of the first semiconductor unit 10, the interlayer bonding layer 20 having an interconnection structure 30 therein, the interconnection structure 30 including at least one conductive layer, the interconnection structure 30 having a top end and a bottom end opposite to the top end, and the first TSV structure 101 being in contact with the bottom end of the interconnection structure 30; and the second semiconductor unit 40 is positioned on the surface of the interlayer bonding layer 20, the second semiconductor unit 40 and the first semiconductor unit 10 are respectively positioned on two opposite sides of the interlayer bonding layer 20, a second TSV structure 102 is arranged in the second semiconductor unit 40, and the second TSV structure 102 is in contact with the top end of the interconnection structure 30.

The semiconductor structure provided in the present embodiment will be described in detail below with reference to the accompanying drawings.

In this embodiment, the semiconductor structure is a 3D semiconductor structure, and may include a DRAM chip, and a logic chip, for example. The first TSV structure 101 on the upper layer and the second TSV structure 102 on the lower layer are electrically connected through the interconnection structure 30 including the conductive layer, a scheme that a solder ball or a copper column is used for electrical connection in the prior art is replaced, and the thickness of the interconnection structure 30 including the conductive layer can be set to be smaller, so that the vertical distance between the first TSV structure 101 and the second TSV structure 102 is small, the resistance value between the first TSV structure 101 and the second TSV structure 102 is favorably reduced, and the overall thickness of the semiconductor structure is favorably reduced.

The first semiconductor unit 10 includes a first wafer or a first chip, and the second semiconductor unit 40 includes a first wafer or a second chip.

The wafer and the chip are mainly distinguished as follows: the wafer can be manufactured by adopting an integrated circuit manufacturing technology, for example, an NMOS device, a PMOS device, a CMOS device and the like are formed on a substrate through deposition, etching, doping and other processes, and a dielectric layer, an interconnection structure, a pad electrically connected with the interconnection structure and other structures are formed on the devices, so that a plurality of chips are formed in the wafer; and cutting the wafer to form a plurality of chips.

The chip may be an active component, a passive component, a micro-electro-mechanical system, or an optical component. Specifically, the chip may be a memory chip, a communication chip, a processing chip, a flash memory chip, a logic chip, or a specific function chip, distinguished by function type, for example, the processing chip may be an image sensor chip, a temperature sensor chip, a pressure sensor chip, or the like, and the specific function chip may be a chip developed for some specific functions, for example, a Wifi chip, a bluetooth chip, a power management chip, or the like.

In this embodiment, taking the first semiconductor unit 10 as a first chip and the second semiconductor unit 40 as a second chip as an example, the types of the first chip and the second chip may be the same or different.

The first semiconductor unit 10 includes a first substrate 11 and a first functional stack 12 located on a surface of the first substrate 11, where a surface of the first functional stack 12 is a top surface of the first semiconductor unit 10. In this embodiment, the first TSV structure 101 penetrates the first substrate 11 and the first functional stack 12.

In this embodiment, the first substrate 11 is a silicon substrate. In other embodiments, the first substrate may also be a germanium substrate, a silicon carbide substrate, a III-V substrate, a sapphire substrate, or the like. The first functional stack 12 includes at least one dielectric layer (dielectric layer) and an interconnect layer located in the dielectric layer, and the first functional stack 12 further has a gate structure of an NMOS transistor, a PMOS transistor, or a CMOS transistor.

The second semiconductor unit 40 includes a second substrate 41 and a second functional stack 42 on a surface of the second substrate 41. The second substrate 41 faces the first semiconductor unit 10. For a detailed description of the second substrate 41 and the second functional stack 42, reference may be made to the foregoing detailed description of the first substrate 11 and the second functional stack 12.

In this embodiment, the second TSV structure 102 is exposed on the top surface of the second semiconductor unit 40, that is, the second functional stack 42 exposes the second TSV structure 102, so as to facilitate electrical connection between the second TSV structure 102 and other semiconductor units located above the second TSV structure.

The function of the interlayer bonding layer 20 includes providing a spatial location for providing an interconnect structure 30 that electrically connects the first TSV structure 101 and the second TSV structure 102. The interlayer bonding layer 20 is made of a dielectric material. In this embodiment, the interlayer bonding layer is made of an organic dielectric material. In other embodiments, the material of the interlayer bonding layer may also be an inorganic dielectric material.

The interconnect structure 30 includes: a bottom conductive layer located on the top surface of the first semiconductor unit 10, the bottom conductive layer having a first front surface and a first back surface opposite to the first front surface, and the first back surface of the bottom conductive layer contacting the first TSV structure 101. The bottom end of the interconnect structure 30 is flush with the backside of the interlayer bonding layer 20.

Compared with a solder ball or a copper column, the thickness of the layered bottom conductive layer can be set to be smaller, so that the vertical distance between the first TSV structure 101 and the second TSV structure 102 is correspondingly smaller, and the thickness of the corresponding interlayer bonding layer 20 is correspondingly smaller, thereby being beneficial to reducing the overall thickness of the semiconductor structure and reducing the resistance value between the first TSV structure 101 and the second TSV structure 102. The bottom conductive Layer may be formed using a Redistribution Layer (RDL) process.

In this embodiment, taking the example that the interconnect structure 30 includes a single conductive layer as an example, the interconnect structure 30 is a bottom conductive layer 30. Accordingly, the second TSV structure 102 is in contact with the first front side of the underlying conductive layer 30.

The thickness of the interconnect structure 30 in a direction along the first semiconductor unit 10 towards the second semiconductor unit 40 is the distance between the top end of the interconnect structure 30 and the bottom end of the interconnect structure 30. The thickness of the interconnect structure 30 is not too small nor too large in a direction pointing along the first semiconductor unit 10 towards the second semiconductor unit 40. If the thickness of the interconnection structure 30 is too small, the uniformity of the thickness of the interconnection structure 30 is relatively poor, which tends to cause the electrical connection performance between the first TSV structure 101 and the second TSV structure 102 to be poor; if the thickness of the interconnect structure 30 is too large, it is not beneficial to reduce the overall thickness of the semiconductor structure.

In the present embodiment, the thickness of the interconnect structure 30 in a direction pointing along the first semiconductor unit 10 towards the second semiconductor unit 40 is in the range of 0.4 μm to 10 μm, for example 1 μm, 3 μm, 5.5 μm, 7 μm or 9.5 μm. When the interconnect structure 30 includes a single conductive layer, the thickness of the underlying conductive layer is in the range of 0.4 μm to 10 μm.

In this embodiment, in a direction pointing to the second semiconductor unit 40 along the first semiconductor unit 10, the thickness of the interlayer bonding layer 20 is greater than that of the interconnection structure 30, and accordingly, the second TSV structure 102 is also located in the interlayer bonding layer 20 with a partial thickness, which is beneficial to improving the bonding force between the second semiconductor unit 40 and the interlayer bonding layer 20 and improving the reliability of the semiconductor structure.

FIG. 2 is a cross-sectional view of another semiconductor structure. In other embodiments, as shown in fig. 2, the thickness of the interlayer bonding layer 20 may also be equal to the thickness of the interconnection structure 30 in the direction pointing to the second semiconductor unit 40 along the first semiconductor unit 10, and accordingly, the top end of the interconnection structure 30 is flush with the surface of the interlayer bonding layer 20, and the second TSV structure 102 is not disposed in the interlayer bonding layer 20.

In this embodiment, the interconnect structure 30 includes a single conductive layer, but in other embodiments, the interconnect structure may further include at least two conductive layers,

FIG. 3 is a cross-sectional view of another semiconductor structure.

As shown in fig. 3, the interconnect structure 30 includes, in addition to the bottom conductive layer 31: a top conductive layer 32, wherein the top conductive layer 32 has a second front surface and a second back surface opposite to the second front surface, wherein the second back surface is opposite to the first front surface of the bottom conductive layer 31, and the second front surface of the top conductive layer 32 is in contact with the second TSV structure 102; an intermediate interconnect structure electrically connecting the first front surface and the second back surface of the underlying conductive layer 31.

The second front surface of the top conductive layer 32 is the top of the interconnect structure 30. Taking the second front surface of the top conductive layer 32 located in the interlayer bonding layer 20 as an example, in other embodiments, the second front surface of the top conductive layer may also be flush with the surface of the interlayer bonding layer, which exposes the second front surface of the top conductive layer.

Wherein the intermediate interconnect structure comprises: and a conductive plug 33, wherein one end of the conductive plug 33 is contacted with the first front surface of the bottom conductive layer 31, and the other end of the conductive plug 33 is contacted with the second back surface of the top conductive layer 32. It should be noted that, in other embodiments, the intermediate interconnect structure may further include: at least one intermediate conductive layer; and the conductive plugs are respectively electrically connected with the bottom conductive layer and the middle conductive layer and electrically connected with the middle conductive layer and the upper conductive layer.

The number of conductive layers in the interconnection structure 30 is reasonably set, so that the length of the second TSV structure 102 contacting the top end of the interconnection structure 30 is more flexibly set, for example, the number of conductive layers in the interconnection structure 30 is reasonably increased, so that the length of the second TSV structure 102 is relatively short, and the difficulty in the formation process of the second TSV structure 102 is favorably reduced.

In addition, the number of layers and the position distribution of the conductive layers in the interconnection structure 30 are reasonably set to meet the requirements of different distribution and arrangement of signals, so that different design requirements or electrical signal connection requirements are met.

It should be noted that, for convenience of illustration, only two first TSV structures 101 and two second TSV structures 102 are shown, in other embodiments, the number of the first TSV structures in the semiconductor structure may be any number, the number of the second TSV structures may also be any number, and the number of the second TSV structures is the same as the number of the first TSV structures.

In this embodiment, when the number of the second TSV structures is at least two, the lengths of all the second TSV structures are the same in the direction pointing to the second semiconductor unit along the first semiconductor unit, and accordingly, the number of conductive layers in each interconnect structure is the same.

In this embodiment, taking the semiconductor structure including two layers of semiconductor units as an example, in an actual process, the number of layers of semiconductor units in the semiconductor structure may be set according to actual requirements, and the multiple layers of semiconductor units are stacked in a vertical direction, and any one of the layers of semiconductor units serves as both the second semiconductor unit of the next layer of semiconductor unit and the first semiconductor unit of the previous layer of semiconductor unit.

The utility model discloses another embodiment still provides a semiconductor structure, and is different from the preceding embodiment in that, in this embodiment, the quantity of second TSV structure is more than two or two, and in the direction along the directional second semiconductor unit of first semiconductor unit, all the length of second TSV structure is not identical, corresponding, all the number of piles of conducting layer among the interconnect structure is not identical. Fig. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 4, a semiconductor structure includes: a first semiconductor unit 200 and a first TSV structure 201 located in the first semiconductor unit 200; an interlayer bonding layer 203, wherein the interlayer bonding layer 203 has an interconnection structure therein, the interconnection structure comprises at least one conductive layer, the interconnection structure has a top end and a bottom end opposite to the top end, and the first TSV structure 201 is in contact with the bottom end of the interconnection structure; and the second semiconductor unit 205 is positioned on the surface of the interlayer bonding layer 203, the second semiconductor unit 205 and the first semiconductor unit 200 are respectively positioned on two opposite sides of the interlayer bonding layer 203, a second TSV structure 206 is arranged in the second semiconductor unit 205, and the second TSV structure 206 is also in contact with the top end of the interconnection structure 204.

The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, and it should be noted that the same or corresponding portions as those in the previous embodiment will not be described in detail below.

The first semiconductor unit 200 includes a first substrate 21 and a first functional stack 22 located on a surface of the first substrate 21, where a surface of the first functional stack 22 is a top surface of the first semiconductor unit 200. In this embodiment, the first TSV structure 201 penetrates the first substrate 21 and the first functional stack 22.

The second semiconductor unit 205 includes a second substrate 51 and a second functional stack 52 on a surface of the second substrate 51. The second substrate 51 faces the first semiconductor unit 200.

For a detailed description of the second semiconductor unit 205 and the first semiconductor unit 200, reference may be made to the corresponding description of the foregoing embodiments, which are not repeated herein. In this embodiment, the number of the second TSV structures 206 is two or more, and the lengths of all the second TSV structures 206 are not completely the same in the direction pointing to the second semiconductor unit 205 along the first semiconductor unit 200; the number of conductive layers in all of the interconnect structures is not exactly the same. For ease of illustration, only two second TSV structures 206 are shown in fig. 4.

The interconnect structure includes: a first interconnect structure (not labeled) and a second interconnect structure 204, and the number of conductive layers in the first interconnect structure is different from the number of conductive layers in the second interconnect structure 204.

The first interconnect structure includes: a bottom conductive layer 214, the bottom conductive layer 214 being located on the top surface of the first semiconductor unit 200, the bottom conductive layer 214 having a first front surface and a first back surface opposite to the first front surface, the first back surface of the bottom conductive layer 214 being in contact with the first TSV structure 201, and the first front surface of the bottom conductive layer 214 being in contact with the second TSV structure 206.

The second interconnect structure 204 includes: a bottom conductive layer 214, wherein the bottom conductive layer 214 is located on the top surface of the first semiconductor unit 200, the bottom conductive layer 214 has a first front surface and a first back surface opposite to the first front surface, and the first back surface of the bottom conductive layer 214 is in contact with the first TSV structure 201; a top conductive layer 224, the top conductive layer 224 having a second front side and a second back side opposite the second front side, wherein the second back side is opposite the first front side, and the second front side of the top conductive layer 224 is in contact with the second TSV structure 206; an intermediate interconnect structure electrically connecting the first front side and the second back side.

Wherein the bottom conductive layer 214 in the first interconnect structure is at the same level as the bottom conductive layer 214 in the second interconnect structure 204 and is spaced apart from each other.

In this embodiment, the intermediate interconnect structure includes: a conductive plug 234, one end of the conductive plug 234 contacting the first front surface of the bottom conductive layer 214, and the other end of the conductive plug 234 contacting the second back surface. In other embodiments, the intermediate interconnect structure may further include at least one intermediate conductive layer.

In the semiconductor structure provided by this embodiment, the number of conductive layers in different interconnect structures is reasonably arranged, so that the second TSV structures 206 with different lengths can be electrically connected to the corresponding first TSV structures 201.

It should be noted that, in this embodiment, the semiconductor structure includes two layers of semiconductor units as an example, in other embodiments, the number of layers of the semiconductor units included in the semiconductor structure may also be set reasonably according to actual requirements, and an interlayer bonding layer is disposed between adjacent layers of semiconductor units.

Fig. 5 to 7 are SEM (scanning electron microscope) comparison views of a semiconductor structure according to an embodiment of the present invention and a conventional semiconductor structure. Take the example where the semiconductor structure comprises a DRAM chip.

In fig. 5, the left diagram shows a local cross-section SEM schematic diagram of a semiconductor structure formed by 4 DRAM chips and a single logic chip in the prior art, and the right diagram shows a local cross-section SEM schematic diagram of a semiconductor structure formed by 4 DRAM chips and a single logic chip in the embodiment of the present invention, and the semiconductor structure in the right diagram includes: a first semiconductor unit 500 and a first TSV structure 501 located in the first semiconductor unit 500; an interlayer bonding layer 503 having an interconnect structure (not labeled) therein; a second semiconductor unit 505 and a second TSV structure 506 located in the second semiconductor unit 505. Wherein, taking the thickness of the DRAM chips in the prior art and the embodiment of the utility model as an example, the distance between the DRAM chips of the prior adjacent layers is 50 μm; the embodiment of the utility model provides a semiconductor structure's thickness is thinner 200 mu m than present, can practice thrift the thickness of 2 DRAM chips.

In fig. 6, the left diagram shows a local cross-section SEM schematic diagram of a semiconductor structure composed of 4 DRAM chips, and the right diagram shows a local cross-section SEM schematic diagram of a semiconductor structure composed of 4 DRAM chips, where the semiconductor structure includes: a first semiconductor unit 600 and a first TSV structure 601 located in the first semiconductor unit 600; an interlayer bonding layer 603 having an interconnect structure (not labeled) within the interlayer bonding layer 603; a second semiconductor unit 605 and a second TSV structure 606 located in the second semiconductor unit 605. Wherein, taking the thickness of the DRAM chips in the prior art and the embodiment of the utility model as an example, the distance between the DRAM chips of the prior adjacent layers is 20 μm; the embodiment of the utility model provides a semiconductor structure's thickness is thinner 60 mu m than present, can practice thrift the thickness of 1 DRAM chip.

In fig. 7, the left diagram shows a local cross-section SEM schematic diagram of a semiconductor structure composed of 8 DRAM chips and a single logic chip, and the right diagram shows a local cross-section SEM schematic diagram of a semiconductor structure composed of 8 DRAM chips and a single logic chip, provided by the embodiment of the present invention, and the semiconductor structure includes in the right diagram: a first semiconductor unit 700 and a first TSV structure 701 located in the first semiconductor unit 700; an interlayer bonding layer 703 having an interconnect structure (not labeled) within the interlayer bonding layer 703; a second semiconductor unit 705, and a second TSV structure 706 located in the second semiconductor unit 705. Wherein, taking the thickness of the DRAM chips in the prior art and the embodiment of the utility model as an example, the distance between the DRAM chips of the prior adjacent layers is 17 μm; the embodiment of the utility model provides a semiconductor structure's thickness is than current thin 136 mu m, can practice thrift the thickness of 2 DRAM chips.

Correspondingly, the embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which can be used to manufacture the above semiconductor structure, including: providing a first semiconductor unit, wherein the first semiconductor unit is provided with a first TSV structure, and the top surface of the first semiconductor unit is exposed out of the first TSV structure; providing a second semiconductor unit; forming an interlayer bonding layer, wherein an interconnection structure is formed in the interlayer bonding layer and comprises at least one conductive layer, the interconnection structure is provided with a top end and a bottom end opposite to the top end, the first semiconductor unit and the second semiconductor unit are respectively positioned on the opposite surfaces of the interlayer bonding layer, and the first TSV structure is in contact with the bottom end of the interconnection structure; forming a second TSV structure through the second semiconductor unit, the second TSV structure also being in contact with a top end of the interconnect structure. The following detailed description will be made in conjunction with the accompanying drawings.

It should be noted that, the number of the second TSV structures is two, and the length of each second TSV structure is different as an example. In other embodiments, the number of the second TSV structures may be any number, and the length of each second TSV structure may also be the same.

Fig. 8 to 10 are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 8, a first semiconductor unit 200 is provided, the first semiconductor unit 200 has a first TSV structure 201 therein, and a top surface of the first semiconductor unit 200 exposes the first TSV structure 201; an interlayer bonding layer 203 is formed on the top surface of the first semiconductor unit 200, an interconnection structure including at least one conductive layer is formed in the interlayer bonding layer 203, the interconnection structure has a top end and a bottom end opposite to the top end, and the first TSV structure 201 is in contact with the bottom end of the interconnection structure.

In this embodiment, the top end of the interconnection structure is located in the interlayer bonding layer 203, and the first TSV structure 201 penetrates through the first semiconductor unit 200.

One of the interconnect structures includes only the underlying conductive layer 214 in contact with the first TSV structure 201; another interconnect structure includes: a bottom conductive layer 214, a top conductive layer 224 on the bottom conductive layer 214, and a conductive plug 234.

For a corresponding description of the first semiconductor unit 200 and the interconnect structure, reference may be made to the corresponding description of the foregoing embodiments, which are not repeated herein. In other embodiments, the interconnect structure may also be only a single conductive layer, or the number of conductive layers of each interconnect structure may also be the same.

Referring to fig. 9, a second semiconductor unit 205 is provided; the second semiconductor unit 205 is bonded to the surface of the interlayer bonding layer 203.

For a corresponding description of the second semiconductor unit 205, reference may be made to the corresponding description of the foregoing embodiments, and further description is omitted here.

After bonding the second semiconductor unit 205 to the surface of the interlayer bonding layer 203, the first semiconductor unit 200 and the second semiconductor unit 205 are respectively located on the surfaces opposite to the interlayer bonding layer 203.

The second semiconductor unit 205 is bonded to the surface of the interlayer bonding layer 203 by one or more of direct bonding (also referred to as fusion bonding) adhesive layer bonding, metal diffusion bonding, or eutectic bonding.

Referring to fig. 10, a second TSV hole 216 is formed in the second semiconductor unit 205 and a portion of the thickness of the interlayer bonding layer 203, and the second TSV hole 216 exposes the top end of the interconnect structure.

In this embodiment, the second semiconductor unit 205 and the interlayer bonding layer 203 are etched by using an etching process until the top end of the interconnection structure is exposed, so as to form a second TSV hole 216. Specifically, one of the second TSV holes 216 exposes the surface of the bottom conductive layer 213, and the other second TSV hole 216 exposes the surface of the top conductive layer 223.

During the etching process, the bottom conductive layer 213 and the top conductive layer 223 in different interconnect structures are respectively used as an etching stop layer.

In this example, Deep Reactive Ion Etching (DRIE) was used for Etching. In other embodiments, a Bosh etching process may also be used for etching.

Referring to fig. 4, the second TSV structure 206 is formed by filling the second TSV hole 216 (see fig. 10) with a conductive material.

In this embodiment, an electroplating process is used to form a conductive material filling the second TSV hole 216 by electroplating, and after the electroplating process is completed, the chemical mechanical polishing process is further performed on the top surface of the second semiconductor unit 205 to remove the conductive material formed by electroplating and located on the top of the second semiconductor unit 205.

It should be noted that in other embodiments, the interlayer bonding layer may also expose the top of the interconnect structure. Correspondingly, the method for forming the second TSV structure comprises the following steps: forming the second TSV structure after bonding the second semiconductor unit to the surface of the interlayer bonding layer; alternatively, the second TSV structure is formed before bonding the second semiconductor unit to the interlayer bonding layer.

The subsequent process steps further comprise: bonding a semiconductor unit on the second semiconductor unit 205 with an interlayer bonding layer provided between the second semiconductor unit 205 and the semiconductor unit; according to actual process requirements, a plurality of semiconductor units are stacked in a direction perpendicular to the surface of the second semiconductor unit 205; then, a dicing process is performed.

Another embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which is different from the previous embodiment in that, in the present embodiment, after the interlayer bonding layer is formed on the bottom surface of the second semiconductor unit, the interlayer bonding layer is bonded to the top surface of the first semiconductor unit. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 11 to 13 are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 11, a second semiconductor unit 305 is provided; an interlayer bonding layer 303 is formed on the bottom surface of the second semiconductor unit 305.

The interconnect structure has a top end and a bottom end opposite to the top end, wherein the end of the interconnect structure near the second semiconductor unit 305 is the top end, and the end of the interconnect structure far from the second semiconductor unit 305 is the bottom end.

In this embodiment, the top of the interconnect structure is located within the interlayer bonding layer 303. One of the interconnect structures includes only the bottom conductive layer 314, and the bottom of the interlayer bonding layer 303 exposes the surface of the bottom conductive layer 314. Another interconnect structure includes: a bottom conductive layer 314, a top conductive layer 324 on the bottom conductive layer 314, and a conductive plug 334.

For the corresponding description of the interconnect structure, reference may be made to the corresponding description of the foregoing embodiments, which are not repeated herein.

Referring to fig. 12, a first semiconductor unit 300 is provided, the first semiconductor unit 300 has a first TSV structure 301 therein, and a top surface of the first semiconductor unit 300 exposes the first TSV structure 301; the interlayer bonding layer 303 is bonded to the top surface of the first semiconductor unit 300.

In this embodiment, the interlayer bonding layer 303 is bonded to the top surface of the first semiconductor unit 300 by a direct bonding process. In other embodiments, the bonding process may also be a metal diffusion bonding or eutectic bonding.

The first TSV structure 301 is in contact with the bottom conductive layer 314.

Referring to fig. 13, a second TSV structure 306 is formed, the second TSV structure 306 penetrating the second semiconductor unit 305 and electrically connected to the top end of the interconnect structure.

For the process steps for forming the second TSV structure 306, reference may be made to the corresponding descriptions of the foregoing embodiments, which are not repeated herein.

In this embodiment, one second TSV structure 306 is in contact with the bottom conductive layer 314, and the other second TSV structure 306 is in contact with the top conductive layer 314.

In this embodiment, the second TSV structure 306 is formed after the interlayer bonding layer 303 is bonded to the top surface of the first semiconductor unit 300. In other embodiments, the second TSV structure may also be formed after forming the interlayer bonding layer on the bottom surface of the second semiconductor unit and before bonding the interlayer bonding layer to the top surface of the first semiconductor unit.

It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A semiconductor structure, comprising:

the device comprises a first semiconductor unit and a first TSV structure positioned in the first semiconductor unit, wherein the first TSV structure is exposed out of the top surface of the first semiconductor unit;

an interlayer bonding layer on the top surface of the first semiconductor unit, wherein the interlayer bonding layer is internally provided with an interconnection structure, the interconnection structure comprises at least one conductive layer, the interconnection structure is provided with a top end and a bottom end opposite to the top end, and the first TSV structure is in contact with the bottom end of the interconnection structure;

the second semiconductor unit and the first semiconductor unit are respectively positioned on two opposite sides of the interlayer bonding layer, a second TSV structure is arranged in the second semiconductor unit, and the second TSV structure is in contact with the top end of the interconnection structure.

2. The semiconductor structure of claim 1, wherein a thickness of the interconnect structure is in a range of 0.4 μ ι η to 10 μ ι η in a direction along the first semiconductor unit toward the second semiconductor unit.

3. The semiconductor structure of claim 1 or 2, wherein the interconnect structure comprises: the bottom conducting layer is positioned on the top surface of the first semiconductor unit and provided with a first front surface and a first back surface opposite to the first front surface, and the first back surface of the bottom conducting layer is in contact with the first TSV structure.

4. The semiconductor structure of claim 3, wherein a first front side of the bottom conductive layer is in contact with the second TSV structure.

5. The semiconductor structure of claim 3, wherein the interconnect structure further comprises: a top conductive layer having a second front side and a second back side opposite the second front side, wherein the second back side is opposite the first front side, and the second front side of the top conductive layer is in contact with the second TSV structure; an intermediate interconnect structure electrically connecting the first front side and the second back side.

6. The semiconductor structure of claim 5, wherein the intermediate interconnect structure comprises: and one end of the conductive plug is contacted with the first front surface of the bottom conductive layer, and the other end of the conductive plug is contacted with the second back surface.

7. The semiconductor structure of claim 5, wherein the intermediate interconnect structure further comprises at least one intermediate conductive layer.

8. The semiconductor structure of claim 1, wherein the second TSV structure is exposed at a top surface of the second semiconductor unit.

9. The semiconductor structure of claim 1, wherein the first semiconductor unit comprises a first wafer or a first chip; the second semiconductor unit includes a second wafer or a second chip.

10. The semiconductor structure of claim 1, wherein a thickness of the interlayer bonding layer is equal to a thickness of the interconnect structure in a direction pointing along the first semiconductor unit toward the second semiconductor unit.

11. The semiconductor structure according to claim 1, wherein a thickness of the interlayer bonding layer is larger than a thickness of the interconnect structure in a direction pointing from the first semiconductor unit to the second semiconductor unit; and the second TSV structure is also located within a partial thickness of the interlayer junction layer.

12. The semiconductor structure of claim 1, wherein the number of the second TSV structures is two or more, and the lengths of all the second TSV structures are not exactly the same in a direction along the first semiconductor unit toward the second semiconductor unit; the number of conductive layers in all of the interconnect structures is not exactly the same.

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