CN105428331A - Carrier-based fan-out 2.5D/3D package structure - Google Patents
Carrier-based fan-out 2.5D/3D package structure Download PDFInfo
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- CN105428331A CN105428331A CN201510969543.9A CN201510969543A CN105428331A CN 105428331 A CN105428331 A CN 105428331A CN 201510969543 A CN201510969543 A CN 201510969543A CN 105428331 A CN105428331 A CN 105428331A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The invention belongs to the field of electronic packaging, and particularly relates to a carrier-based fan-out 2.5D/3D package structure, which comprises a TSV adapter plate, flip chips, an underfill adhesive, a molding compound, a BGA solder ball and the like, wherein the flip chips are inversely welded on the front surface of the TSV adapter plate; the molding compound packages all the chips and the TSV adapter plate; and the BGA solder ball is implanted into the back surface of the TSV adapter plate. According to the carrier-based fan-out 2.5D/3D package structure, system-in-package is achieved by combining a fan-out technology and an adapter plate technology; the production cost is reduced; reduction of warping is facilitated; the chip offset is reduced; and the feasibility of the process and the reliability of a package body are improved.
Description
Technical field
The invention belongs to Electronic Packaging field, particularly relate to a kind of fan-out 2.5/3D encapsulating structure based on carrier.
Background technology
Along with the requirement drive of consumer electronics product, as smart mobile phone, panel computer etc., the encapsulating face of electronic product is to future development that is thin, little and low cost.The current Advanced Packaging method about 2.5D and 3D has obtained the concern of industry, and obtains certain development result.But be faced with the high predicament of many technical barriers and cost based on the Advanced Packaging design of silicon through hole.
Fan-out encapsulation is a kind of new Advanced Packaging method released in recent years, and its conventional package advantage combining wafer-level packaging manufacturing technology and single nude film at first carries out batch micro operations, thus considerably reduces the packaging cost of electronic product.Typical fan-out packaging technology flow process, is first mounted on silicon wafer carrier by nude film front, tears carrier wafer open bonding after plastic packaging, makes RDL(wiring layer more thereafter) and plant ball, reliability testing and product packaging are done in finally section.
At present, no matter be that the encapsulation of wafer scale fan-out or the encapsulation of plate level fan-out all face two large technological challenges, one is warpage issues, and two is chip offset.Warpage issues mainly owing to have employed the encapsulating material of different heat expansion coefficient in packaging technology, as plastic packaging material, chip and carrier etc.If the storeroom thermal coefficient of expansion adopted does not mate, several millimeters, the even large warpage of tens millimeters can be caused.Chip offset mainly causes because harmomegathus occurs plastic packaging material in curing process.Therefore the reliability effect of plastic packaging material to whole encapsulating structure should not be underestimated.
Summary of the invention
In order to solve above technical problem, the invention provides a kind of fan-out 2.5/3D encapsulating structure based on carrier, this encapsulating structure combines fan-out and keyset technology realizes system in package, compare traditional 2.5D/3D to encapsulate, reduce thickness, reduce production cost, be conducive to reducing warpage, reduce chip offset amount, improve the feasibility of technique and the reliability of packaging body.
Solve a kind of fan-out 2.5/3D encapsulating structure based on carrier in the present invention of above technical problem, it is characterized in that: comprise TSV keyset, flip-chip, underfill, plastic packaging material, BGA soldered ball, flip-chip flip chip bonding is in the front of TSV keyset; Plastic packaging material encapsulating flip-chip and TSV keyset, and the exposed TSV keyset back side; BGA soldered ball is planted at the TSV keyset back side, and underfill is between flip-chip and TSV keyset.
Described flip-chip is single bare chip, or many bare chips, or single group multiple-level stack chip assembly, or some groups of multiple-level stack chip assemblies, or the combination of bare chip and multiple-level stack chip.
Described single bare chip flip chip bonding is on each TSV keyset; Described many bare chips difference flip chip bonding is on each TSV keyset; Described single group multiple-level stack chip assembly is assembled on each TSV keyset; Described some groups of multiple-level stack chip assemblies are assembled on each TSV keyset respectively; Described bare chip and multiple-level stack chip are assembled on each TSV keyset respectively.
Described TSV keyset is silicon keyset, and silicon keyset is provided with silicon through hole, electro-coppering in silicon through hole; TSV keyset front and back is respectively equipped with wiring layer I and II again.
There is multilayer wiring layer I again in described TSV keyset front, then has micro convex point between wiring layer I and flip-chip.
Passivation layer 1, Seed Layer 1, again wiring layer II is also provided with successively, passivation layer 2, Seed Layer 2, UBM bottom metal layers between the described TSV keyset back side and BGA soldered ball.
Described Seed Layer 1, again wiring layer II, Seed Layer 2 and the interconnection of UBM bottom metal layers.
Described flip-chip is by micro convex point, again wiring layer I, keyset silicon through hole, again wiring layer II, UBM bottom metal layers and the interconnection of BGA ball.
Described passivation material is PI or PBO, and seed layer materials is Ti/Cu.
The thickness of described wiring layer is again about 3 ~ 5 μm, and material is copper.Chips of the present invention is interconnected by the front RDL of TSV keyset, is then drawn by silicon through hole and fans out on BGA soldered ball below, to weld with pcb board.Use TSV keyset, effectively have compressed taking up room of packaged chip, the plastic-sealed body that plastic packaging is formed is thinner, is conducive to reducing the chip to be packaged impact different from plastic-sealed body thermal coefficient of expansion.And structure is simple, makes production cost low.
Structure in the present invention combines wafer level fan-out technology and keyset technology realizes system in package, reduces production cost; Can amount of warpage be reduced, reduce chip offset amount, be conducive to the feasibility improving technique.
Accompanying drawing explanation
Fig. 1 is encapsulating structure schematic diagram in the present invention
Fig. 2 be in the present invention single front with the TSV keyset of wiring layer again
Fig. 3-13 is that in the present invention, encapsulating structure forms the structural representation in flow process
Wherein, in figure, mark is specially: 1.TSV keyset, 2. flip-chip, 3. underfill, 4. plastic packaging material, 5.BGA soldered ball, 6. keyset silicon through hole, 7. wiring layer I again, 8. wiring layer II again, 9. micro convex point, 10. passivation layer 1,11. Seed Layer 1,12. passivation layer 2., 13. Seed Layer 2,14.UBM bottom metal layers, 15. temporary adhesion glue, 16. support plates
Embodiment
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Arbitrary feature disclosed in this specification (comprising any accessory claim, summary), unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object.That is, unless specifically stated otherwise, each feature is an example in a series of equivalence or similar characteristics.
Embodiment 1
Based on a fan-out 2.5/3D encapsulating structure for carrier, comprise TSV keyset, flip-chip, underfill, plastic packaging material, BGA soldered ball, flip-chip flip chip bonding is in the front of TSV keyset; Plastic packaging material encapsulating flip-chip and TSV keyset, and the exposed TSV keyset back side; BGA soldered ball is planted at the TSV keyset back side, and underfill is between flip-chip and TSV keyset.
Flip-chip is single bare chip, or many bare chips, or single group multiple-level stack chip assembly, or some groups of multiple-level stack chip assemblies.Single bare chip flip chip bonding is on each TSV keyset; Described many bare chips difference flip chip bonding is on each TSV keyset; Described single group multiple-level stack chip assembly is assembled on each TSV keyset; Described some groups of multiple-level stack chip assemblies are assembled on each TSV keyset respectively.
TSV keyset is silicon keyset, and silicon keyset is provided with silicon through hole, electro-coppering in silicon through hole; TSV keyset front and back is respectively equipped with 1 layer of wiring layer I and wiring layer II more again.The thickness of wiring layer I or II is about 3 ~ 5 μm again, and material is copper.
Also be provided with successively between the TSV keyset back side and BGA soldered ball and be followed successively by passivation layer 1, Seed Layer 1, again wiring layer II, passivation layer 2, Seed Layer 2, UBM bottom metal layers.Passivation material is PI or PBO, and seed layer materials is Ti/Cu.
Seed Layer 1, again wiring layer II, Seed Layer 2 and the interconnection of UBM bottom metal layers.Flip-chip is by wiring layer I, keyset silicon through hole, again wiring layer II, UBM bottom metal layers and the interconnection of BGA ball again.
Embodiment 2
Based on a fan-out 2.5/3D encapsulating structure for carrier, comprise TSV keyset, flip-chip, underfill, plastic packaging material, BGA soldered ball, flip-chip flip chip bonding is in the front of TSV keyset; Plastic packaging material encapsulating flip-chip and TSV keyset, and the exposed TSV keyset back side; BGA soldered ball is planted at the TSV keyset back side, and underfill is between flip-chip and TSV keyset.
Flip-chip is the combination of bare chip and multiple-level stack chip, and bare chip and multiple-level stack chip are assembled on each TSV keyset respectively.
TSV keyset is silicon keyset, and silicon keyset is provided with silicon through hole, electro-coppering in silicon through hole; TSV keyset front and back is respectively equipped with 3 layers of wiring layer I and wiring layer II more again.Micro convex point is had again between wiring layer I and flip-chip.The thickness of wiring layer I or II is about 3 ~ 5 μm again, and material is copper.
Passivation layer 1, Seed Layer 1, again wiring layer II is also provided with successively, passivation layer 2, Seed Layer 2, bottom metal layers between the TSV keyset back side and BGA soldered ball.Passivation material is PI or PBO, and seed layer materials is Ti/Cu.
Seed Layer 1, again wiring layer II, Seed Layer 2 and the interconnection of UBM bottom metal layers.Flip-chip is by micro convex point, again wiring layer I, keyset silicon through hole, again wiring layer II, UBM bottom metal layers and the interconnection of BGA ball.
Be described in detail below in conjunction with the formation of accompanying drawing to the structure in the present invention:
(1) the TSV keyset of multilayer wiring layer is more just being worn in preparation, and the thickness of every layer of wiring layer is again about 3 ~ 5 μm, and material is copper, and below thinning back side to 200 μm, back side dew TSV copper facing also cuts list, as shown in Figure 4;
(2) 2.5D/3D encapsulating structure needs support plate in manufacturing process, and support plate shape is square or circular, the optional silicon of circular carrier plate material or glass etc.; The optional glass of square support plate or double face copper etc.
(3) on support plate, apply ephemeral key rubber alloy, be used for pasting keyset and follow-up tear bonding open, as shown in Figure 5, the optional silicon of described circular carrier plate material, glass and kovar alloy material etc.;
(4) TSV keyset array is affixed on support plate, be covered with circular support plate, face up, as shown in Figure 6;
(5) flip-chip upside-down mounting is soldered on each keyset, and fills underfill, as shown in Figure 7;
Flip-chip is single bare chip, or many bare chips, or single group multiple-level stack chip assembly, or some groups of multiple-level stack chip assemblies, or the combination of bare chip and multiple-level stack chip.
Single bare chip flip chip bonding is on each TSV keyset; Described many bare chips difference flip chip bonding is on each TSV keyset; If single group multiple-level stack chip assembly is assembled on each TSV keyset; If some groups of multiple-level stack chip assemblies are assembled on each TSV keyset respectively; If bare chip and multiple-level stack chip are assembled on each TSV keyset respectively.
(6) or compressing and forming process shaping by metaideophone or other plastic package process are by between plastic packaging rubber seal to each keyset, between chip and the upper surface of chip, and carry out Post RDBMS process, as shown in Figure 8;
(7) bonding is torn to circular or square support plate open, dismantle circular or square support plate, as shown in Figure 9;
(8) overturn 180 °, make one deck passivation layer at the keyset back side, window, passivation material is PI or PBO, sputtering one deck Seed Layer, and seed layer materials is Ti/Cu, and the keyset back side makes one deck RDL; Sputtering one deck Seed Layer, makes UBM bottom metal layers, plants BGA soldered ball, cut into slices and test.As shown in Figure 10-Figure 13;
Through above-mentioned steps, completion system level encapsulation substantially.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature of disclosing in this manual or any combination newly, and the step of the arbitrary new method disclosed or process or any combination newly.
Claims (10)
1. the fan-out 2.5D/3D encapsulating structure based on carrier, it is characterized in that: comprise TSV keyset (1), flip-chip (2), underfill (3), plastic packaging material (4), BGA soldered ball (5), flip-chip (2) flip chip bonding is in the front of TSV keyset (1); Plastic packaging material (4) encapsulating flip-chip (2) and TSV keyset (1), and exposed TSV keyset (1) back side; BGA soldered ball (5) is planted at TSV keyset (1) back side, and underfill (3) is positioned between flip-chip (2) and TSV keyset (1).
2. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 1, it is characterized in that: described flip-chip (2) is single bare chip, or many bare chips, or single group multiple-level stack chip assembly, or some groups of multiple-level stack chip assemblies, or the combination of bare chip and multiple-level stack chip.
3. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 2, is characterized in that: described single bare chip flip chip bonding is on each TSV keyset (1); Described many bare chips difference flip chip bonding is on each TSV keyset (1); Described single group multiple-level stack chip assembly is assembled on each TSV keyset (1); Described some groups of multiple-level stack chip assemblies are assembled on each TSV keyset (1) respectively; Described bare chip and multiple-level stack chip are assembled on each TSV keyset (1) respectively.
4. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 1, is characterized in that: described TSV keyset (1) is silicon keyset, and silicon keyset is provided with keyset silicon through hole (6), electro-coppering in keyset silicon through hole; TSV keyset (1) front and back is respectively equipped with wiring layer I (7) and wiring layer II (8) more again.
5. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 1, is characterized in that: there is multilayer wiring layer I (7) again in described TSV keyset (1) front, then has micro convex point (9) between wiring layer I (7) and flip-chip (2).
6. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 1, it is characterized in that: between described TSV keyset (1) back side and BGA soldered ball (5), be also provided with passivation layer 1(10 successively), Seed Layer 1(11), wiring layer II (8), passivation layer 2(12 again), Seed Layer 2(13), UBM bottom metal layers (14).
7. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 6, is characterized in that: described Seed Layer 1(11), wiring layer II (8), Seed Layer 2(13 again) and UBM bottom metal layers (14) interconnection.
8. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 1, is characterized in that: described flip-chip (2) is by micro convex point (9), again wiring layer I (7), keyset silicon through hole (6), again wiring layer II (8), UBM bottom metal layers (14) and BGA soldered ball (5) interconnection.
9. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to claim 6, it is characterized in that: described passivation material is PI or PBO, seed layer materials is Ti/Cu.
10. a kind of fan-out 2.5/3D encapsulating structure based on carrier according to any one of claim 4-8, is characterized in that: the thickness of described wiring layer again I (7) or again wiring layer II (8) is about 3 ~ 5 μm, and material is copper.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510969543.9A CN105428331B (en) | 2015-12-22 | 2015-12-22 | It is a kind of that 2.5D/3D encapsulating structures are fanned out to based on carrier |
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| CN201510969543.9A CN105428331B (en) | 2015-12-22 | 2015-12-22 | It is a kind of that 2.5D/3D encapsulating structures are fanned out to based on carrier |
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| CN105428331B CN105428331B (en) | 2018-04-20 |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106783760A (en) * | 2016-12-26 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | Chip-packaging structure and method |
| CN106783776A (en) * | 2016-12-26 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | Chip-packaging structure and method |
| CN106960825A (en) * | 2017-03-08 | 2017-07-18 | 华进半导体封装先导技术研发中心有限公司 | A kind of two-sided fan-out packaging structure and method for packing based on silicon pinboard |
| CN107611045A (en) * | 2017-09-29 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | A kind of three-dimensional chip encapsulating structure and its method for packing |
| CN109945852A (en) * | 2019-03-22 | 2019-06-28 | 中国科学院微电子研究所 | The encapsulating structure and production method of gyroscope |
| CN110071047A (en) * | 2019-04-28 | 2019-07-30 | 北京航天控制仪器研究所 | A kind of silicon substrate pinboard production method of the integrated application of micro-system |
| CN110634832A (en) * | 2019-08-29 | 2019-12-31 | 上海先方半导体有限公司 | Packaging structure based on through silicon via adapter plate and manufacturing method thereof |
| CN110676240A (en) * | 2019-10-16 | 2020-01-10 | 上海先方半导体有限公司 | 2.5D packaging structure and manufacturing method thereof |
| WO2021119924A1 (en) * | 2019-12-16 | 2021-06-24 | 华为技术有限公司 | Chip stack structure and manufacturing method therefor |
| CN113066771A (en) * | 2021-03-23 | 2021-07-02 | 浙江集迈科微电子有限公司 | Multilayer stacks microsystem structure |
| CN113192936A (en) * | 2021-04-23 | 2021-07-30 | 泓林微电子（昆山）有限公司 | Double-sided chip packaging structure |
| CN114334946A (en) * | 2021-12-09 | 2022-04-12 | 江苏长电科技股份有限公司 | Packaging structure and manufacturing method |
| WO2022151572A1 (en) * | 2021-01-18 | 2022-07-21 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure for reducing warpage of molded wafer, and manufacturing method therefor |
| CN115312496A (en) * | 2022-07-12 | 2022-11-08 | 武汉大学 | Three-dimensional semiconductor integrated packaging structure and process based on rear through hole technology |
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