CN113066771B - Multilayer stacked microsystem structure - Google Patents
Multilayer stacked microsystem structure Download PDFInfo
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- CN113066771B CN113066771B CN202110309148.3A CN202110309148A CN113066771B CN 113066771 B CN113066771 B CN 113066771B CN 202110309148 A CN202110309148 A CN 202110309148A CN 113066771 B CN113066771 B CN 113066771B
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- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 98
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 88
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- 230000017525 heat dissipation Effects 0.000 claims abstract description 43
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 14
- 229910052718 tin Inorganic materials 0.000 claims description 14
- 238000003466 welding Methods 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 11
- 238000009713 electroplating Methods 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 239000000084 colloidal system Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
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- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a multi-layer stacked microsystem structure; the power digital chip is welded on the upper surface of the upper cover silicon wafer, a first heat dissipation metal shell is welded on the upper part of the upper cover silicon wafer, an adapter plate is welded on the lower part of the silicon wafer, a power radio frequency chip is mounted on the lower part of the adapter plate, a PCB (printed circuit board) is mounted on the lower part of the adapter plate, and a second heat dissipation metal shell is fixedly mounted on the lower surface of the PCB; according to the invention, the functional chip is arranged in the middle of the module by utilizing the adapter plate process, then the power digital chip and the power radio frequency chip are arranged on two sides of the functional chip, and the radiating devices are respectively arranged above and below the power digital chip and the power radio frequency chip, so that heat of the power chip can be timely radiated to the terminal, and the temperature rise of the module is avoided.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a multi-layer stacked microsystem structure.
Background
Millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automotive radar, airborne missile tracking systems, space spectrum detection, imaging and the like, and becomes an emerging industry. New applications place new demands on the electrical performance, compact structure and system reliability of the product, and for wireless transmitting and receiving systems, it is not currently possible to integrate them on the same chip (SOC), so that it is necessary to integrate different chips, including radio frequency units, filters, power amplifiers, etc., into a single system to realize the functions of transmitting and receiving signals. However, the radio frequency chip and the large-power consumption digital chip belong to the power chip, the power is higher, a special heat dissipation structure is needed to timely conduct out the heat of the chip, if the power chip in the module structure is in the surrounding of the multi-layer material, the heat dissipation path is blocked, the internal part of the whole module will have too high working temperature, and the service life of the module is influenced, so that different heat dissipation devices are needed to be arranged at the nearest position of the module close to the radio frequency chip, so that the heat of the chip can be timely dissipated out, and the healthy working environment is provided for all the chips of the module, and various problems still exist in various semiconductors on the market.
The manufacturing process of the multilayer stacked radio frequency microsystem cube structure disclosed in the authority publication No. CN110010491A realizes that radio frequency modules are stacked in multiple layers through a bonding process to form a cube structure with a bonding pad structure, the cube can facilitate the erection and installation of the radio frequency modules, can be connected with a water-cooling pipeline access port in a simpler mode and adapt to site requirements, but does not solve the problems that the power of the existing semiconductor chip is higher, a special heat dissipation structure is needed to conduct heat of the chip in time, if a power chip in a module structure is in the surrounding of a multilayer material, the heat dissipation path is blocked, the working temperature inside the whole module is too high, and the service life of the module is influenced.
Disclosure of Invention
The present invention is directed to a multi-layered stacked microsystem structure, which solves the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions: the utility model provides a multilayer stacks microsystem structure, includes the silicon chip, the fixed welding of inlaying in centre of silicon chip has the function chip, the upper portion welding of silicon chip has the upper cover silicon chip, the upper surface paste of upper cover silicon chip is equipped with power digital chip, the upper portion of upper cover silicon chip still welds and installs first heat dissipation metal casing, the lower part welding of silicon chip has the keysets, the lower part paste of keysets has power radio frequency chip, the lower part paste of keysets is connected with the PCB board, be equipped with the copper of inlaying on the PCB board, the fixed paste of lower surface of PCB board is equipped with second heat dissipation metal casing, the silicon chip the upper cover silicon chip with the inside of keysets is all inlayed and is had TSV metal column.
Preferably, the multilayer stacked microsystem structure is prepared as follows:
s1, manufacturing TSV blind holes on the surface of a silicon wafer, depositing a passivation layer, then depositing a seed layer, electroplating TSV metal, and polishing metal on the surface of the silicon wafer to obtain the silicon wafer with the TSV metal column;
s2, manufacturing RDL and a bonding pad on the end face of the TSV metal column, thinning the back face of the silicon wafer to expose the bottom of the TSV metal column, depositing a passivation layer, and polishing to expose the end of the TSV metal column;
s3, etching a cavity on the surface of the silicon wafer, embedding the functional chip into the cavity in a welding or gluing mode, filling colloid in a gap between the functional chip and the cavity, and manufacturing RDL on the surface of the silicon wafer to interconnect the TSV metal column and the bonding pad of the functional chip;
s4, repeating S1-S3 to manufacture the upper cover silicon wafer with the TSV metal column, bonding the silicon wafer and the upper cover silicon wafer into a first module by using a wafer bonding process, setting solder balls on the back surface of the first module, and finally attaching the power digital chip on the front surface of the module;
s5, repeating the steps S1-S3 to manufacture the adapter plate with the TSV metal column, arranging copper core tin balls on the surface of the adapter plate, and then attaching the power radio frequency chip on the surface of the copper core tin balls to obtain a second module;
s6, welding the first module and the second module together through a chip bonding process to obtain a third module, arranging the first heat dissipation metal shell on the top of the third module, and connecting the power digital chip and the first heat dissipation metal shell through heat conduction silicone grease to form a fourth module;
and S7, attaching the fourth module to the PCB embedded with the copper insert through a surface mounting process, and attaching the second heat dissipation metal shell to the back surface of the PCB to obtain a final multilayer stacking structure.
Preferably, the bonding pads are welded on the end faces of the TSV metal columns, and the bonding pads are soldering tin plates.
Preferably, the TSV blind hole in S1 is a TSV hole formed on the surface of the silicon wafer by photolithography or etching, and the TSV hole has a hole diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000um.
Preferably, the processing procedure of the silicon wafer in S1 is as follows: and depositing a silicon oxide or silicon nitride insulating layer above the silicon wafer, or directly performing thermal oxidation, and manufacturing a deposition seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation process.
Preferably, the thickness of the insulating layer is in the range of 10nm-100um, the thickness of the deposition seed layer is in the range of 1nm-100um, at least one layer of the deposition seed layer is arranged, and the metal material selected for the deposition seed layer is one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Preferably, the temperature of the TSV blind holes in the S1 is 200-500 ℃ when electroplating filling is carried out, and copper on the surface of the silicon wafer is removed by a CMP process, so that only copper filling is left on the surface of the silicon wafer.
Preferably, in the step S2, an RDL and the bonding pad are fabricated at the open end of the TSV through a photolithography and electroplating process, the back surface of the silicon wafer is thinned by using a carrier as a support, the thickness of the thinned silicon wafer is 100nm-700um, the thinning is directly performed on the back surface of the silicon wafer to expose the back surface of the TSV, the passivation layer is covered on the back surface of the TSV, and then CMP is performed to expose the metal of the TSV.
Preferably, in the step S3, a recess is etched on the back surface of the silicon wafer by using a photolithography or dry etching process, and the width of the recess is 1um-1000um, and the depth is 10um-1000um.
Preferably, the first module, the second module and the third module are fixedly connected through a wafer bonding process, the first heat dissipation metal shell and the second heat dissipation metal shell are all copper-aluminum heat dissipation metal shells, and heat dissipation fins are arranged on the first heat dissipation metal shell and the second heat dissipation metal shell.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the functional chip is arranged in the middle of the module by utilizing the adapter plate process, then the power digital chip and the power radio frequency chip are arranged on two sides of the functional chip, and the radiating devices are respectively arranged above and below the power digital chip and the power radio frequency chip, so that heat of the power chip can be timely radiated to the terminal, and the temperature rise of the module is avoided.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of a structure of a silicon wafer provided with TSV blind holes;
FIG. 3 is a schematic diagram of a silicon-on-wafer damascene TSV metal pillar of the present invention;
FIG. 4 is a schematic diagram of a silicon die damascene functional chip of the present invention;
fig. 5 is a schematic structural diagram of an adapter plate provided with a TSV blind hole according to the present invention;
fig. 6 is a schematic structural diagram of an interposer damascene TSV metal pillar and copper core solder ball of the present invention.
In the figure: 1. a silicon wafer; 2. a silicon wafer is covered; 3. a power digital chip; 4. a first heat dissipating metal housing; 5. an adapter plate; 6. a PCB board; 7. copper is inlaid; 8. a second heat dissipating metal housing; 9. TSV metal pillars; 10. solder balls; 11. copper core tin balls; 12. TSV blind holes; 13. a bonding pad; 14. a functional chip; 15. a colloid; 16. a power radio frequency chip.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-6, the present invention provides a technical solution: the utility model provides a multilayer stacks microsystem structure, includes silicon chip 1, the fixed welding of inlaying in the centre of silicon chip 1 has functional chip 14, the upper portion welding of silicon chip 1 has upper cover silicon chip 2, the upper surface subsides of upper cover silicon chip 2 installs power digital chip 3, the upper portion of upper cover silicon chip 2 still welds and installs first heat dissipation metal casing 4, the lower part welding of silicon chip 1 has keysets 5, the lower part subsides of keysets 5 is equipped with power radio frequency chip 16, the lower part subsides of keysets 5 is connected with PCB board 6, be equipped with copper insert 7 on the PCB board 6, the fixed subsides of lower surface of PCB board 6 is equipped with second heat dissipation metal casing 8, silicon chip 1 the upper cover silicon chip 2 with the inside of keysets 5 has all been inlayed TSV metal column 9.
In order to implement the preparation of the multi-layer stacked microsystem structure, in this embodiment, preferably, the preparation steps of the multi-layer stacked microsystem structure are as follows:
s1, manufacturing TSV blind holes 12 on the surface of a silicon wafer 1, depositing a passivation layer, then depositing a seed layer, electroplating TSV metal, and polishing metal on the surface of the silicon wafer to obtain the silicon wafer 1 with the TSV metal columns 9;
s2, manufacturing RDL and a bonding pad 13 on the end face of the TSV metal column 9, thinning the back face of the silicon wafer 1 to expose the bottom of the TSV metal column 9, depositing a passivation layer, and polishing to expose the end of the TSV metal column 9;
s3, etching a cavity on the surface of the silicon wafer 1, embedding the functional chip 14 into the cavity in a welding or gluing mode, filling a colloid 15 in a gap between the functional chip 14 and the cavity, and manufacturing an RDL on the surface of the silicon wafer 1 to interconnect the TSV metal column 9 and the bonding pad 13 of the functional chip 14;
s4, repeating S1-S3 to manufacture the upper cover silicon wafer 2 with the TSV metal columns 9, bonding the silicon wafer 1 and the upper cover silicon wafer 2 into a first module by using a wafer bonding process, arranging solder balls 10 on the back of the first module, and finally attaching the power digital chip 3 on the front of the module;
s5, repeating S1-S3 to manufacture the adapter plate 5 with the TSV metal columns 9, arranging copper core tin balls 11 on the surface of the adapter plate 5, and then attaching the power radio frequency chip 16 on the surface of the copper core tin balls 11 to obtain a second module;
s6, welding the first module and the second module together through a chip bonding process to obtain a third module, arranging the first heat dissipation metal shell 4 at the top of the third module, and connecting the power digital chip 3 and the first heat dissipation metal shell 4 through heat conduction silicone grease to form a fourth module;
and S7, attaching a fourth module to the PCB 6 embedded with the copper insert 7 through a surface mounting process, and attaching the second heat dissipation metal shell 8 to the back surface of the PCB 6 to obtain a final multilayer stacking structure.
In order to realize the electrical connection and transmission of the multi-layer stacked microsystem, in this embodiment, preferably, the end surfaces of the TSV metal columns 9 are all soldered with the bonding pads 13, and the bonding pads 13 are solder pads.
In order to realize the preparation of the TSV metal column 9 on the silicon wafer 1, in this embodiment, preferably, the TSV blind hole 12 in S1 is a TSV hole formed on the surface of the silicon wafer 1 by photolithography or etching, and the diameter of the TSV hole ranges from 1um to 1000um, and the depth ranges from 10um to 1000um.
In order to implement technical processing on the silicon wafer 1, in this embodiment, preferably, the processing procedure of the silicon wafer 1 in S1 is as follows: and depositing a silicon oxide or silicon nitride insulating layer above the silicon wafer 1, or directly performing thermal oxidation, and manufacturing a deposition seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation process.
In order to keep the thickness of the multi-layer stacked microsystem suitable, in this embodiment, preferably, the thickness of the insulating layer is in a range of 10nm-100um, the thickness of the deposition seed layer is in a range of 1nm-100um, at least one layer of the deposition seed layer is provided, and the metal material selected from titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel is used as the deposition seed layer.
In order to make the texture of the TSV metal column 9 precisely uniform, in this embodiment, it is preferable that the temperature of the TSV blind hole 12 in S1 is 200-500 degrees when the electroplating filling is performed, and the CMP process removes copper from the surface of the silicon wafer 1, so that only copper filling remains on the surface of the silicon wafer 1.
In order to realize the processing of the silicon wafer 1, so that the TSV metal post 9 can leak out and is convenient for electrical connection, in this embodiment, preferably, in the step S2, RDL and the bonding pad 13 are fabricated at the TSV opening end through a photolithography and electroplating process, the back surface of the silicon wafer is thinned by using a carrier as a support, the thinning thickness is 100nm-700um, the thinning process is directly performed on the back surface of the silicon wafer 1, the TSV back surface is exposed, the passivation layer is covered on the back surface, and then CMP exposes the TSV metal.
In order to implement the damascene mounting of the functional chip 14, in this embodiment, preferably, a recess is etched on the back surface of the silicon wafer 1 in the step S3 by using a photolithography or dry etching process, where the width of the recess is 1um-1000um and the depth is 10um-1000um.
In order to realize multi-layer stacking and perform rapid heat dissipation, in this embodiment, preferably, the first module, the second module, and the third module are fixedly connected through a wafer bonding process, the first heat dissipation metal housing 4 and the second heat dissipation metal housing 8 are all copper-aluminum heat dissipation metal housings, and heat dissipation fins are disposed on the first heat dissipation metal housing 4 and the second heat dissipation metal housing 8.
The working principle and the using flow of the invention are as follows:
firstly, manufacturing TSV blind holes 12 on the surface of a silicon wafer 1, depositing a passivation layer, then depositing a seed layer, electroplating TSV metal, and polishing metal on the surface of the silicon wafer to obtain the silicon wafer 1 with the TSV metal columns 9;
secondly, manufacturing RDL and a bonding pad 13 on the end face of the TSV metal column 9, thinning the back face of the silicon wafer 1 to expose the bottom of the TSV metal column 9, depositing a passivation layer, and polishing to expose the end of the TSV metal column 9;
thirdly, etching a cavity on the surface of the silicon wafer 1, embedding the functional chip 14 into the cavity in a welding or gluing mode, filling a colloid 15 in a gap between the functional chip 14 and the cavity, and then manufacturing an RDL on the surface of the silicon wafer 1 to interconnect the TSV metal column 9 and the bonding pad 13 of the functional chip 14;
fourth, S1-S3 are repeated to manufacture the upper cover silicon wafer 2 with the TSV metal columns 9, the silicon wafer 1 and the upper cover silicon wafer 2 are bonded into a first module by a wafer bonding process, solder balls 10 are arranged on the back of the first module, and finally the power digital chip 3 is attached to the front of the module;
fifthly, repeating S1-S3 to manufacture the adapter plate 5 with the TSV metal columns 9, arranging copper core tin balls 11 on the surface of the adapter plate 5, and then attaching the power radio frequency chip 16 on the surface of the copper core tin balls 11 to obtain a second module;
a sixth step of welding the first module and the second module together through a chip bonding process to obtain a third module, wherein the first heat dissipation metal shell 4 is arranged at the top of the third module, and the power digital chip 3 and the first metal shell 4 are connected through heat conduction silicone grease to form a fourth module;
and a seventh step of attaching the fourth module to the PCB 6 embedded with the copper insert 7 through a surface mounting process, and attaching the second heat dissipation metal shell 8 to the back surface of the PCB 6 to obtain a final multilayer stacking structure.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (10)
1. A multi-layer stacked microsystem structure comprising a silicon wafer (1), characterized in that: the novel high-power semiconductor device is characterized in that a functional chip (14) is fixedly embedded and welded in the middle of the silicon chip (1), an upper cover silicon chip (2) is welded on the upper portion of the silicon chip (1), a power digital chip (3) is attached to the upper surface of the upper cover silicon chip (2), a first heat dissipation metal shell (4) is further welded and installed on the upper portion of the upper cover silicon chip (2), an adapter plate (5) is welded on the lower portion of the silicon chip (1), a power radio frequency chip (16) is attached to the lower portion of the adapter plate (5), a PCB (6) is attached to the lower portion of the adapter plate (5), a copper-embedded (7) is arranged on the PCB (6), a second heat dissipation metal shell (8) is fixedly attached to the lower surface of the PCB (6), and metal columns (9) are embedded in the silicon chip (1), the upper cover silicon chip (2) and the TSV (5).
2. A process for preparing a multi-layered stacked microsystem structure according to claim 1, comprising the steps of:
s1, manufacturing TSV blind holes (12) on the surface of a silicon wafer (1), depositing a passivation layer, then depositing a seed layer, electroplating TSV metal, and polishing metal on the surface of the silicon wafer to obtain the silicon wafer (1) with the TSV metal columns (9);
s2, manufacturing RDL and a bonding pad (13) on the end face of the TSV metal column (9), thinning the back face of the silicon wafer (1) to expose the bottom of the TSV metal column (9), depositing a passivation layer, and polishing to expose the end of the TSV metal column (9);
s3, etching a cavity on the surface of the silicon wafer (1), embedding the functional chip (14) into the cavity in a welding or gluing mode, filling a colloid (15) in a gap between the functional chip (14) and the cavity, and manufacturing an RDL on the surface of the silicon wafer (1) to enable the TSV metal column (9) and the bonding pad (13) of the functional chip (14) to be connected;
s4, repeating S1-S2 to manufacture the upper cover silicon wafer (2) with the TSV metal columns (9), bonding the silicon wafer (1) and the upper cover silicon wafer (2) into a first module by using a wafer bonding process, arranging solder balls (10) on the back of the first module, and finally attaching the power digital chip (3) on the front of the module;
s5, repeating the steps S1-S2 to manufacture the adapter plate (5) with the TSV metal columns (9), arranging copper core tin balls (11) on the surface of the adapter plate (5), and then attaching the power radio frequency chip (16) on the surface of the copper core tin balls (11) to obtain a second module;
s6, welding the first module and the second module together through a chip bonding process to obtain a third module, arranging the first heat dissipation metal shell (4) at the top of the third module, and connecting the power digital chip (3) and the first heat dissipation metal shell (4) through heat conduction silicone grease to form a fourth module;
and S7, attaching the fourth module to the PCB (6) embedded with the copper insert (7) through a surface mounting process, and attaching the second heat dissipation metal shell (8) to the back surface of the PCB (6) to obtain a final multilayer stacking structure.
3. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: the bonding pads (13) are welded on the end faces of the TSV metal columns (9), and the bonding pads (13) are soldering tin plates.
4. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: TSV blind holes (12) in the S1 are formed in the surface of the silicon wafer (1) through photoetching or etching technology, the diameter of the TSV holes ranges from 1um to 1000um, and the depth of the TSV holes ranges from 10um to 1000um.
5. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: the processing process of the silicon wafer (1) in the step S1 is as follows: and depositing a silicon oxide or silicon nitride insulating layer above the silicon wafer (1), or directly performing thermal oxidation, and manufacturing a deposition seed layer above the insulating layer through physical sputtering, magnetron sputtering or evaporation process.
6. The process for preparing a multi-layered stacked microsystem structure of claim 5, wherein: the thickness of the insulating layer is in the range of 10nm-100um, the thickness of the deposition seed layer is in the range of 1nm-100um, at least one layer of deposition seed layer is arranged, and the deposition seed layer is made of one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
7. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: the temperature of the TSV blind holes (12) in the S1 is 200-500 ℃ when electroplating filling is carried out, copper on the surface of the silicon wafer (1) is removed through a CMP process, and only copper filling is left on the surface of the silicon wafer (1).
8. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: and in the step S2, RDL and the bonding pad (13) are manufactured at the opening end of the TSV through a photoetching electroplating process, the back surface of the silicon wafer is thinned by taking a slide glass as a support, the thinning thickness is 100nm-700 mu m, thinning is directly performed on the back surface of the silicon wafer (1) to expose the back surface of the TSV, the passivation layer is covered on the back surface of the TSV, and then the TSV metal is exposed through CMP.
9. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: and in the step S3, a groove is etched on the back surface of the silicon wafer (1) by using a photoetching or dry etching process, wherein the width of the groove is 1um-1000um, and the depth is 10um-1000um.
10. The process for preparing a multi-layered stacked microsystem structure of claim 2, wherein: the first module, the second module and the third module are fixedly connected through a wafer bonding process, the first heat dissipation metal shell (4) and the second heat dissipation metal shell (8) are copper-aluminum heat dissipation metal shells, and heat dissipation fins are arranged on the first heat dissipation metal shell (4) and the second heat dissipation metal shell (8).
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1893053A (en) * | 2005-07-08 | 2007-01-10 | 三星电子株式会社 | Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure |
| CN105428331A (en) * | 2015-12-22 | 2016-03-23 | 成都锐华光电技术有限责任公司 | Carrier-based fan-out 2.5D/3D package structure |
| CN107768349A (en) * | 2017-09-25 | 2018-03-06 | 江苏长电科技股份有限公司 | Two-sided SiP three-dimension packagings structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7928563B2 (en) * | 2008-05-28 | 2011-04-19 | Georgia Tech Research Corporation | 3-D ICs with microfluidic interconnects and methods of constructing same |
| US8604603B2 (en) * | 2009-02-20 | 2013-12-10 | The Hong Kong University Of Science And Technology | Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers |
| US8957525B2 (en) * | 2012-12-06 | 2015-02-17 | Texas Instruments Incorporated | 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor |
| US8933540B2 (en) * | 2013-02-28 | 2015-01-13 | International Business Machines Corporation | Thermal via for 3D integrated circuits structures |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1893053A (en) * | 2005-07-08 | 2007-01-10 | 三星电子株式会社 | Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure |
| CN105428331A (en) * | 2015-12-22 | 2016-03-23 | 成都锐华光电技术有限责任公司 | Carrier-based fan-out 2.5D/3D package structure |
| CN107768349A (en) * | 2017-09-25 | 2018-03-06 | 江苏长电科技股份有限公司 | Two-sided SiP three-dimension packagings structure |
Non-Patent Citations (1)
| Title |
|---|
| 微系统集成用倒装芯片工艺技术的发展及趋势;赵雪薇;阎璐;邢朝洋;李男男;朱政强;;导航与控制(第05期);19-29 * |
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