CN114759015B - Three-dimensional stacking integrated structure of high-power radio frequency chip and preparation method thereof - Google Patents
Three-dimensional stacking integrated structure of high-power radio frequency chip and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a three-dimensional stacked integrated structure of a high-power radio frequency chip and a preparation method thereof, wherein the three-dimensional stacked integrated structure comprises a multi-layer circuit substrate, the high-power radio frequency chip and a low-K value adapter plate which are sequentially arranged from bottom to top, the low-K value adapter plate is inversely arranged on the upper surface of the high-power radio frequency chip, a plurality of independent electromagnetic isolation structures are formed on the high-power radio frequency chip, other chips or elements are arranged on the low-K value adapter plate, the other chips or elements are interconnected with the low-K value adapter plate, and the low-K value adapter plate is electrically connected with the high-power radio frequency chip. The three-dimensional stacking structure is compatible with the traditional hybrid integration process, and a mainstream heat sink heat dissipation technology can be used, so that a silicon-based through hole heat dissipation or micro-channel heat dissipation structure is avoided, the reliability is improved, the processing period is shortened, and the processing cost is reduced.
Description
Technical Field
The invention relates to the technical field of radio frequency chips, in particular to a three-dimensional stacking integrated structure of a high-power radio frequency chip and a preparation method thereof.
Background
From the aspect of the high-density integrated product form of the existing high-power radio frequency chip, the multi-chip module (MCM) technology is mainly adopted, the high-power radio frequency chip (such as GaAs chip and GaN chip) and the microminiature chip type element are assembled on an LTCC or multi-layer PCB substrate, and the cascade connection of the element and the multi-functional substrate is realized by adopting the modes of gold wire bonding and the like. In general, high-power radio frequency chip integration generally requires an air cavity structure with a height of several millimeters above the chip to flatly mount all chips and peripheral matching circuits on a two-dimensional direction of a substrate, so that the performance of the radio frequency chip can meet the requirement, but a large amount of circuit effective area is occupied. The method has the defects that the product volume is large, the requirement of multi-channel high-density integration of the radio frequency unit is not met, and the integration density of channels is required to be improved in a three-dimensional stacking mode of chips so as to improve the functional density of the channels.
Currently, in the patent related to stacking high-power radio frequency chips (such as patent CN108766897B, CN108083223 a), a multi-stack multi-cavity package structure is mostly adopted, and the package adopts silicon material as both a package cavity and a sidewall routing layer to realize vertical interconnection. However, the main problems of the integration mode are that the product volume is larger, the stacking and integration structure is complex, the vertical interconnection path is long, the difficulty in manufacturing the vertical through holes on the side wall of the tube shell is large, the product reliability is low, the performance is poor, the cost is high, the processing period is long, and the engineering popularization and application are difficult.
The three-dimensional stacking structure of the high-power radio frequency chip is an effective way for further improving the integration density. However, the three-dimensional stacking structure in the high-power radio frequency field has few reports at present, and mainly has the following technical difficulties: (a) The design difficulty of electromagnetic compatibility is high, the surface air cavity of the microwave circuit by flip-chip bonding is limited in height, and the high-power radio frequency chip is easy to cause self-excitation or crosstalk. (b) When the high-power chip is designed in multiple stages and multiple channels, the stacking structure is easy to cause electromagnetic interference, and electromagnetic isolation is required to be enhanced between the front-stage transistor and the final-stage transistor of the high-power radio-frequency chip and between the multiple channels. (c) The peripheral circuit of the high-power radio frequency chip is complex, and circuits such as a driving circuit, a power supply and a detection circuit are often needed, so that the high-density integration difficulty is high, and the high-density integration requirement and the electromagnetic compatibility requirement are difficult to meet. (d) Vertical interconnection is realized through the wiring layer on the side wall of the packaging cavity, the integrated structure is complex, the process difficulty is high, and the engineering practicability is poor. (f) The heat flux density of the three-dimensional stacked integrated high-power GaN chip can reach more than 100W/cm < 2 >, which is far beyond the heat dissipation capacity of the silicon substrate, and a through hole heat dissipation or micro-channel heat dissipation structure is required to be manufactured on the silicon substrate, so that the reliability of the substrate is poor, the processing period is long, and the processing cost is high.
Disclosure of Invention
Aiming at the defects in the prior art, the high-power radio frequency chip three-dimensional stacking integrated structure and the preparation method thereof provided by the invention solve the problems that the volume of the current high-power radio frequency chip integrated product is large, the three-dimensional stacking integrated structure is complex, the design difficulty of electromagnetic compatibility is large, high-density integration is difficult to carry out, and heat dissipation is difficult.
In order to achieve the aim of the invention, the invention adopts the following technical scheme: the utility model provides a three-dimensional integrated structure that stacks of high-power radio frequency chip, includes from bottom to top multilayer circuit substrate, high-power radio frequency chip, low K value keysets that sets gradually, low K value keysets is adorned in high-power radio frequency chip's upper surface upside down, forms a plurality of independent electromagnetic isolation structures on high-power radio frequency chip, be equipped with other chips or components on the low K value keysets, other chips or components and low K value keysets interconnect, low K value keysets realizes electrical connection with high-power radio frequency chip.
Further: the high-power radio frequency chip upper surface is equipped with preceding stage transistor and last stage transistor from left to right, high-power radio frequency chip lower surface is equipped with chip lower surface metallization ground plane, high-power radio frequency chip runs through and is equipped with chip radio frequency signal transmission hole and chip ground hole, chip radio frequency signal transmission hole upper and lower surface is equipped with perpendicular signal hole pad, chip ground hole upper and lower surface is equipped with little bump shielding ball pad, high-power radio frequency chip from top to bottom includes two-way radio frequency channel, set up little bump shielding ball between the transistor between preceding stage transistor and the last stage transistor, two-way set up little bump shielding ball pad between the multichannel between the radio frequency channel.
Further: the high-power radio frequency chip is a leadless interconnection chip, the upward radio frequency input/output port is of a vertical signal transmission micro-bump flip-chip structure, and the downward input/output port is of a radio frequency transmission through hole structure.
Further: the high-K-value adapter plate is characterized in that a large-area metallized grounding layer is arranged on the upper surface of the low-K-value adapter plate, an adapter plate micro-bump bonding pad is arranged in a region, corresponding to the micro-bump shielding ball bonding pad, of the lower surface of the low-K-value adapter plate, the large-area metallized grounding layer is connected with the adapter plate micro-bump bonding pad through an adapter plate grounding hole, and the adapter plate micro-bump bonding pad is connected with the micro-bump shielding ball bonding pad through a micro-bump shielding ball.
Further: the upper surface of the low-K value adapter plate and the input/output port structure of other chips or elements are of a radio frequency channel structure, and the downward signal input/output port structure is of a transmission through hole structure.
Further: the electromagnetic isolation structure comprises a plurality of independent air cavities which are formed by micro-bump shielding balls, a chip lower surface metallized grounding layer, chip grounding holes, micro-bump shielding ball bonding pads, a large-area metallized grounding layer, an adapter plate grounding hole and an adapter plate micro-bump bonding pad.
Further: the other chips or elements are positioned on the large-area metallized grounding layer, the other chips or elements are interconnected with the signal pad of the adapter plate through leads, and the signal pad of the adapter plate is interconnected with the high-power radio frequency chip through the vertical signal transmission micro-convex points.
A preparation method of a three-dimensional stacked integrated structure of a high-power radio frequency chip comprises the following steps:
step 1: providing a low-K value adapter plate;
step 2: manufacturing a through hole on the low-K value adapter plate;
step 3: preparing an adhesion layer on the surface of the low-K value adapter plate;
step 4: performing high-precision metal electroplating filling on the through holes;
step 5: plating gold or nickel palladium gold on the surface of the adhesion layer by using an electroplating process to form a metallization layer;
step 6: assembling the bare chip on the metallized low-K value adapter plate by adopting a micro-assembly eutectic process;
step 7: ball implantation is carried out on the lower surface of the low-K value adapter plate, and a laser ball implantation process is adopted to manufacture gold balls or tin balls;
step 8: mounting a high-power radio frequency chip on a multilayer circuit substrate;
step 9: bonding the low-K value adapter plate to a high-power radio frequency chip;
step 10: other chips or components are attached to the upper surface of the low-K interposer/multilayer circuit substrate to meet interconnect requirements.
Further: the adhesion layer material is Ti/TiN/TiW.
Further: the low-K adapter plate is a glass substrate, the K value range is 5-6, and the thickness is larger than or equal to 200 mu m.
The beneficial effects of the invention are as follows:
(1) The invention adopts the low-K value adapter plate and the micro-bump shielding ball to realize that the height of the air cavity of the high-power chip is reduced from thousands of micrometers to tens of micrometers, thereby greatly reducing the thickness of the assembly, improving the electromagnetic compatibility and avoiding the self-excitation and crosstalk of the power chip. Meanwhile, the vertical interconnection of radio frequency signals is realized, instead of the vertical interconnection through the wiring layer on the side wall of the packaging cavity, the integration level is improved, the integration complexity and the process difficulty are reduced, and the method has strong innovation and engineering practicability.
(2) According to the invention, the high-power radio frequency chip and the peripheral circuit thereof are three-dimensionally stacked and integrated, the channel area occupied by the peripheral circuit is reduced, and the integration density of the channels is improved, so that the space between the radio frequency multiple channels is reduced, and the requirements of the improvement, the modularity, the universalization and the expansibility of the working frequency of the radio frequency unit are met.
(3) The three-dimensional stacking structure is compatible with the traditional hybrid integration process, and a mainstream heat sink heat dissipation technology can be used, so that a silicon-based through hole heat dissipation or micro-channel heat dissipation structure is avoided, the reliability is improved, the processing period is shortened, and the processing cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a three-dimensional stacked integrated structure of a high-power radio frequency chip;
FIG. 2 is a schematic diagram of the top surface of a high power RF chip;
FIG. 3 is a schematic top surface view of a low K adapter plate;
FIG. 4 is a schematic view of the lower surface of the low K adapter plate;
fig. 5 is a schematic diagram of a process of fabricating a three-dimensional stacked integrated structure of high-power rf chips.
Wherein: 1. a multilayer circuit substrate; 2. a high-power radio frequency chip; 3. a low K value interposer; 4. other chips or components; 5. a chip grounding hole; 6. an adapter plate grounding hole; 7. a micro-bump shielding ball; 8. a chip radio frequency signal transmission hole; 9. an interposer signal pad; 10. a large area metallized ground layer; 11. a micro-bump shielding ball bonding pad; 12. the patch panel is a micro bump pad; 13. a metallized grounding layer on the lower surface of the chip; 14. a pre-stage transistor; 15. a final stage transistor; 16. a lead wire; 17. an electromagnetic isolation structure; 18. vertical signal transmission micro-bumps; 19. micro-bump shielding balls among transistors; 20. a micro-bump shielding ball bonding pad between multiple channels; 21. vertical signal hole pads.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1, the three-dimensional stacked integrated structure of a high-power radio frequency chip comprises a multi-layer circuit substrate 1, a high-power radio frequency chip 2 and a low-K value adapter plate 3 which are sequentially arranged from bottom to top, wherein the low-K value adapter plate 3 is inversely arranged on the upper surface of the high-power radio frequency chip 2, a plurality of independent electromagnetic isolation structures 17 are formed on the high-power radio frequency chip 2, other chips or elements 4 are arranged on the low-K value adapter plate 3, the other chips or elements 4 are interconnected with the low-K value adapter plate 3, and the low-K value adapter plate 3 is electrically connected with the high-power radio frequency chip 2.
According to the invention, as shown in fig. 1, the adapter plate is inversely arranged on the upper surface of the high-power radio frequency, and a plurality of independent air cavity electromagnetic isolation structures are formed above the high-power radio frequency chip ingeniously. And other radio frequency or digital chips and other elements can be continuously and positively arranged above the low-K value adapter plate, so that the integration density is greatly improved.
As shown in fig. 2, the high-power rf chip 2 is a compound semiconductor chip, the upper surface of the high-power rf chip 2 is provided with a front transistor 14 and a final transistor 15 from left to right, the lower surface of the high-power rf chip 2 is provided with a chip lower surface metallization ground layer 13, the high-power rf chip 2 is provided with a chip rf signal transmission hole 8 and a chip ground hole 5 in a penetrating manner, the upper and lower surfaces of the chip rf signal transmission hole 8 are provided with vertical signal hole pads 21, the upper and lower surfaces of the chip ground hole 5 are provided with micro-bump shielding ball pads 11, the high-power rf chip 2 comprises two paths of rf channels from top to bottom, an inter-transistor micro-bump shielding ball 19 is arranged between the front transistor 14 and the final transistor 15, and a multi-channel micro-bump shielding ball pad 20 is arranged between the two paths of rf channels.
As shown in fig. 3 and fig. 4, the upper surface of the low-K value interposer 3 is provided with a large-area metallized ground layer 10, the area of the lower surface of the low-K value interposer 3 corresponding to the micro-bump shielding ball pad 11 is provided with an interposer micro-bump pad 12, the large-area metallized ground layer 10 is connected with the interposer micro-bump pad 12 through the interposer ground hole 6, and the interposer micro-bump pad 12 is connected with the micro-bump shielding ball pad 11 through the micro-bump shielding ball 7.
The electromagnetic isolation structure 17 comprises a plurality of independent air cavities formed by the micro-bump shielding balls 7, the chip lower surface metallization grounding layer 13, the chip grounding holes 5, the micro-bump shielding ball bonding pads 11, the large-area metallization grounding layer 10, the adapter plate grounding holes 6 and the adapter plate micro-bump bonding pads 12. Each unit circuit air cavity is surrounded by a shielding ball, and comprises a shielding ball between a front-stage transistor and a final-stage transistor of a high-power radio frequency chip, a shielding ball between multiple channels of the high-power radio frequency chip and a shielding ball of an outer ring of the high-power chip.
The upper surface of the low-K value adapter plate and the input/output port structure of other chips are of a radio frequency channel structure, and the downward signal input/output port structure is of a transmission through hole structure.
The high-power radio frequency chip 2 is a leadless interconnection chip, the upward radio frequency input/output port structure is a vertical signal transmission micro-bump flip-chip structure, and the downward input/output port structure is a radio frequency transmission through hole structure.
The spacing of the micro-bump shielding balls can be designed in a single row or double rows at intervals. The diameter of the micro-bump shielding ball structure is 60-120 mu m, and the solder balls are gold balls.
The other chips or components 4 include other radio frequency chips or other digital chips, capacitive chip components, resistive chip components, etc.
The multilayer circuit substrate 1 is a high-heat-dissipation ceramic substrate or a copper core embedded high-frequency printed board.
A three-dimensional stacked integrated structure of a high-power radio frequency chip and a preparation method thereof are provided, and the implementation process comprises the following steps as shown in fig. 5:
step (1): a low K value interposer is provided. And manufacturing a through hole on the low-K value adapter plate. And precisely exposing the adapter plate by adopting deep ultraviolet light with special wavelength (250-300 nm), so as to realize modification of the micropore pattern of the adapter plate. Then, a high-temperature heat treatment is required to effect ion aggregation and recrystallization of the exposed portion. And the modified glass is subjected to microporous corrosion by adopting a high-precision HF corrosion process.
Step (2): and (3) after cleaning the surface of the low-K adapter plate, preparing the TiW adhesive layer by using a magnetron sputtering method. And carrying out high-precision metal electroplating filling Cu on the through holes by adopting a reverse pulse power supply, jet stirring, plating solution circulating filtration and other methods.
Step (3): and plating gold on the surface of the adhesion layer by using an electroplating process to form a metallized gold layer.
Step (4): the bare chip is mounted to the metallized interposer using a micro-assembly eutectic process.
Step (5): and (3) planting gold balls on the lower surface of the adapter plate by adopting a laser ball planting process.
Step (6): and mounting the high-power radio frequency chip on the LTCC substrate by adopting a micro-assembly eutectic process.
Step (7): and bonding the adapter plate to the high-power radio frequency chip by adopting an ultrasonic hot-pressing flip-chip bonding capability process.
Claims (7)
1. The three-dimensional stacked integrated structure of the high-power radio frequency chip is characterized by comprising a multi-layer circuit substrate (1), a high-power radio frequency chip (2) and a low-K value adapter plate (3) which are sequentially arranged from bottom to top, wherein the low-K value adapter plate (3) is inversely arranged on the upper surface of the high-power radio frequency chip (2), a plurality of independent electromagnetic isolation structures (17) are formed on the high-power radio frequency chip (2), other chips or elements (4) are arranged on the low-K value adapter plate (3), the other chips or elements (4) are interconnected with the low-K value adapter plate (3), and the low-K value adapter plate (3) is electrically connected with the high-power radio frequency chip (2);
the high-power radio frequency chip (2) is provided with a front-stage transistor (14) and a final-stage transistor (15) from left to right, the lower surface of the high-power radio frequency chip (2) is provided with a chip lower surface metallization grounding layer (13), the high-power radio frequency chip (2) is provided with a chip radio frequency signal transmission hole (8) and a chip grounding hole (5) in a penetrating manner, the upper surface and the lower surface of the chip radio frequency signal transmission hole (8) are provided with vertical signal hole bonding pads (21), the upper surface and the lower surface of the chip grounding hole (5) are provided with micro-bump shielding ball bonding pads (11), the high-power radio frequency chip (2) comprises two paths of radio frequency channels from top to bottom, a transistor micro-bump shielding ball (19) is arranged between the front-stage transistor (14) and the final-stage transistor (15), and a multi-channel micro-bump shielding ball bonding pad (20) is arranged between the two paths of radio frequency channels;
the high-K-value adapter plate (3) is characterized in that a large-area metallized grounding layer (10) is arranged on the upper surface of the low-K-value adapter plate (3), an adapter plate micro-bump pad (12) is arranged in a region, corresponding to the micro-bump shielding ball pad (11), of the lower surface of the low-K-value adapter plate (3), the large-area metallized grounding layer (10) is connected with the adapter plate micro-bump pad (12) through an adapter plate grounding hole (6), and the adapter plate micro-bump pad (12) is connected with the micro-bump shielding ball pad (11) through a micro-bump shielding ball (7);
the electromagnetic isolation structure (17) comprises a plurality of independent air chambers which are formed by micro-bump shielding balls (7), a chip lower surface metallization grounding layer (13), chip grounding holes (5), micro-bump shielding ball bonding pads (11), a large-area metallization grounding layer (10), adapter plate grounding holes (6) and adapter plate micro-bump bonding pads (12).
2. The three-dimensional stacked integrated structure of high-power rf chips according to claim 1, wherein the high-power rf chip (2) is a leadless interconnection chip, an upward rf input/output port is a vertical signal transmission micro bump flip-chip structure, and a downward rf input/output port structure is a rf transmission via structure.
3. The three-dimensional stacked integrated structure of high-power rf chips according to claim 1, wherein the input/output port structure of the upper surface of the low-K adapter plate (3) and other chips or elements (4) is a radio frequency channel structure, and the downward signal input/output port structure is a transmission through hole structure.
4. The three-dimensional stacked integrated structure of high-power radio frequency chips according to claim 1, characterized in that the other chips or elements (4) are located on a large-area metallized ground layer (10), the other chips or elements (4) are interconnected with a interposer signal pad (9) by leads (16), and the interposer signal pad (9) is signal-interconnected with the high-power radio frequency chip (2) by vertical signal transmission micro bumps (18).
5. The method for manufacturing the three-dimensional stacked integrated structure of the high-power radio frequency chip according to any one of claims 1 to 4, comprising the steps of:
step 1: providing a low-K value adapter plate;
step 2: manufacturing a through hole on the low-K value adapter plate;
step 3: preparing an adhesion layer on the surface of the low-K value adapter plate;
step 4: performing high-precision metal electroplating filling on the through holes;
step 5: plating gold or nickel palladium gold on the surface of the adhesion layer by using an electroplating process to form a metallization layer;
step 6: assembling the bare chip on the metallized low-K value adapter plate by adopting a micro-assembly eutectic process;
step 7: ball implantation is carried out on the lower surface of the low-K value adapter plate, and a laser ball implantation process is adopted to manufacture gold balls or tin balls;
step 8: mounting a high-power radio frequency chip on a multilayer circuit substrate;
step 9: bonding the low-K value adapter plate to a high-power radio frequency chip;
step 10: other chips or components are attached to the upper surface of the low-K interposer/multilayer circuit substrate to meet interconnect requirements.
6. The method for manufacturing a three-dimensional stacked integrated structure of a high-power radio frequency chip according to claim 5, wherein the adhesion layer material is Ti/TiN/TiW.
7. The method for manufacturing the three-dimensional stacked integrated structure of the high-power radio frequency chip according to claim 5, wherein the low-K value adapter plate is a glass substrate, the K value ranges from 5 to 6, and the thickness is larger than or equal to 200 μm.
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| CN117394015A (en) * | 2023-10-27 | 2024-01-12 | 惠州市特创电子科技股份有限公司 | Three-dimensional phased array antenna package and preparation method thereof |
| CN117476631B (en) * | 2023-12-26 | 2024-03-22 | 广东仁懋电子有限公司 | Gallium nitride microwave power device |
| CN117976632A (en) * | 2024-04-02 | 2024-05-03 | 中国电子科技集团公司第二十九研究所 | Vertical interconnection structure of radio frequency chip and manufacturing method thereof |
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| US20180197829A1 (en) * | 2017-01-09 | 2018-07-12 | Qorvo Us, Inc. | Three-dimensional integrated circuit assembly with active interposer |
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