CN115159444B - Leadless three-dimensional heterogeneous integrated structure and manufacturing method thereof - Google Patents
Leadless three-dimensional heterogeneous integrated structure and manufacturing method thereof Download PDFInfo
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- CN115159444B CN115159444B CN202211045028.8A CN202211045028A CN115159444B CN 115159444 B CN115159444 B CN 115159444B CN 202211045028 A CN202211045028 A CN 202211045028A CN 115159444 B CN115159444 B CN 115159444B
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- B81—MICROSTRUCTURAL TECHNOLOGY
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- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0083—Temperature control
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- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
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Abstract
The invention discloses a leadless three-dimensional heterogeneous integrated structure and a manufacturing method thereof, the structure comprises a sealing bonding part, a vertical through hole part and a heterogeneous integrated part, wherein the sealing bonding part is a microelectronic sensor sealing ring, an optical waveguide sealing ring and a microchannel sealing ring which are made of materials compatible with a silicon through hole filling material, and the sealing bonding of the microelectronic sensor, the optical waveguide sealing ring and the microchannel is realized by using process conditions compatible with a silicon through hole bonding process; the vertical via portion comprises an optical vertical via, a microfluidic vertical via; the heterogeneous integration part is used for manufacturing an electrical interconnection structure, an optical interconnection structure and a cooling liquid circulation structure with a rewiring layer and micro bumps on a silicon wafer substrate, and realizes the on-wafer heterogeneous three-dimensional integration of chips with different functions by using the silicon wafer substrate, the airtight bonding structure and the silicon through hole adapter plate with the vertical through hole part, and has the function of local cooling and heat dissipation.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a three-dimensional heterogeneous integrated structure without leads and a manufacturing method thereof.
Background
With the advent of the world of everything interconnection and intelligent perception, microelectronic sensors are increasingly widely applied to factory production and daily life of people. Microelectronic sensors typically convert detected force, thermal, acoustic, optical, chemical, etc. signals into electrical signals that are read by an integrated circuit chip. Although microelectronic sensors are made of materials and fabricated in a similar manner to microelectronic integrated circuits, in actual production, the step coverage capability of the photoresist for different devices needs to be considered, since sensors usually have deep trench or floating sensitive structures and integrated circuits are planar structures. In addition, since the sensor and the integrated circuit are affected by the front and rear manufacturing processes, it is generally difficult to manufacture the sensor portion and the integrated circuit portion in one chip at the same time, and the monolithic integration of the sensor and the integrated circuit can be realized only by the delicate structural design and process design. Many electronic systems are formed by individually packaging the sensor and then soldering the sensor and the integrated circuit together on a circuit board, wherein the most commonly used way for leading out the sensor header signal is wire bonding. The packaging mode not only increases the occupied area, but also has obvious parasitic effect of overlong interconnecting wires. In addition, the wire bonding approach also reduces device reliability.
Although some documents report the leadless bonding technology of the sensor in recent years, the sensor is usually bonded to the substrate first, and then the lead holes of the substrate are filled with the conductive paste and the leads. The whole process is not only complicated, but also the materials such as conductive paste, pins and the like are incompatible with the integrated circuit process, and are difficult to be applied to the mixed integration of large-scale sensors and integrated circuits.
Through Silicon Via (TSV) technology is a key technology in the advanced packaging field, and chips are stacked in a three-dimensional direction by making vertical conduction between the chips and between the wafer and the wafer. The vertical conduction is generally realized by filling conductive materials such as copper, tungsten and the like in the deeply etched silicon through hole, the traditional lead bonding method is replaced, the interconnection length can be reduced, the signal delay is reduced, the capacitance/inductance is reduced, the power consumption is reduced, the speed is increased, the reliability of a device is improved, the bandwidth is increased, and the miniaturization of device integration is realized. However, microelectronic sensors usually have a three-dimensional suspension structure, hermetic bonding is required in many cases, and the single TSV bonding technology cannot provide the hermetic requirement of the microelectronic sensor. Meanwhile, as the degree of integration of an integrated circuit chip increases, the integrated circuit chip is subject to serious heat generation, and heat dissipation needs to be performed through microfluid.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a leadless three-dimensional heterogeneous integrated structure and a manufacturing method thereof, which utilize materials and process conditions compatible with a through silicon via technology to realize the common encapsulation of a three-dimensional microelectronic sensor and an integrated circuit on a through silicon via adapter plate, and the specific technical scheme is as follows:
a leadless three-dimensional heterogeneous integrated structure comprises a heterogeneous integrated part based on a silicon wafer substrate, a vertical through hole part based on a composite silicon through hole adapter plate, a sealing bonding part based on a sealing ring and chips with different functions; the heterogeneous integrated part is integrally connected with chips with different functions through the matching arrangement of the sealing bonding part and the vertical through hole part.
Further, the vertical through hole part based on the composite through silicon via interposer specifically includes: etching the composite silicon through hole adapter plate to obtain vertical through holes which are arranged separately or in a coupling manner, namely, the vertical through holes comprise an electrical vertical through hole, an optical vertical through hole and a microfluid vertical through hole which are arranged separately or in a coupling manner; the optical vertical through hole is internally provided with a cladding layer and a core layer, the material of the core layer is preferably but not limited to air, organic polymer SU8 or silicon, and the material of the cladding layer is preferably but not limited to silicon dioxide; cooling liquid flows up and down in the micro-fluid vertical through hole to dissipate heat of the chip; the electrical vertical through hole is preferably but not limited to silicon dioxide as an insulating layer of a side wall, and copper plating is filled in the hole to serve as conductive metal;
wherein the coupling setting is specifically: and respectively coupling or simultaneously coupling the electrical vertical through hole with the optical vertical through hole and the micro-fluid vertical through hole by adopting a hollow closed-loop or open-loop structure to form a composite vertical through hole structure for simultaneously providing electrical conduction, up-and-down flow of cooling liquid and optical path signal transmission.
Furthermore, the upper surface and the lower surface of the composite silicon through hole adapter plate are respectively etched with a bonding pad and a micro-bump by photoetching, the chips with different functions are bonded with the micro-bump on the composite silicon through hole adapter plate through the bonding pads of the chips, and then the electrical signals of the chips are led out without leads through the electrical vertical through holes.
Further, the heterogeneous integrated part based on the silicon wafer substrate, wherein the silicon wafer substrate is a single-layer or double-layer structure, and when the silicon wafer substrate is a single-layer structure, the heterogeneous integrated part specifically includes:
the silicon wafer substrate is provided with a rewiring layer in the horizontal direction, and the rewiring layer is connected with the electrical vertical through hole through the micro-bumps to form an electrical interconnection structure so as to electrically connect chips with different functions;
the optical waveguide structure is arranged on the silicon wafer substrate in the horizontal direction, and forms an optical interconnection structure through a micro mirror and an optical vertical through hole;
the horizontal micro-channel on the silicon wafer substrate is bonded with the micro-fluid vertical through hole to form a cooling fluid circulation structure;
when the silicon wafer substrate is of a double-layer structure, the method specifically comprises the following steps: the silicon wafer substrate is formed by three-dimensionally stacking an electrical transverse rewiring adapter plate on an upper layer and a microfluid-optical transverse rewiring adapter plate on a lower layer, wherein a rewiring layer and a vertical through hole are arranged on the electrical transverse rewiring adapter plate in the horizontal direction, and the microfluid-optical transverse rewiring adapter plate is provided with an optical waveguide structure, a micro-channel and a vertical through hole in the horizontal direction.
Further, the sealing bonding part is an optical waveguide sealing ring, a micro-channel sealing ring and a microelectronic sensor sealing ring which are made of materials compatible with filling materials of the vertical through hole part on the composite silicon through hole adapter plate.
Furthermore, the microelectronic sensor sealing ring hermetically bonds the corresponding microelectronic sensor on the composite silicon through hole adapter plate; the optical waveguide sealing ring is a copper sealing ring or a copper/tin sealing ring and grows around the bottom of the optical vertical through hole; the micro-channel sealing ring adopts a copper sealing ring or a copper/tin sealing ring and grows around the bottom of the micro-fluid vertical through hole, around the micro-channel in the horizontal direction and around the position of the bottom of the chip corresponding to the micro-channel in the horizontal direction; the microfluid vertical through hole, the micro-channel sealing ring, the horizontal micro-channel and the bottom of the chip form a closed pipeline, and cooling liquid in the closed pipeline is preferably, but not limited to water.
Further, the chips with different functions comprise microelectronic sensors, integrated circuit chips and optoelectronic chips.
A manufacturing method of a leadless three-dimensional heterogeneous integrated structure comprises the steps of taking a composite silicon through hole adapter plate as sealing bonding of a bonding substrate, and then taking a silicon wafer substrate as sealing bonding of the bonding substrate, so that the leadless three-dimensional heterogeneous integrated structure is formed;
specifically, the method comprises the following steps: etching an electrical vertical hole on a silicon wafer, oxidizing the inner side wall of the hole, sputtering a metal seed layer on the upper surface of the silicon wafer, electroplating to grow a copper column, polishing and regrowing a heavy wiring layer to form an electrical interconnection structure; then photoetching and etching the vertical hole, oxidizing the inner side wall of the hole and filling the core layer material of the vertical hole to obtain an optical vertical interconnection structure; then sputtering a metal seed layer on the upper surface of the silicon wafer, and photoetching and electroplating to grow micro bumps and sealing rings corresponding to chips with different functions; photoetching and etching a cavity groove for packaging a three-dimensional sensitive membrane of the microelectronic sensor on the upper surface of the silicon wafer; then thinning the lower surface of the silicon wafer to obtain an electrical vertical through hole and an optical vertical through hole, and continuing to grow a bonding pad, a micro-bump and a sealing ring on the lower surface in an electroplating way; directly etching a microfluid vertical through hole on the upper surface of the silicon wafer to obtain a composite silicon through hole adapter plate; finally, chips with different functions are integrally packaged on the composite silicon through hole adapter plate; then, the composite silicon through hole adapter plate integrated and packaged with the chip is hermetically bonded with the silicon wafer substrate, and is integrated and packaged into a leadless three-dimensional heterogeneous integrated structure;
wherein the bonding is copper-copper direct hot-press bonding or copper-tin transient liquid phase bonding, and when copper-copper direct hot-press bonding is adopted, the sputtering metal seed layer is preferably a titanium/copper seed layer, the thickness of an adhesion layer of titanium is preferably 300A-500A, the thickness of the metal seed layer of copper is preferably 3000A-5000A, and the heights of the copper column and the copper ring are preferably 3 μm-6 μm; when the copper-tin transient liquid phase bonding is adopted, the height of the tin layer generated by continuous electroplating is preferably 5-10 μm.
Further, when the chip adopts a microelectronic sensor, the bonding of the three-dimensional sensitive membrane of the microelectronic sensor on the silicon through hole adapter plate specifically comprises: and adopting copper-copper direct hot-pressing bonding or copper-tin transient liquid phase bonding to bond the three-dimensional sensitive membrane on the silicon through hole adapter plate in a sealing manner through a copper sealing ring or a copper/tin sealing ring.
Further, when the chip adopts a microelectronic sensor, the bonding step of the microelectronic sensor on the through silicon via interposer includes:
firstly, a titanium/copper seed layer is preferentially sputtered on the upper surface and the lower surface of a three-dimensional sensitive membrane, then the surface of the three-dimensional sensitive membrane with a deep groove structure is coated with a first photoresist by a glue spraying method, the surface of the three-dimensional sensitive membrane without the deep groove structure is coated with a second photoresist by a glue throwing method, the two surfaces are respectively photoetched with the graphs of a sealing ring and an electrode column and are electroplated to grow the sealing ring and the electrode column, then a corresponding copper sealing ring or a copper/tin sealing ring is electroplated and grown on a sensor bonding substrate, the three-dimensional sensitive membrane is hermetically bonded with the sensor bonding substrate by copper-copper direct hot-pressing bonding or copper-tin transient liquid phase bonding, an independent self-packaged microelectronic sensor is obtained after scribing, and finally the microelectronic sensor is bonded with a micro bump on a silicon through hole adapter plate through a bonding pad of the microelectronic sensor.
Compared with the prior art, the invention has the following advantages:
firstly, the invention realizes the on-chip three-dimensional heterogeneous integration of a microelectronic sensing chip, an integrated circuit chip and a photoelectric chip, has the function of local cooling and heat dissipation, and is not only suitable for chip-level multifunctional system integration, but also suitable for wafer-level multifunctional system integration.
Secondly, the invention uses the materials and process conditions compatible with the through silicon via technology, simultaneously realizes the airtight bonding of the microelectronic sensor and the lead-free electric signal extraction, and realizes the monolithic integration with the integrated circuit chip.
Thirdly, the bonding method using the silicon through hole adapter plate as the bonding substrate can simultaneously realize the airtight bonding of the sensitive diaphragm of the microelectronic sensor and the lead-free lead extraction of the electrical signal in a one-step bonding process, and has simple and convenient process and good compatibility.
Fourthly, the bonding method using the silicon wafer substrate as the bonding substrate solves the problem that the traditional photoresist spinning process is difficult to coat photoresist on the surface of the sensitive diaphragm of the microelectronic sensor with a deep groove structure through the photoresist spraying process, further realizes wafer-level airtight bonding of the microelectronic sensor, and can be popularized to multilayer airtight bonding.
Drawings
Fig. 1a to 1g are schematic structural diagrams of a main process flow of a three-dimensional sensitive membrane of a microelectronic sensor directly implementing hybrid co-encapsulation with an integrated circuit on a through silicon via interposer according to an embodiment of the present invention;
fig. 2a to 2i are schematic structural diagrams of a main process flow of implementing hybrid co-encapsulation with an integrated circuit through a through-silicon via interposer after a sensor is packaged according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a leadless, three-dimensional, heterogeneous integrated structure of a three-dimensional sensitive diaphragm employing a microelectronic sensor, in accordance with an embodiment of the present invention;
FIG. 4 is a schematic illustration of a leadless, heterogeneous integrated structure employing a microelectronic sensor in accordance with an embodiment of the present invention;
FIG. 5 is a schematic top view and a schematic cross-sectional view of an electro-optical-microfluidic composite vertical via structure according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a main process flow of a leadless three-dimensional heterogeneous integration of a hollow closed-loop electro-optical-microfluidic composite vertical via structure according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a main process flow of a leadless three-dimensional heterogeneous integration of a hollow open-loop electrical-optical-microfluidic composite vertical via structure in accordance with embodiments of the present invention;
FIGS. 8a to 8b are schematic diagrams of electrical, optical, microfluidic on-wafer transverse rewiring based on a hollow open-loop electrical-optical-microfluidic composite vertical via structure according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a three-dimensional heterogeneous integrated structure without leads when a silicon wafer substrate according to an embodiment of the present invention has a double-layer structure.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
Example 1:
as shown in fig. 3 and 4, a leadless three-dimensional heterogeneous integrated structure according to an embodiment of the present invention realizes on-chip three-dimensional heterogeneous integration of chips with different functions, and includes a heterogeneous integrated portion based on a silicon wafer substrate 19, a vertical through hole portion based on a composite through-silicon-via interposer 20, a seal bonding portion based on a seal ring, and chips with different functions; the heterogeneous integrated part is in integrated connection with chips with different functions through the matching arrangement of the sealing bonding part and the vertical through hole part; wherein the different functional chips include microelectronic sensors 17, integrated circuit chips 18, optoelectronic chips 22, etc.
The vertical through hole part based on the composite through silicon via interposer 20 specifically includes: etching the composite silicon through hole adapter plate 20 to obtain an optical vertical through hole 21, wherein a cladding layer and a core layer are arranged in the optical vertical through hole, the material of the core layer is preferably but not limited to air, organic polymer SU8 or silicon, and the material of the cladding layer is preferably but not limited to silicon dioxide;
etching and growing an electrical vertical through hole 1 on the composite silicon through hole adapter plate 20, photoetching and etching the upper surface and the lower surface of the composite silicon through hole adapter plate 20 respectively to form a bonding pad and a micro-bump, bonding chips with different functions with the micro-bump on the composite silicon through hole adapter plate 20 through the bonding pad per se, and then leading out an electrical signal of the chip without a lead through the electrical vertical through hole 1. The partial structure is used as an electrical lead-out structure of the chip, so that electrical lead-free lead-out is realized, and the traditional lead bonding mode is replaced.
And etching a micro-fluid vertical through hole 23 for the cooling liquid to flow up and down on the composite silicon through hole adapter plate 20.
The sealing bonding part is a microelectronic sensor sealing ring 7, an optical waveguide sealing ring 30 and a micro-channel sealing ring 31 which are made of materials compatible with the filling materials of the vertical through hole part on the composite silicon through hole adapter plate 20, and the microelectronic sensor 17, the optical waveguide circuit and the micro-channel are hermetically bonded by adopting process conditions compatible with a silicon through hole bonding process.
The microelectronic sensor sealing ring 7 hermetically bonds the microelectronic sensor 17 to the composite through-silicon-via interposer 20.
A copper sealing ring or a copper/tin sealing ring is grown around the bottom of the optical vertical through hole 21 to serve as an optical waveguide sealing ring 30 which is used for being in sealing bonding with the silicon wafer substrate 19; micro-channel sealing rings 31 are grown around the bottoms of the micro-fluid vertical through holes 23, around the horizontal micro-channel 27 and around the corresponding positions of the bottoms of the chips and the horizontal micro-channel 27, and the micro-channel sealing rings 31 are copper sealing rings or copper/tin sealing rings 31 and are used for being in sealing bonding with the silicon wafer substrate 19.
The micro-fluid vertical through hole 23, the micro-channel sealing ring 31, the horizontal micro-channel 27 and the bottom of the integrated circuit chip 18 to be cooled form a closed pipeline, and the cooling liquid in the closed pipeline, preferably but not limited to water, flows in the closed pipeline and takes away heat generated during the operation of the chip.
The heterogeneous integrated part based on the silicon wafer substrate 19 specifically includes:
the silicon wafer substrate 19 is provided with a rewiring layer 24 in the horizontal direction, and the rewiring layer is connected with the electrical vertical through hole 1 through micro bump bonding to form an electrical interconnection structure, so that electrical signals are led out, and chips with different functions are electrically connected with each other;
the optical waveguide structure in the horizontal direction on the silicon wafer substrate 19 forms an optical interconnection structure through the micro-mirror 40 and the optical vertical through hole 21, so that an optical path for the optoelectronic device to communicate with the outside is realized;
the horizontal micro-channel 27 on the silicon wafer substrate 19 is used for absorbing heat when the cooling liquid flows in the horizontal direction, and forms a cooling liquid circulation structure together with the micro-fluid vertical through hole 23 for the cooling liquid to flow up and down.
The integrated structure can be heterogeneous integration of chip-level multifunctional chips and can also be heterogeneous integration of wafer-level multifunctional chips; the through-silicon-via interposer 20 may be one or more, and may be a three-dimensional stack of one or more layers.
The manufacturing method of the leadless three-dimensional heterogeneous integrated structure comprises the steps of taking a composite silicon through hole adapter plate 20 as the sealing bonding of a bonding substrate, and then taking a silicon wafer substrate 19 as the sealing bonding of the bonding substrate, so as to form the leadless three-dimensional heterogeneous integrated structure;
specifically, the method comprises the following steps: etching an electrical vertical hole on a silicon wafer, oxidizing the inner side wall of the hole, sputtering a metal seed layer on the upper surface of the silicon wafer, electroplating to grow a copper column, polishing and regrowing a heavy wiring layer 24 to form an electrical interconnection structure; then photoetching and etching the vertical hole, oxidizing the inner side wall of the hole and filling the core layer material of the vertical hole to obtain an optical vertical interconnection structure; then sputtering a metal seed layer on the upper surface of the silicon wafer, photoetching and electroplating to grow micro bumps and sealing rings corresponding to chips with different functions; etching a cavity groove for packaging the three-dimensional sensitive membrane of the microelectronic sensor 17 on the upper surface of the silicon wafer by photoetching; then thinning the lower surface of the silicon wafer to obtain an electrical vertical through hole 1 and an optical vertical through hole 21, and continuing to grow a bonding pad, a micro-bump and a sealing ring on the lower surface in an electroplating way; then directly etching a microfluid vertical through hole 23 on the upper surface of the silicon wafer to obtain a composite silicon through hole adapter plate 20; finally, chips with different functions are integrally packaged on the composite silicon through hole adapter plate 20; and then, the composite silicon through hole adapter plate 20 integrated and packaged with the chip is hermetically bonded with the silicon wafer substrate 19, and is integrated and packaged into a three-dimensional heterogeneous integrated structure without a lead.
In this embodiment, as shown in fig. 1a to 1g, a main process structure of a three-dimensional sensitive membrane 9 of a microelectronic sensor directly implementing mixed co-encapsulation with an integrated circuit chip on a through silicon via interposer 20 specifically includes the following contents:
a titanium/copper seed layer 2 is preferably sputtered on the upper and lower surfaces of the composite through silicon via interposer 20, as shown in FIG. 1a, the thickness of the adhesion layer is preferably 300A to 500A for titanium, and 3000A to 5000A for copper.
Photoetching patterns of an electrode column and a sealing ring of the microelectronic sensor on the upper surface of the through silicon via adapter plate 20, and growing a copper column and a copper ring 3 at the positions of the electrode column and the sealing ring, as shown in fig. 1b, preferably, the height of the electroplated copper column/ring is 3-6 μm; if a copper-tin bonding mode is adopted subsequently, a tin layer 4 is required to be grown through electroplating, the height is 5-10 mu m, and the height is shown in figure 1 c; if copper-copper bonding is subsequently adopted, no tin layer needs to be grown.
Respectively photoetching and etching a bonding pad 5 on the upper surface and the lower surface of the through silicon via adapter plate 20, as shown in fig. 1 d; then, a sealed cavity 6 of the microelectronic sensor is etched and etched on the surface of the through silicon via interposer 20, as shown in fig. 1 e.
The three-dimensional sensitive membrane 9 and the integrated circuit chip 18 of the microelectronic sensor are integrally packaged on the through silicon via adapter plate 20 under the conditions of completely same bonding temperature, pressure and the like, the bonding method is copper-copper direct hot-pressing bonding as shown in figure 1f, or copper-tin transient liquid phase bonding as shown in figure 1g, the vacuum degree can be adjusted according to needs during the bonding of the microelectronic sensor, the bonding temperature is preferably 200-400 ℃, the bonding pressure is preferably 0.5-30MPa, and the bonding time is preferably 15-120min.
In the bonding process, the airtight bonding of the three-dimensional sensitive membrane 9 of the microelectronic sensor and the lead-free electric signal extraction of the three-dimensional sensitive membrane 9 and the integrated circuit chip 18 are simultaneously completed.
Fig. 2a to 2g show the structure of the main process flow for implementing hybrid co-encapsulation with the integrated circuit through the through-silicon via interposer after the sensor is packaged.
A titanium/copper seed layer 2 is preferably sputtered on the upper and lower surfaces of the wafer-level three-dimensional sensitive membrane 9, the thickness of the titanium is preferably 300A-500A for the thickness of the adhesive layer, and the thickness of the copper is preferably 3000A-5000A for the thickness of the seed layer, as shown in FIG. 2 a.
And (3) spraying glue on the surface of the three-dimensional sensitive membrane with the deep groove structure to realize first photoresist coating 11, throwing glue on the surface of the three-dimensional sensitive membrane without the deep groove structure to realize second photoresist coating 12, and photoetching the front surface and the back surface to form a graph of the sealing ring and the electrode column respectively, as shown in figure 2 b.
Electroplating to grow a sealing ring 13 and an electrode column 14, preferably to electroplate a copper column/ring with a height of 3 to 6 μm, as shown in FIG. 2 c; then, a corresponding copper seal ring 15 is grown on the wafer-level sensor bonding substrate in an electroplating way, as shown in fig. 2d, if a copper-tin bonding way is adopted subsequently, a tin layer 16 is also grown in an electroplating way, the height is preferably 5-10 μm, as shown in fig. 2e, if the copper-copper bonding way is adopted subsequently, the tin layer is not required to be grown; thereafter, a first step bonding is performed, using copper-copper direct thermocompression bonding, as shown in fig. 2f, or copper-tin transient liquid phase bonding, as shown in fig. 2g, to achieve wafer level hermetic bonding of the sensor.
The microelectronic sensor 17 and the integrated circuit chip 18 are integrally packaged on the silicon wafer substrate 19 under the same bonding temperature, pressure and the like by using copper-copper direct thermocompression bonding as shown in fig. 2h or copper-tin transient liquid phase bonding as shown in fig. 2 i.
The integrated structure can be chip-level multifunctional chip heterogeneous integration or wafer-level multifunctional chip heterogeneous integration; the through-silicon-via interposer 20 may be one or more, and may be a three-dimensional stack of one or more layers.
Example 2:
as shown in fig. 9, a schematic diagram of a three-dimensional heterogeneous integrated structure without leads when a silicon wafer substrate (19) of an embodiment of the present invention is a two-layer structure. The specific contents are as follows:
in order to further improve the utilization rate of the area of the composite through-silicon-via interposer 20 and further improve the integration density and the heat dissipation capability of the optoelectronic integrated system, the electrical vertical through-hole 1 may adopt a hollow ring-shaped or open ring-shaped structure and is coupled with the optical vertical through-hole 21 and the microfluidic vertical through-hole 23 to form a composite vertical through-hole structure capable of providing electrical conduction, up-and-down flow of cooling liquid and optical path signal transmission simultaneously.
As shown in fig. 5, (a) in fig. 5 shows that the electrical through hole 1, the optical vertical through hole 21 and the microfluidic vertical through hole 23 which adopt a solid structure are separately arranged on the composite through silicon via interposer 20, and (b) in fig. 5 to (l) in fig. 5 are schematic composite vertical through hole structures which adopt a hollow closed ring or hollow open ring structure, wherein the electrical vertical through hole 1, the optical vertical through hole 21 and the microfluidic vertical through hole 23 are respectively coupled or simultaneously coupled to form a structure capable of providing electrical conduction, up-and-down flow of cooling liquid and optical path signal transmission simultaneously. The cross section shapes of the electrical vertical through hole 1, the optical vertical through hole 21 and the micro-fluid vertical through hole 23 can be made into a round shape, a square shape or other polygons as required, the cross sections of the three can be set into a solid shape, a hollow shape or a semi-hollow shape as required, the shapes of the three can be set into an open loop or a closed loop as required by wiring, and the three can be arranged in a vertical mode as required or can be set into two or three coupling modes. Fig. 5 (m) is a cross-sectional structure of the coupling structure of fig. 5 (d). Fig. 5 (n) is a cross-sectional structure of fig. 5 (f) or fig. 5 (i), and the patterning of the deep trench step can also be achieved by using the deep trench glue spraying process. An optical waveguide sealing ring 30 and a micro-channel sealing ring 31 are also respectively arranged around the surfaces of the optical vertical through hole 21 and the micro-fluid vertical through hole 23, and (o) in fig. 5 is a schematic structural diagram of manufacturing the optical waveguide sealing ring and the micro-channel sealing ring on the surface of the composite vertical through hole structure (g) in fig. 5.
As shown in fig. 6, the main process flow of the leadless three-dimensional heterogeneous integration based on the hollow closed-loop electro-optical-microfluidic composite vertical through hole structure of the embodiment of the present invention specifically includes the following steps:
in the first step, an electrical deep groove structure 32 and an optical deep groove structure 33 are etched on the upper surface of the composite through silicon via interposer 20 by photolithography, and the sidewalls are oxidized.
Secondly, sputtering and growing seed layer metal, spraying glue to protect the optical deep groove and imaging the electrical deep groove, filling the electrical deep groove with electroplated copper, removing the seed layer metal and polishing the front surface; preferably, an organic polymer SU8 is filled in the optical deep groove to form a core layer, and the upper surface of the composite through-silicon-via adapter plate 20 is respectively etched by photoetching to form a sealed cavity 6 of the microelectronic sensor; spraying glue for protection, photoetching and etching a microfluid deep groove structure 34, thinning and polishing the back surface to obtain a composite silicon through hole adapter plate which is simultaneously provided with a microelectronic sensor sealing cavity 6, a hollow annular electrical vertical through hole 1 and an optical vertical through hole 21 and a microfluid vertical through hole 23; and finally, growing a microelectronic sensor sealing ring 3, an optical waveguide sealing ring 30 and a micro-channel sealing ring 31 on the front surface and the back surface of the composite silicon through hole adapter plate.
And thirdly, arranging transverse rewiring 35 of the electrical interconnection line on the silicon chip, and continuously and vertically leading out the micro-fluid vertical through hole 23 of the optical vertical through hole 21 to obtain an electrical transverse rewiring adapter plate 36.
And fourthly, etching a transverse connecting groove 37 of the micro-channel and a transverse connecting groove 38 of the optical passage on the silicon chip, forming a cladding 39 on the structure of the transverse connecting groove 38 of the optical passage, manufacturing a micro-mirror 40 in the groove structure of the silicon chip by etching silicon or obliquely photoetching photosensitive organic matter and metalizing, and preferably filling organic polymer SU8 in the groove structure to form a core layer 41 to obtain the micro-fluid-optical transverse rewiring adapter plate 42.
And fifthly, stacking the composite through silicon via adapter plate 20, the electrical transverse rewiring adapter plate 36 and the microfluid-optical transverse rewiring adapter plate 42 in three dimensions to obtain a silicon substrate with electrical, optical and microfluidic channels capable of being transmitted in any transverse direction and longitudinal direction in an integrated structure. And then the microelectronic sensing chip 9, the integrated circuit chip 18 and the silicon optical chip 22 are integrated on the silicon substrate, so that the three-dimensional heterogeneous integration of multiple chips is realized.
As shown in fig. 7, the main process flow of a leadless three-dimensional heterogeneous integration based on a hollow open-loop electro-optical-microfluidic composite vertical via structure according to the embodiment of the present invention; since the electrical vertical via 1 outside the composite vertical via structure employed in this embodiment is an open-loop structure, the lateral rewiring of the microfluidic vertical via 23 inside can be done on the same silicon rewiring interposer 42 as the lateral rewiring of the electrical vertical via 1.
Fig. 8a to 8b are schematic diagrams of electrical, optical, microfluidic on-wafer transverse rewiring based on a hollow open-loop electrical-optical-microfluidic composite vertical via structure according to an embodiment of the present invention. Fig. 8a is a bottom pattern of a hollow open-loop composite vertical via on the composite through-silicon-via interposer 20, and fig. 8b is a corresponding electrical, optical, microfluidic on-wafer redistribution pattern on the upper surface of the silicon redistribution interposer 42.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the foregoing has described in detail the practice of the invention, it will be appreciated by those skilled in the art that variations may be applied to the embodiments described in the foregoing examples, or equivalents may be substituted for elements thereof. All changes, equivalents and the like which come within the spirit and principles of the invention are desired to be protected.
Claims (5)
1. A three-dimensional heterogeneous integrated structure without a lead is characterized by comprising a heterogeneous integrated part based on a silicon wafer substrate (19), a vertical through hole part based on a composite silicon through hole adapter plate (20), a sealing bonding part based on a sealing ring and chips with different functions; the heterogeneous integrated part is in integrated connection with chips with different functions through the matching arrangement of the sealing bonding part and the vertical through hole part;
the vertical through hole part based on the composite silicon through hole adapter plate (20) specifically comprises: vertical through holes which are arranged separately or in a coupling way are obtained on the composite silicon through hole adapter plate (20) through etching, namely, the electrical vertical through hole (1), the optical vertical through hole (21) and the microfluid vertical through hole (23) are arranged separately or in a coupling way;
the optical vertical through hole is internally provided with a cladding layer and a core layer, the core layer is made of air and organic polymer SU8 or silicon, and the cladding layer is made of silicon dioxide; cooling liquid flows up and down in the micro-fluid vertical through hole (23) to dissipate heat of the chip; silicon dioxide is filled in the electrical vertical through hole to serve as an insulating layer of the side wall, and copper plating is filled in the hole to serve as conductive metal;
wherein the coupling setting is specifically: the electrical vertical through hole (1) is respectively coupled with the optical vertical through hole (21) and the micro-fluid vertical through hole (23) or is simultaneously coupled with the optical vertical through hole (21) by adopting a hollow closed-loop or open-loop structure to form a composite vertical through hole structure for simultaneously providing electrical conduction, up-down flow of cooling liquid and optical path signal transmission;
the upper surface and the lower surface of the composite silicon through hole adapter plate (20) are respectively etched with a bonding pad and a micro-bump in a photoetching way, the chips with different functions are bonded with the micro-bump on the composite silicon through hole adapter plate (20) through the bonding pad per se, and then the electrical signals of the chips are led out without leads through the electrical vertical through holes (1);
the heterogeneous integrated part based on the silicon wafer substrate (19), wherein the silicon wafer substrate (19) is of a single-layer structure or a double-layer structure, and when the silicon wafer substrate is of a single-layer structure, the heterogeneous integrated part specifically comprises the following steps:
a rewiring layer (24) in the horizontal direction is arranged on the silicon wafer substrate (19), and the rewiring layer and the electrical vertical through hole (1) are connected through the micro-bumps to form an electrical interconnection structure so as to electrically connect chips with different functions;
a horizontal optical waveguide structure on the silicon wafer substrate (19), the optical waveguide structure forming an optical interconnect structure with an optical vertical via (21) through a micromirror (40);
a horizontal micro channel (27) on the silicon wafer substrate (19) is bonded with the micro-fluid vertical through hole (23) to form a cooling fluid circulation structure;
when the silicon wafer substrate (19) is a double-layer structure, the method specifically comprises the following steps: the silicon wafer substrate (19) is formed by three-dimensionally stacking an electrical transverse rewiring adapter plate (36) on the upper layer and a microfluid-optical transverse rewiring adapter plate (42) on the lower layer, wherein a rewiring layer (24) in the horizontal direction and a vertical through hole are arranged on the electrical transverse rewiring adapter plate (36), and the microfluid-optical transverse rewiring adapter plate (42) is provided with an optical waveguide structure, a microchannel and a vertical through hole in the horizontal direction;
the sealing bonding part is an optical waveguide sealing ring (30), a micro-channel sealing ring (31) and a microelectronic sensor sealing ring (7) which are made of materials compatible with the filling material of the vertical through hole part on the composite silicon through hole adapter plate (20);
the microelectronic sensor sealing ring (7) is used for bonding a corresponding microelectronic sensor (17) on the composite silicon through hole adapter plate (20) in an airtight mode; the optical waveguide sealing ring (30) adopts a copper sealing ring or a copper/tin sealing ring and grows around the bottom of the optical vertical through hole (21); the micro-channel sealing ring (31) adopts a copper sealing ring or a copper/tin sealing ring, and grows around the bottom of the micro-fluid vertical through hole (23), around the horizontal micro-channel (27) and around the position of the bottom of the chip corresponding to the horizontal micro-channel (27); the micro-fluid vertical through hole (23), the micro-channel sealing ring (31), the horizontal micro-channel (27) and the bottom of the chip form a closed pipeline, and cooling liquid in the closed pipeline comprises water.
2. A leadless three-dimensional heterogeneous integrated structure according to claim 1, wherein said chips of different functions comprise microelectronic sensors (17), integrated circuit chips (18), optoelectronic chips (22).
3. A manufacturing method of a leadless three-dimensional heterogeneous integrated structure is characterized in that a through silicon via adapter plate (20) is used for sealing bonding of a bonding substrate, and then a silicon wafer substrate (19) is used for sealing bonding of the bonding substrate, so that the leadless three-dimensional heterogeneous integrated structure is formed;
specifically, the method comprises the following steps: etching an electrical vertical hole in a silicon wafer and carrying out oxidation on the inner side wall of the hole, sputtering a metal seed layer on the upper surface of the silicon wafer and electroplating to grow a copper column, and polishing and regrowing a heavy wiring layer (24) to form an electrical interconnection structure; then photoetching and etching the vertical hole, oxidizing the inner side wall of the hole and filling the core layer material of the vertical hole to obtain an optical vertical interconnection structure; then sputtering a metal seed layer on the upper surface of the silicon wafer, photoetching and electroplating to grow micro bumps and sealing rings corresponding to chips with different functions; photoetching and etching a cavity groove for packaging a three-dimensional sensitive membrane of the microelectronic sensor on the upper surface of the silicon wafer; then thinning the lower surface of the silicon wafer to obtain an electrical vertical through hole (1) and an optical vertical through hole (21), and continuing to electroplate and grow a bonding pad, a micro bump and a sealing ring on the lower surface; then directly etching a microfluid vertical through hole (23) on the upper surface of the silicon wafer to obtain a composite silicon through hole adapter plate (20); finally, chips with different functions are integrated and packaged on the composite silicon through hole adapter plate (20); then, the composite silicon through hole adapter plate (20) which is integrated and packaged with the chip is hermetically bonded with the silicon wafer substrate (19) and is integrated and packaged into a leadless three-dimensional heterogeneous integrated structure;
wherein the bonding employs copper-copper direct hot-press bonding or copper-tin transient liquid phase bonding, and when employing copper-copper direct hot-press bonding, the sputtered metal seed layer is a sputtered titanium/copper seed layer, an adhesion layer thickness of titanium is 300A-500A, a metal seed layer thickness of copper is 3000A-5000A, and heights of the copper column and the copper ring are 3 μm-6 μm; and when the copper-tin transient liquid phase bonding is adopted, the height of the tin layer generated by continuous electroplating is 5-10 mu m.
4. A method for manufacturing a leadless three-dimensional heterogeneous integrated structure, according to claim 3, wherein when the chip is a microelectronic sensor, the bonding of the three-dimensional sensitive membrane (9) of the microelectronic sensor on the composite through silicon via interposer (20) is specifically: and the three-dimensional sensitive membrane (9) is hermetically bonded on the silicon through hole adapter plate (20) through a copper sealing ring or a copper/tin sealing ring by adopting copper-copper direct hot-pressing bonding or copper-tin transient liquid phase bonding.
5. The method for manufacturing a leadless three-dimensional heterogeneous integrated structure according to claim 3, wherein when the chip is a microelectronic sensor, the step of bonding the microelectronic sensor on the composite through-silicon-via interposer (20) comprises:
firstly, sputtering a titanium/copper seed layer (2) on the upper surface and the lower surface of a three-dimensional sensitive membrane (9), then coating a first photoresist (11) on the surface of the three-dimensional sensitive membrane (9) with a deep groove structure by using a glue spraying method, coating a second photoresist (12) on the surface of the three-dimensional sensitive membrane (9) without the deep groove structure by using a glue throwing method, photoetching graphs of a sealing ring and an electrode column on the two surfaces respectively, electroplating to grow the sealing ring (13) and the electrode column (14), electroplating to grow a corresponding copper sealing ring or a copper/tin sealing ring on a sensor bonding substrate, then carrying out copper-copper direct hot-pressing bonding or copper-tin transient liquid phase bonding to carry out airtight bonding on the three-dimensional sensitive membrane (9) and the sensor bonding substrate, obtaining an independent self-packaged microelectronic sensor (17) after scribing, and finally carrying out bonding with a micro bump on the composite silicon through hole adapter plate (20) through a bonding pad of the microelectronic sensor (17).
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| CN1935630A (en) * | 2006-10-18 | 2007-03-28 | 中国科学院上海微系统与信息技术研究所 | Micro electromechanical system chip size airtight packaging vertical interconnecting structure and its manufacturing method |
| US7928563B2 (en) * | 2008-05-28 | 2011-04-19 | Georgia Tech Research Corporation | 3-D ICs with microfluidic interconnects and methods of constructing same |
| CN102024782B (en) * | 2010-10-12 | 2012-07-25 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
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| CN110054141A (en) * | 2019-03-27 | 2019-07-26 | 西人马联合测控（泉州）科技有限公司 | Pressure sensor and its packaging method |
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