CN111312703A - Three-dimensional hybrid integrated circuit packaging structure and assembling method - Google Patents
Three-dimensional hybrid integrated circuit packaging structure and assembling method Download PDFInfo
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- CN111312703A CN111312703A CN202010090969.8A CN202010090969A CN111312703A CN 111312703 A CN111312703 A CN 111312703A CN 202010090969 A CN202010090969 A CN 202010090969A CN 111312703 A CN111312703 A CN 111312703A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 147
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 230000000149 penetrating effect Effects 0.000 claims abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000005476 soldering Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims 2
- 239000007787 solid Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 10
- 238000003466 welding Methods 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 description 10
- 238000004804 winding Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
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- 238000011161 development Methods 0.000 description 3
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- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention provides a three-dimensional hybrid integrated circuit packaging structure and an assembly method, belonging to the technical field of semiconductor packaging, and comprising a packaging shell, a lower substrate and an upper substrate, wherein the packaging shell is provided with a pin penetrating through a bottom plate of the packaging shell; the upper layer substrate and the lower layer substrate are laminated and interconnected through a BGA (ball grid array) ball-planting flip-chip bonding process; the front welding disc of the lower layer substrate and the front welding disc of the upper layer substrate are both provided with components. The three-dimensional hybrid integrated circuit packaging structure provided by the invention can improve the integration level of the hybrid integrated circuit, and meanwhile, components which are large in size and need to be debugged can be placed on the upper substrate, so that the individual debugging and the individual assembly are convenient, other components are not damaged during the debugging, the operability of the product is improved, and the assembly difficulty is simplified.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a three-dimensional hybrid integrated circuit packaging structure and an assembly method.
Background
The mixed integrated circuit is an important circuit design and integration mode in the technical field of microelectronics, has flexible design, short development period, debugging and wide working frequency range, and is widely applied to microwave circuit products.
The thin film hybrid integrated circuit is a ceramic substrate which is made by a thin film process such as evaporation, sputtering, electroplating and the like on a ceramic substrate, has high line precision, can design a thin film resistor, and is suitable for assembly modes such as sticking, bonding and the like. Then, the discrete micro-elements and devices are assembled on the ceramic substrate, and the assembled discrete micro-elements and devices can be semiconductor chips or monolithic integrated circuits, and the like, and finally, the hybrid integrated circuit is formed by additional packaging and sealing.
Hybrid integrated circuits, particularly thin film hybrid integrated circuits, are an area of advantage at low frequencies. For example, microwave circuit products below 6GHz often need discrete capacitance, resistance, inductance and other elements in the circuit, and these elements have large volumes, and must be integrated by adopting a hybrid integrated circuit mode, while MMIC circuits are difficult to implement.
The main problems in the existing hybrid integrated circuit technology are as follows: due to the adoption of a two-dimensional plane integration technology, all components are mounted on the ceramic substrate in the maximum plane direction, and certain span is needed between the lead bonding of the semiconductor chip and the like and the ceramic substrate from one welding point to the other welding point. In addition, the ceramic substrate is required to be assembled with necessary thin film resistors, thin film capacitors, thin film inductors and the like according to the requirements of specific circuits, so that the number of components mounted on the surface of the ceramic substrate is limited, and especially, components with large volumes occupy most of the area and space on the ceramic substrate.
Meanwhile, as the operating frequency of the product is reduced, some components in the circuit must adopt components matched with the frequency. As the frequency decreases, the capacitance of the capacitor, the inductance of the inductor, and the resistance of the resistor increase, and the Q value, i.e., the quality factor, is also required to be higher. For example, tantalum capacitors, which function as filters, core-wound inductors, magnetic-ring-wound inductors, and the like, which function as matching, feeding, and transformers, are much larger in size than semiconductor chip devices.
The two-dimensional plane integration technology not only affects the product volume and reduces the integration level, but also brings certain influence and limitation in the aspects of circuit design, component assembly and circuit debugging.
With the development of the three-dimensional integration technology, the three-dimensional integration technology is introduced into the hybrid integrated circuit, so that the assembly density of components in the hybrid integrated circuit can be effectively improved, the packaging size of a product is reduced, and the adaptability and the technical development of the hybrid integrated circuit are further improved.
However, in the three-dimensional hybrid integrated circuit, it is also necessary to provide an effective technical approach for solving the problems of layout and debugging of components with large size.
Disclosure of Invention
The invention aims to provide a three-dimensional hybrid integrated circuit packaging structure, aiming at solving the problems of inconvenient debugging of components and inconvenient layout of components with larger volume.
In order to achieve the purpose, the invention adopts the technical scheme that: there is provided a three-dimensional hybrid integrated circuit package structure, including: the packaging structure comprises a packaging shell, a lower substrate and an upper substrate, wherein the packaging shell is provided with a pin penetrating through a bottom plate of the packaging shell; the lower substrate is connected with the packaging shell through a lower back bonding pad arranged on the back of the lower substrate, a lower front bonding pad is arranged on the front of the lower substrate, and the lower front bonding pad and the pins are connected with each other through gold wire bonding; the front surface of the upper-layer substrate is provided with an upper-layer front bonding pad, the back surface of the upper-layer substrate is provided with an upper-layer back bonding pad, the upper-layer substrate is provided with a plurality of metal filling holes for connecting the upper-layer front bonding pad and the upper-layer back bonding pad, solder balls arranged in an array mode are arranged between the upper-layer substrate and the lower-layer substrate, and the upper-layer substrate and the lower-layer substrate are connected in a laminated mode through a BGA (ball grid array) ball-planting flip-chip bonding process; and components are arranged on the lower-layer front bonding pad of the lower-layer substrate and the upper-layer front bonding pad of the upper-layer substrate.
As another embodiment of this application, components and parts on the positive pad of upper strata are for waiting the magnetic core wire winding inductance and the first paster device of debugging, magnetic core wire winding inductance pass through the enameled wire with the positive pad of upper strata links to each other, the components and parts that are equipped with on the positive pad of lower floor's base plate are semiconductor chip and the second paster device that do not need the debugging, the volume of first paster device is greater than the volume of second paster device.
As another embodiment of the present application, the magnetic core wire-wound inductor and the first chip device are fixed on the upper-layer front pad by pasting or welding.
As another embodiment of the present application, the semiconductor chip and the second chip device are fixed on the lower front surface bonding pad by pasting or soldering.
As another embodiment of the present application, the solder balls in the BGA flip chip mounting are disposed directly below the metal filling holes in a one-to-one correspondence.
As another embodiment of the present application, the upper substrate and the lower substrate are both ceramic pieces.
As another embodiment of the present application, the lower back pad of the lower substrate is fixed to the bottom plate of the package housing by a conductive adhesive.
As another embodiment of this application, lower floor's back pad tiling the back of lower floor's base plate, just the side all around of lower floor's back pad with the side parallel and level all around of lower floor's base plate.
The invention also provides an assembly method of the three-dimensional hybrid integrated circuit packaging structure, which comprises the following steps:
arranging a component on a lower-layer front bonding pad of a lower-layer substrate;
connecting a lower-layer back bonding pad of the upper-layer substrate with a lower-layer front bonding pad of the lower-layer substrate by using a BGA (ball grid array) ball-planting flip-chip bonding process to realize the laminated interconnection of the upper-layer substrate and the lower-layer substrate;
fixing a lower-layer back pad of the laminated and interconnected lower-layer substrate to a bottom plate of the packaging shell;
fixing a component on an upper-layer front bonding pad of the upper-layer substrate;
and bonding the lower-layer front bonding pad of the lower-layer substrate with the pin of the packaging shell through the gold wire, and realizing signal connection of the components fixed on the upper-layer substrate through the metal filling hole, the solder ball, the lower-layer front bonding pad, the gold wire and the pin.
The three-dimensional hybrid integrated circuit packaging structure and the assembling method provided by the invention have the beneficial effects that: compared with the prior art, the three-dimensional hybrid integrated circuit packaging structure provided by the invention realizes the stacking application of two substrates in product packaging by utilizing the Ball Grid Array (BGA) technology. Assembling a lower substrate and an upper substrate by adopting a thin film assembly process; assembling a semiconductor chip and a surface-mounted component on a lower substrate, and interconnecting the upper substrate and the lower substrate by using a BGA ball-planting flip-chip bonding process to realize a laminated substrate; then assembling the laminated substrate on a bottom plate of the package housing; then, mounting components such as a large-volume chip capacitor and a magnetic core winding inductor needing debugging on the upper-layer substrate; and finally, connecting the port of the lower substrate or the upper substrate with a packaging pin by using gold wire welding, wherein the main performance debugging points are arranged on the upper substrate, and can be subjected to fine adjustment, local debugging and even component specification replacement so as to meet performance indexes.
The invention utilizes the three-dimensional circuit to improve the integration level of the hybrid integrated circuit, can place components which have larger volume and need to be debugged on the upper substrate, is convenient for independent debugging and independent assembly, does not damage other devices during debugging, improves the operability of products and simplifies the assembly difficulty.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a three-dimensional hybrid integrated circuit package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a package housing according to an embodiment of the present invention;
FIG. 3 is a schematic view of a lower substrate according to an embodiment of the present invention;
FIG. 4 is a schematic view of an upper substrate structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a component assembly of a lower substrate according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating a process of stacking a lower substrate and an upper substrate according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a lower substrate and an upper substrate stacked together according to an embodiment of the present invention;
fig. 8 is a structural diagram of an upper substrate provided in an embodiment of the present invention after a component is mounted thereon;
fig. 9 is a schematic manufacturing flow chart of a three-dimensional hybrid integrated circuit package structure according to an embodiment of the invention.
In the figure: 1. a package housing; 2. a pin; 3. a lower substrate; 4. an upper substrate; 5. a lower front bonding pad; 6. a lower back pad; 7. an upper-layer front-side bonding pad; 8. an upper layer back pad; 9. filling the hole with metal; 10. a solder ball; 11. gold wire; 12. a semiconductor chip; 13. a first chip device; 14. a magnetic core winding inductor; 15. enamelled wires; 16. a second patch device.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 8, a three-dimensional hybrid integrated circuit package structure provided by the present invention will be described. The three-dimensional hybrid integrated circuit packaging structure comprises a packaging shell 1, a lower substrate 3 and an upper substrate 4, wherein the packaging shell 1 is provided with a pin 2 penetrating through a bottom plate of the packaging shell 1; the lower substrate 3 is connected with the packaging shell 1 through a lower back pad 6 arranged on the back of the lower substrate 3, a lower front pad 5 is arranged on the front of the lower substrate 3, and the lower front pad 5 and the pins 2 are bonded and interconnected through gold wires 11; the front surface of the upper-layer substrate 4 is provided with an upper-layer front surface bonding pad 7, the back surface of the upper-layer substrate 4 is provided with an upper-layer back surface bonding pad 8, the upper-layer substrate 4 is provided with a plurality of metal filling holes 9 used for connecting the upper-layer front surface bonding pad 7 and the upper-layer back surface bonding pad 8, solder balls 10 arranged in an array mode are arranged between the upper-layer substrate 4 and the lower-layer substrate 3, and the upper-layer substrate 4 and the lower-layer substrate 3 are connected in a laminated mode through a BGA ball-planting flip-chip bonding process; and components are arranged on the lower-layer front bonding pad 5 of the lower-layer substrate 3 and the upper-layer front bonding pad 7 of the upper-layer substrate 4.
Compared with the prior art, the three-dimensional hybrid integrated circuit packaging structure provided by the invention realizes the stacking application of two substrates in product packaging by utilizing the Ball Grid Array (BGA) technology. Assembling a lower substrate 3 and an upper substrate 4 by adopting a thin film assembly process; assembling a semiconductor chip 12 and a mounting component on a lower substrate 3, and interconnecting an upper substrate 4 and the lower substrate 3 by using a BGA ball-mounting flip-chip bonding process to realize a laminated substrate; then the laminated substrate is assembled to the bottom plate of the package can 1; then, mounting components such as a large-volume chip capacitor and a magnetic core winding inductor 14 to be debugged on the upper substrate 4; and finally, the ports of the lower substrate 3 or the upper substrate 4 are connected with the packaging pins 2 by welding with gold wires 11, wherein main performance debugging points are arranged on the upper substrate 4, and can be subjected to fine adjustment, local debugging and even component specification replacement so as to meet performance indexes.
The invention utilizes the three-dimensional circuit to improve the integration level of the hybrid integrated circuit, and simultaneously can place components which have larger volume and need to be debugged on the upper substrate 4, thereby facilitating the independent debugging and the independent assembly, and not damaging other components during the debugging, improving the operability of the product and simplifying the assembly difficulty.
When the circuit performance is debugged, the tightness degree and the wiring mode of the enameled wire 15 can be adjusted, and the specification of a surface mounted device or the specification of the magnetic core winding inductor 14 can be changed to meet the required circuit performance index. When a component on the upper substrate 4 is replaced or debugged, the other components such as the semiconductor chip 12 are not damaged.
In the invention, the packaging shell 1 is mainly used for bearing a ceramic substrate and sealing and protecting an internal circuit after assembling and debugging indexes; the lead 2 is mainly used for signal connection with the substrate through gold wire 11 bonding in the package, and is led out of the package shell 1.
Ball Grid Array, BGA for short, is a surface mount package for multi-pin LSI (Large-scale integrated circuit) in which Ball contacts are formed as pins on the back of a substrate in an Array manner, and components are mounted on the front of the substrate (part of the BGA chip and the terminals are on the same surface of the substrate). In this embodiment, two layers of substrates are provided, the ball grid array solder balls 10 are led out from the back of the upper substrate 4, components can be mounted on the front of the upper substrate 4 and the front of the lower substrate 3, the integration level of the hybrid integrated circuit is improved, and meanwhile, the components which are large in size and need to be debugged are placed on the upper ceramic substrate, so that independent debugging and independent assembly are facilitated.
Wherein the metal filled holes 9 serve to connect signals and ground.
As a specific embodiment of the three-dimensional hybrid integrated circuit package structure provided by the present invention, please refer to fig. 1, the components on the upper front pad 7 are a magnetic core winding inductor 14 and a first chip device 13 to be debugged, the magnetic core winding inductor 14 is connected to the upper front pad 7 through an enameled wire 15, the components on the lower front pad 5 of the lower substrate 3 are a semiconductor chip 12 and a second chip device 16 that do not need to be debugged, and the semiconductor chip 12 and the second chip device 16 that do not need to be debugged are interconnected with the lower front pad 5 through a gold wire 11, and the volume of the first chip device 13 is larger than the volume of the second chip device 16. The components and parts needing to be debugged and the components and parts with large size are fixed on the upper substrate 4, so that the components and parts can be conveniently debugged and assembled independently, other components are not damaged during debugging, the overall height or size of a packaged device can be reduced, and the operability of the product is improved and the assembly difficulty is simplified.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1, the core wire-wound inductor 14 and the first chip device 13 are fixed on the upper front pad 7 by adhesion or soldering.
Referring to fig. 1, as a specific implementation manner of the embodiment of the present invention, the semiconductor chip 12 and the second chip device 16 are fixed on the lower front surface pad 5 by adhesion or soldering.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1, the solder balls 10 in the BGA flip chip mounting process are correspondingly disposed right below the metal filling holes 9. The solder ball 10 is a solder ball, a copper pillar, a gold bump, or an alloy bump.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1, the upper substrate 4 and the lower substrate 3 are both ceramic pieces. Front and back circuit patterns are mounted on the front and back surfaces of the upper substrate 4 and the lower substrate 3 using a thin film process technique.
As a specific implementation manner of the embodiment of the invention, referring to fig. 1, a lower back pad 6 of the lower substrate 3 is fixed to a bottom plate of the package housing 1 through a conductive adhesive.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1, the lower back pad 6 is flatly laid on the back surface of the lower substrate 3, and the peripheral side surface of the lower back pad 6 is flush with the peripheral side surface of the lower substrate 3.
Referring to fig. 1 to 9, the present invention further provides an assembling method of a three-dimensional hybrid integrated circuit package structure, including the following steps:
s101: arranging components on a lower-layer front bonding pad 5 of the lower-layer substrate 3;
s102: connecting a lower-layer back bonding pad 6 of the upper-layer substrate 4 and a lower-layer front bonding pad 5 of the lower-layer substrate 3 by using a BGA ball-planting flip-chip bonding process to realize the lamination interconnection of the upper-layer substrate 4 and the lower-layer substrate 3;
s103: fixing the lower back pad 6 of the laminated and interconnected lower substrate 3 on the bottom plate of the packaging shell 1;
fixing components on the upper-layer front bonding pad 7 of the upper-layer substrate 4;
s104: and a lower-layer front bonding pad 5 of the lower-layer substrate 3 is bonded with a pin 2 of the packaging shell 1 through a gold wire 11, and a component fixed on the upper-layer substrate 4 is in signal connection with the pin 2 through a metal filling hole 9, a solder ball 10, the lower-layer front bonding pad 5, the gold wire 11 and the pin.
In this embodiment, the BGA ball-mounting flip-chip bonding process is a packaging technique for the conventional multi-pin 2 device and circuit. The BGA is characterized by using solder balls 10 as the leads 2, which not only improves the packaging density, but also improves the packaging performance.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. Three-dimensional solid hybrid integrated circuit packaging structure, its characterized in that includes:
the packaging shell is provided with pins penetrating through a bottom plate of the packaging shell;
the lower substrate is connected with the packaging shell through a lower back bonding pad arranged on the back of the lower substrate, a lower front bonding pad is arranged on the front of the lower substrate, and the lower front bonding pad and the pins are connected with each other through gold wire bonding;
the front surface of the upper-layer substrate is provided with an upper-layer front bonding pad, the back surface of the upper-layer substrate is provided with an upper-layer back bonding pad, the upper-layer substrate is provided with a plurality of metal filling holes for connecting the upper-layer front bonding pad and the upper-layer back bonding pad, solder balls arranged in an array mode are arranged between the upper-layer substrate and the lower-layer substrate, and the upper-layer substrate and the lower-layer substrate are connected in a laminated mode through a BGA (ball grid array) ball-planting flip-chip bonding process;
and components are arranged on the lower-layer front bonding pad of the lower-layer substrate and the upper-layer front bonding pad of the upper-layer substrate.
2. The package structure of claim 1, wherein the components on the upper front pad are a core wire inductor to be debugged and a first chip device, the core wire inductor is connected to the upper front pad through an enameled wire, the components on the lower front pad of the lower substrate are a semiconductor chip and a second chip device that do not need to be debugged, and the volume of the first chip device is larger than the volume of the second chip device.
3. The package structure of claim 2, wherein the core wire inductor and the first chip device are attached to the upper front pad by gluing or soldering.
4. The package structure of claim 2, wherein the semiconductor chip and the second chip device are attached to the lower front side pad by gluing or soldering.
5. The package structure of claim 1, wherein the solder balls in the BGA flip chip are disposed directly under the metal filling holes in a one-to-one correspondence.
6. The package structure of claim 1, wherein the upper substrate and the lower substrate are ceramic pieces.
7. The package structure of claim 1, wherein the lower back pads of the lower substrate are secured to the bottom plate of the package housing by a conductive adhesive.
8. The package structure of claim 1, wherein the lower back pad is tiled on the back side of the lower substrate and the peripheral side of the lower back pad is flush with the peripheral side of the lower substrate.
9. The method of assembling the three dimensional hybrid integrated circuit package structure of any of claims 1-8, comprising the steps of:
arranging a component on a lower-layer front bonding pad of a lower-layer substrate;
connecting a lower-layer back bonding pad of the upper-layer substrate with a lower-layer front bonding pad of the lower-layer substrate by using a BGA (ball grid array) ball-planting flip-chip bonding process to realize the laminated interconnection of the upper-layer substrate and the lower-layer substrate;
fixing a lower-layer back pad of the laminated and interconnected lower-layer substrate to a bottom plate of the packaging shell;
fixing a component on an upper-layer front bonding pad of the upper-layer substrate;
and bonding the lower-layer front bonding pad of the lower-layer substrate with the pin of the packaging shell through the gold wire, and realizing signal connection of the components fixed on the upper-layer substrate through the metal filling hole, the solder ball, the lower-layer front bonding pad, the gold wire and the pin.
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| CN202010090969.8A CN111312703A (en) | 2020-02-13 | 2020-02-13 | Three-dimensional hybrid integrated circuit packaging structure and assembling method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111933623A (en) * | 2020-06-29 | 2020-11-13 | 中国航空工业集团公司北京长城航空测控技术研究所 | Packaging interconnection structure and method based on substrate side bonding pad |
| CN112992476A (en) * | 2021-02-05 | 2021-06-18 | 南京矽力微电子技术有限公司 | Transformer, and package module |
| CN114743963A (en) * | 2022-04-15 | 2022-07-12 | 江苏芯德半导体科技有限公司 | Multilayer chip packaging structure and packaging process thereof |
-
2020
- 2020-02-13 CN CN202010090969.8A patent/CN111312703A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111933623A (en) * | 2020-06-29 | 2020-11-13 | 中国航空工业集团公司北京长城航空测控技术研究所 | Packaging interconnection structure and method based on substrate side bonding pad |
| CN111933623B (en) * | 2020-06-29 | 2024-02-27 | 中国航空工业集团公司北京长城航空测控技术研究所 | Packaging interconnection structure and method based on substrate side bonding pad |
| CN112992476A (en) * | 2021-02-05 | 2021-06-18 | 南京矽力微电子技术有限公司 | Transformer, and package module |
| CN112992476B (en) * | 2021-02-05 | 2022-08-12 | 合肥矽力杰半导体技术有限公司 | Transformer, and package module |
| CN114743963A (en) * | 2022-04-15 | 2022-07-12 | 江苏芯德半导体科技有限公司 | Multilayer chip packaging structure and packaging process thereof |
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