CN114759015A - Three-dimensional stacking integrated structure of high-power radio frequency chip and preparation method thereof - Google Patents
Three-dimensional stacking integrated structure of high-power radio frequency chip and preparation method thereof Download PDFInfo
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- CN114759015A CN114759015A CN202210201064.2A CN202210201064A CN114759015A CN 114759015 A CN114759015 A CN 114759015A CN 202210201064 A CN202210201064 A CN 202210201064A CN 114759015 A CN114759015 A CN 114759015A
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
Abstract
The invention discloses a three-dimensional stacking integrated structure of a high-power radio-frequency chip and a preparation method thereof, wherein the three-dimensional stacking integrated structure comprises a multilayer circuit substrate, the high-power radio-frequency chip and a low-K value adapter plate which are sequentially arranged from bottom to top, the low-K value adapter plate is inversely arranged on the upper surface of the high-power radio-frequency chip, a plurality of independent electromagnetic isolation structures are formed on the high-power radio-frequency chip, other chips or elements are arranged on the low-K value adapter plate, the other chips or elements are mutually connected with the low-K value adapter plate, and the low-K value adapter plate is electrically connected with the high-power radio-frequency chip. The three-dimensional stacking structure is compatible with the traditional hybrid integration process, the mainstream heat sink heat dissipation technology can be used, the silicon-based through hole heat dissipation or micro-channel heat dissipation structure is avoided, the reliability is improved, the processing period is shortened, and the processing cost is reduced.
Description
Technical Field
The invention relates to the technical field of radio frequency chips, in particular to a three-dimensional stacking integrated structure of a high-power radio frequency chip and a preparation method thereof.
Background
From the form of the high-density integrated product of the existing high-power radio frequency chip, a multi-chip module (MCM) technology is mainly adopted, the high-power radio frequency chip (such as GaAs and GaN chips) and a micro chip element are assembled on an LTCC or multi-layer PCB substrate, and the cascade connection of the element and the multifunctional substrate is realized by adopting gold wire bonding and other modes. Generally, high-power radio frequency chip integration generally requires an air cavity structure with the height of several millimeters above a chip to mount all chips and peripheral matching circuits in a two-dimensional direction of a substrate in a tiled mode, so that the performance of the radio frequency chip can meet the requirements, but a large amount of circuit effective area is occupied. The method has the defects that the product volume is large, the requirement of high-density integration of multiple channels of a radio frequency unit is not met, and the integration density of the channels needs to be improved in a chip three-dimensional stacking mode so as to improve the functional density of the channels.
At present, in the patents related to stacking of high-power rf chips (for example, patents CN108766897B and CN108083223A), a multi-stack multi-cavity package structure is mostly adopted, and the package structure adopts silicon material as both the package cavity and the sidewall routing layer to realize vertical interconnection. However, the main problems of this integration method are that the product volume is still large, the stacking integration structure is complex, the vertical interconnection path is long, and the difficulty in manufacturing vertical through holes on the side wall of the tube shell is large, which results in low product reliability, poor performance, high cost, long processing period, and difficult popularization and application in engineering.
The three-dimensional stacking structure of the high-power radio frequency chip is an effective way for further improving the integration density. However, at present, few reports of three-dimensional stacked structures in the field of high-power radio frequency exist, and the following technical difficulties mainly exist: (a) the electromagnetic compatibility design difficulty is high, the height of an air cavity on the surface of a microwave circuit through flip-chip welding is limited, and a high-power radio frequency chip easily causes self-excitation or crosstalk. (b) When the high-power chip needs to be designed in a multi-stage and multi-channel mode, the stack structure is easy to cause electromagnetic interference, and electromagnetic isolation needs to be enhanced between a front-stage transistor and a final-stage transistor of the high-power radio-frequency chip and among multiple channels. (c) The peripheral circuit of the high-power radio frequency chip is complex, circuits such as a drive circuit, a power supply circuit and a detection circuit are often needed, the high-density integration difficulty is high, and the requirements of high-density integration and electromagnetic compatibility are difficult to meet. (d) Vertical interconnection is realized through a wiring layer on the side wall of the packaging cavity, the integrated structure is complex, the process difficulty is high, and the engineering practicability is poor. (f) The heat flow density of the three-dimensional stacked integrated high-power GaN chip can reach more than 100W/cm2, which is far beyond the heat dissipation capability of the silicon substrate, and a through hole heat dissipation structure or a micro-channel heat dissipation structure needs to be manufactured on the silicon substrate, so that the substrate has poor reliability, long processing period and high processing cost.
Disclosure of Invention
Aiming at the defects in the prior art, the three-dimensional stacking integrated structure of the high-power radio frequency chip and the preparation method thereof provided by the invention solve the problems that the current high-power radio frequency chip integrated product is large in volume, the three-dimensional stacking integrated structure is complex, the electromagnetic compatibility design difficulty is high, high-density integration is difficult to carry out, and heat dissipation is difficult.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: the utility model provides a three-dimensional integrated configuration that piles up of high-power radio frequency chip, includes multilayer circuit substrate, high-power radio frequency chip, the low K value keysets that sets gradually from supreme down, the flip-chip of low K value keysets forms a plurality of independent electromagnetic isolation structures at the upper surface of high-power radio frequency chip, be equipped with other chips or components on the low K value keysets, other chips or components and low K value keysets interconnect, the low K value keysets realizes electrical connection with high-power radio frequency chip.
Further: the high-power radio frequency chip comprises a high-power radio frequency chip and is characterized in that a front-stage transistor and a last-stage transistor are arranged on the upper surface of the high-power radio frequency chip from left to right, a metalized grounding layer on the lower surface of the high-power radio frequency chip is arranged on the lower surface of the high-power radio frequency chip, a chip radio frequency signal transmission hole and a chip grounding hole are arranged in the high-power radio frequency chip in a penetrating mode, vertical signal hole bonding pads are arranged on the upper surface and the lower surface of the chip radio frequency signal transmission hole, micro-bump shielding ball bonding pads are arranged on the upper surface and the lower surface of the chip grounding hole, the high-power radio frequency chip comprises two radio frequency channels from top to bottom, inter-transistor micro-bump shielding balls are arranged between the front-stage transistor and the last-stage transistor, and two inter-channel micro-bump shielding ball bonding pads are arranged between multiple channels.
Further: the high-power radio frequency chip is a leadless interconnection chip, the upward radio frequency input/output port of the high-power radio frequency chip is of a vertical signal transmission micro-bump inverted structure, and the downward input/output port structure is of a radio frequency transmission through hole structure.
Further: the low-K value adapter plate is characterized in that a large-area metalized grounding layer is arranged on the upper surface of the low-K value adapter plate, an adapter plate micro-bump bonding pad is arranged in an area, corresponding to the micro-bump shielding ball bonding pad, of the lower surface of the low-K value adapter plate, the large-area metalized grounding layer is connected with the adapter plate micro-bump bonding pad through an adapter plate grounding hole, and the adapter plate micro-bump bonding pad is connected with the micro-bump shielding ball bonding pad through a micro-bump shielding ball.
Further: the structure of the input/output port of the low-K adapter plate and other chips or elements is a radio frequency channel structure, and the structure of the downward signal input/output port is a transmission through hole structure.
Further: the electromagnetic isolation structure comprises a plurality of independent air cavities consisting of micro-convex-point shielding balls, a chip lower surface metalized grounding layer, a chip grounding hole, a micro-convex-point shielding ball bonding pad, a large-area metalized grounding layer, an adapter plate grounding hole and an adapter plate micro-convex-point bonding pad.
Further: the other chips or elements are positioned on the large-area metalized grounding layer, the other chips or elements are interconnected with the signal bonding pad of the adapter plate through a lead, and the signal interconnection of the signal bonding pad of the adapter plate and the high-power radio frequency chip is realized through the vertical signal transmission micro-bump.
A method for preparing a three-dimensional stacking integrated structure of a high-power radio frequency chip comprises the following steps:
step 1: providing a low-K value adapter plate;
step 2: manufacturing a through hole for the low-K value adapter plate;
and step 3: preparing an adhesion layer on the surface of the low-K adapter plate;
and 4, step 4: carrying out high-precision metal electroplating filling on the through hole;
and 5: plating gold or nickel-palladium-gold on the surface of the adhesion layer by using an electroplating process to form a metallization layer;
step 6: assembling a bare chip on the metallized low-K value adapter plate by adopting a micro-assembly eutectic process;
and 7: planting balls on the lower surface of the low-K adapter plate, and manufacturing gold balls or solder balls by adopting a laser ball planting process;
and 8: mounting a high-power radio frequency chip on the multilayer circuit substrate;
and step 9: bonding the low-K adapter plate to a high-power radio frequency chip;
step 10: other chips or components are attached to the upper surface of the low-K interposer/multi-layer circuit substrate to meet the interconnect requirements.
Further: the material of the adhesion layer is Ti/TiN/TiW.
Further: the low-K adapter plate is a glass substrate, the K value range is 5-6, and the thickness is larger than or equal to 200 mu m.
The invention has the beneficial effects that:
(1) the invention adopts the low-K value adapter plate and the micro-convex-point shielding balls to reduce the height of the air cavity of the high-power chip from thousands of microns to dozens of microns, greatly reduces the thickness of the assembly, improves the electromagnetic compatibility and avoids the self-excitation and crosstalk of the power chip. Meanwhile, the vertical interconnection of radio frequency signals is realized, and the vertical interconnection is not realized through a wiring layer on the side wall of the packaging cavity, so that the integration level is improved, the integration complexity and the process difficulty are reduced, and the method has strong innovation and engineering practicability.
(2) The invention integrates the high-power radio frequency chip and the peripheral circuit thereof in a three-dimensional stacking manner, reduces the channel area occupied by the peripheral circuit, and improves the integration density of the channel, thereby reducing the radio frequency multi-channel spacing to meet the requirements of the radio frequency unit on working frequency improvement, modularization, generalization and extension.
(3) The three-dimensional stacking structure is compatible with the traditional hybrid integration process, the mainstream heat sink heat dissipation technology can be used, the silicon-based through hole heat dissipation or micro-channel heat dissipation structure is avoided, the reliability is improved, the processing period is shortened, and the processing cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a three-dimensional stacking integrated structure of a high-power RF chip;
FIG. 2 is a schematic top view of a high power RF chip;
FIG. 3 is a schematic top surface view of a low K interposer;
FIG. 4 is a schematic view of a lower surface of a low K interposer;
FIG. 5 is a schematic diagram of a process for fabricating a three-dimensional stacked integrated structure of a high power RF chip.
Wherein: 1. a multilayer circuit substrate; 2. a high-power radio frequency chip; 3. a low K value adapter plate; 4. other chips or components; 5. a chip ground hole; 6. a grounding hole of the adapter plate; 7. a micro-bump shielding ball; 8. a chip radio frequency signal transmission hole; 9. an interposer signal pad; 10. a large area metallized ground plane; 11. the micro convex points shield the ball bonding pads; 12. the adapter plate micro-convex-point bonding pad; 13. the lower surface of the chip is provided with a metalized grounding layer; 14. a preceding stage transistor; 15. a final stage transistor; 16. a lead wire; 17. an electromagnetic isolation structure; 18. vertical signal transmission micro-bumps; 19. micro-bump shielding balls among the transistors; 20. multi-channel inter-micro bump shielding ball bonding pads; 21. vertical signal via pads.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, a three-dimensional stacking integrated structure of a high-power radio frequency chip comprises a multilayer circuit substrate 1, a high-power radio frequency chip 2 and a low-K adapter plate 3 which are sequentially arranged from bottom to top, wherein the low-K adapter plate 3 is inversely arranged on the upper surface of the high-power radio frequency chip 2, a plurality of independent electromagnetic isolation structures 17 are formed on the high-power radio frequency chip 2, other chips or elements 4 are arranged on the low-K adapter plate 3, the other chips or elements 4 are interconnected with the low-K adapter plate 3, and the low-K adapter plate 3 is electrically connected with the high-power radio frequency chip 2.
According to the scheme shown in the figure 1, the adapter plate is inversely arranged on the upper surface of the high-power radio frequency chip, and a plurality of independent air cavity electromagnetic isolation structures are skillfully formed above the high-power radio frequency chip. Other radio frequency or digital chips and other elements can be continuously and normally arranged above the low-K value adapter plate, so that the integration density is greatly improved.
As shown in fig. 2, the high-power rf chip 2 is a compound semiconductor chip, the upper surface of the high-power rf chip 2 is provided with a front-stage transistor 14 and a final-stage transistor 15 from left to right, the lower surface of the high-power rf chip 2 is provided with a metalized ground layer 13 on the lower surface of the chip, the high-power rf chip 2 is provided with a chip rf signal transmission hole 8 and a chip ground hole 5 in a penetrating manner, the upper surface and the lower surface of the chip rf signal transmission hole 8 are provided with vertical signal hole pads 21, the upper surface and the lower surface of the chip ground hole 5 are provided with micro-bump shielding ball pads 11, the high-power rf chip 2 comprises two rf channels from top to bottom, inter-transistor micro-bump shielding balls 19 are arranged between the front-stage transistor 14 and the final-stage transistor 15, and multi-channel inter-micro-bump shielding ball pads 20 are arranged between the two rf channels.
As shown in fig. 3 and 4, the upper surface of the low-K value interposer 3 is provided with a large-area metalized ground layer 10, the area of the lower surface of the low-K value interposer 3 corresponding to the micro-bump shielding ball pad 11 is provided with an interposer micro-bump pad 12, the large-area metalized ground layer 10 is connected with the interposer micro-bump pad 12 through the interposer ground hole 6, and the interposer micro-bump pad 12 is connected with the micro-bump shielding ball pad 11 through the micro-bump shielding ball 7.
The electromagnetic isolation structure 17 comprises a plurality of independent air cavities consisting of a micro-bump shielding ball 7, a chip lower surface metallization grounding layer 13, a chip grounding hole 5, a micro-bump shielding ball bonding pad 11, a large-area metallization grounding layer 10, an adapter plate grounding hole 6 and an adapter plate micro-bump bonding pad 12. Each unit circuit air cavity is surrounded by shielding balls respectively, and the unit circuit air cavity comprises a shielding ball between a preceding transistor and a final transistor of the high-power radio frequency chip, a shielding ball between multiple channels of the high-power radio frequency chip and a shielding ball on the outer ring of the high-power chip.
The upper surface of the low-K value adapter plate and the input/output port structures of other chips are radio frequency channel structures, and the downward signal input/output port structure is a transmission through hole structure.
The high-power radio frequency chip 2 is a leadless interconnection chip, the upward radio frequency input/output port structure is a vertical signal transmission micro-bump inverted structure, and the downward input/output port structure is a radio frequency transmission through hole structure.
The spacing of the micro-bump shielding balls can be in a single-row arrangement design or in a double-row spacing arrangement design. The diameter of the micro-bump shielding ball structure is 60-120 mu m, and the solder balls are gold balls.
The other chips or components 4 include other radio frequency chips or other digital chips, capacitive chip components, resistive chip components, and the like.
The multilayer circuit substrate 1 is a high-heat-dissipation ceramic substrate or a high-frequency printed board with an embedded copper core.
A three-dimensional stacking integrated structure of a high-power radio frequency chip and a preparation method thereof are disclosed, the implementation process comprises the following steps, as shown in FIG. 5:
step (1): a low K interposer is provided. And manufacturing a through hole for the low-K value adapter plate. And (3) carrying out precise exposure on the adapter plate by adopting deep ultraviolet light with special wavelength (250-300 nm) to realize the modification of the micropore graph of the adapter plate. Followed by a high temperature heat treatment to effect ion aggregation and recrystallization of the exposed portions. And (3) carrying out micropore corrosion on the modified glass by adopting a high-precision HF corrosion process.
Step (2): and (3) cleaning the surface of the low-K adapter plate, and preparing the TiW adhesion layer by using a magnetron sputtering method. And (3) performing high-precision metal electroplating and filling Cu on the through hole by adopting methods such as a reverse pulse power supply, jet stirring, plating solution circulating filtration and the like.
And (3): and plating gold on the surface of the adhesion layer by using an electroplating process to form a metalized gold layer.
And (4): the bare chip is assembled to the metallized interposer using a micro-assembly eutectic process.
And (5): and planting gold balls on the lower surface of the adapter plate by adopting a laser ball planting process.
And (6): and (3) sticking the high-power radio frequency chip to the LTCC substrate by adopting a micro-assembly eutectic process.
And (7): and bonding the adapter plate to the high-power radio frequency chip by adopting an ultrasonic hot-pressing flip-chip bonding capability process.
Claims (10)
1. The utility model provides a three-dimensional integrated configuration that piles up of high-power radio frequency chip, its characterized in that includes multilayer circuit substrate (1), high-power radio frequency chip (2), low K value keysets (3) that set gradually from supreme down, low K value keysets (3) flip-chip forms a plurality of independent electromagnetic isolation structures (17) on high-power radio frequency chip (2) at the upper surface of high-power radio frequency chip (2), be equipped with other chips or component (4) on low K value keysets (3), other chips or component (4) interconnect with low K value keysets (3), electrical connection is realized with high-power radio frequency chip (2) in low K value keysets (3).
2. The three-dimensional stacking integrated structure of high-power radio-frequency chips according to claim 1, wherein a front-stage transistor (14) and a rear-stage transistor (15) are disposed on the upper surface of the high-power radio-frequency chip (2) from left to right, a metalized ground layer (13) is disposed on the lower surface of the high-power radio-frequency chip (2), a chip radio-frequency signal transmission hole (8) and a chip ground hole (5) are formed through the high-power radio-frequency chip (2), a vertical signal hole bonding pad (21) is disposed on the upper surface and the lower surface of the chip radio-frequency signal transmission hole (8), a micro-bump shielding ball bonding pad (11) is disposed on the upper surface and the lower surface of the chip ground hole (5), the high-power radio-frequency chip (2) comprises two radio-frequency channels from top to bottom, and an inter-transistor micro-bump shielding ball (19) is disposed between the front-stage transistor (14) and the rear-stage transistor (15), and a multi-channel micro-bump shielding ball bonding pad (20) is arranged between the two radio frequency channels.
3. The three-dimensional stacked integrated structure of high-power radio frequency chip according to claim 1, wherein the high-power radio frequency chip (2) is a leadless interconnection chip, and the upward radio frequency input/output port is a vertical signal transmission micro-bump flip-chip structure, and the downward input/output port is a radio frequency transmission through-hole structure.
4. The three-dimensional stacking integrated structure of the high-power radio-frequency chip as claimed in claim 2, wherein a large-area metalized ground layer (10) is arranged on the upper surface of the low-K value interposer (3), an interposer micro-bump bonding pad (12) is arranged in an area of the lower surface of the low-K value interposer (3) corresponding to the micro-bump shielding ball bonding pad (11), the large-area metalized ground layer (10) is connected with the interposer micro-bump bonding pad (12) through an interposer grounding hole (6), and the interposer micro-bump bonding pad (12) is connected with the micro-bump shielding ball bonding pad (11) through a micro-bump shielding ball (7).
5. The three-dimensional stacked integrated structure of high-power radio frequency chips as claimed in claim 1, wherein the input/output port structure of the low-K interposer (3) and other chips or components (4) is a radio frequency channel structure, and the downward signal input/output port structure is a transmission via structure.
6. The three-dimensional stacked integrated structure of a high-power radio-frequency chip according to claim 4, wherein the electromagnetic isolation structure (17) comprises a plurality of independent air cavities consisting of a micro-bump shielding ball (7), a lower-surface metallized ground layer (13) of the chip, a chip ground hole (5), a micro-bump shielding ball pad (11), a large-area metallized ground layer (10), an interposer ground hole (6) and an interposer micro-bump pad (12).
7. The three-dimensional stacking integrated structure of high-power radio-frequency chips according to claim 6, characterized in that the other chips or components (4) are located on a large-area metallized ground layer (10), the other chips or components (4) are interconnected with the signal pads (9) of the interposer through leads (16), and the signal pads (9) of the interposer are interconnected with the high-power radio-frequency chips (2) through vertical signal transmission micro bumps (18).
8. A preparation method of a three-dimensional stacking integrated structure of a high-power radio frequency chip is characterized by comprising the following steps:
step 1: providing a low-K adapter plate;
and 2, step: manufacturing a through hole for the low-K value adapter plate;
and step 3: preparing an adhesive layer on the surface of the low-K adapter plate;
and 4, step 4: carrying out high-precision metal electroplating filling on the through hole;
and 5: plating gold or nickel-palladium-gold on the surface of the adhesion layer by using an electroplating process to form a metallization layer;
step 6: assembling a bare chip on the metallized low-K value adapter plate by adopting a micro-assembly eutectic process;
and 7: planting balls on the lower surface of the low-K adapter plate, and manufacturing gold balls or solder balls by adopting a laser ball planting process;
and 8: mounting a high-power radio frequency chip on the multilayer circuit substrate;
and step 9: bonding the low-K adapter plate to a high-power radio frequency chip;
step 10: other chips or components are attached to the upper surface of the low-K interposer/multi-layer circuit substrate to meet the interconnection requirements.
9. The method for preparing the three-dimensional stacked integrated structure of the high-power RF chip as claimed in claim 8, wherein the material of the adhesion layer is Ti/TiN/TiW.
10. The method for preparing the three-dimensional stacked integrated structure of the high-power radio-frequency chip according to claim 8, wherein the low-K adapter plate is a glass substrate, the K value is in a range of 5-6, and the thickness is larger than or equal to 200 μm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115159444A (en) * | 2022-08-30 | 2022-10-11 | 之江实验室 | Leadless three-dimensional heterogeneous integrated structure and manufacturing method thereof |
| CN117476631A (en) * | 2023-12-26 | 2024-01-30 | 广东仁懋电子有限公司 | Gallium nitride microwave power device |
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