CN116314065A - Semiconductor package structure including heat spreader and method of manufacturing the same - Google Patents
Semiconductor package structure including heat spreader and method of manufacturing the same Download PDFInfo
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- CN116314065A CN116314065A CN202310019662.2A CN202310019662A CN116314065A CN 116314065 A CN116314065 A CN 116314065A CN 202310019662 A CN202310019662 A CN 202310019662A CN 116314065 A CN116314065 A CN 116314065A
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- dissipation shell
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000017525 heat dissipation Effects 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000004806 packaging method and process Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 5
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 abstract description 4
- 230000006978 adaptation Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 57
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 230000008054 signal transmission Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 3
- 229910021389 graphene Inorganic materials 0.000 description 3
- 229910002804 graphite Inorganic materials 0.000 description 3
- 239000010439 graphite Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000000320 mechanical mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The application relates to a semiconductor packaging structure comprising a radiator and a manufacturing method thereof, wherein the semiconductor packaging structure comprises a substrate, a conductive component, a plurality of chips and a radiating shell, the conductive component is fixed on the surface of the substrate, the conductive component is a polyhedron, the conductive component is provided with a circuit layer electrically connected with the substrate, each surface of the conductive component is provided with a connecting point electrically connected with the circuit layer, the functional surfaces of the chips are in one-to-one correspondence with each surface of the conductive component and are electrically connected with the connecting points, and the circuit layer is used for electrically connecting the substrate and the chips; the heat dissipation shell is one end open-ended tubular structure, heat dissipation shell open end is fixed in the base plate surface, and conductive component and a plurality of chip are all located inside the heat dissipation shell, and heat dissipation shell inside wall and a plurality of chip looks adaptation to make each chip laminating in each inside wall of casing. The chip packaging method and device are beneficial to improving the chip packaging efficiency.
Description
Technical Field
The present disclosure relates to the field of chip packaging, and more particularly, to a semiconductor package structure including a heat spreader and a method of manufacturing the same.
Background
Modern electronic information technology is rapidly developed, and electronic products are gradually developed towards miniaturization, portability and multifunction. With the miniaturization of electronic products, the packaging structure of the electronic products is also developed towards high density, high precision, fine pitch, high reliability, multilayering, high-speed transmission and the like.
In the related art, the three-dimensional integration technology has important significance in the technical field of chip packaging, two or more chips are packaged in a stacking manner by utilizing a multi-chip stacking packaging process, and circuit interconnection is formed among the chips, so that packaging space can be effectively utilized, higher integration level is realized, the chips are directly interconnected, the length of interconnection lines is obviously shortened, signal transmission is faster, and interference is less. However, the arrangement of the conductive components among the multiple layers of chips is scattered, the conductive paths are long, and the transmission of signals is affected, so that the chip packaging process is complicated.
Accordingly, there is a need for a semiconductor package structure including a heat spreader and a method of manufacturing the same.
Disclosure of Invention
In order to effectively improve the chip packaging efficiency, the application provides a semiconductor packaging structure comprising a radiator and a manufacturing method thereof.
The technical scheme is as follows:
the semiconductor packaging structure comprises a substrate, a conductive assembly, a plurality of chips and a heat dissipation shell, wherein the conductive assembly is fixed on the surface of the substrate, the conductive assembly is a polyhedron, the conductive assembly is provided with a circuit layer electrically connected with the substrate, each surface of the conductive assembly is provided with a connection point electrically connected with the circuit layer, the functional surfaces of the chips are in one-to-one correspondence with each surface of the conductive assembly and are electrically connected with the connection points, and the circuit layer is used for electrically connecting the substrate with the chips; the heat dissipation shell is of a cylindrical structure with one end open, one end of the opening of the heat dissipation shell is fixed on the surface of the substrate, the conductive component and the chips are located inside the heat dissipation shell, and the inner side wall of the heat dissipation shell is matched with the chips so that the chips are attached to the inner side walls of the heat dissipation shell.
Through adopting above-mentioned technical scheme, integrate a plurality of chips on the functional surface of the polyhedron conductive component that has a plurality of surfaces, conductive component surface is provided with the circuit layer with base plate electric connection, and realize electric connection through tie point and chip, thereby only need correspond the dress chip at the surface of this conductive component, can realize the multicore piece encapsulation, can promote chip encapsulation efficiency effectively, set up conductive component and a plurality of chips in the tubular heat dissipation shell, and the chip laminating is in each inside wall of heat dissipation shell, make the laminating area increase of chip and heat dissipation shell, with this heat dispersion who promotes semiconductor packaging structure, simultaneously through the chip, conductive component and heat dissipation shell's tight fit, make semiconductor packaging structure compact size less, can adapt to more application scenarios.
Optionally, the conductive component is any one of a cube, a cuboid or a polygon prism.
Through adopting above-mentioned technical scheme, when conductive component shape is square, cuboid or polygon, conductive component can be as far as possible paste the dress chip on conductive component for can paste more chips in a semiconductor packaging structure, with the promotion encapsulation effect.
Optionally, the connection point is provided with a metal bump, and the metal bump is electrically connected with the functional surface of the chip.
Through adopting above-mentioned technical scheme, through setting up metal lug on the tie point to realize the electrical property of circuit layer and draw forth, avoid appearing the circuit layer poor contact of chip function layer and conductive component as far as possible when mounting the chip.
Optionally, the circuit layer penetrates through the conductive component or the circuit layer is disposed on the surface of the conductive component.
Through adopting above-mentioned technical scheme, can run through conductive component with the circuit layer to make conductive channel lead to form inside the electrical component, be convenient for chip and conductive component electric connection, the circuit layer also can set up in conductive component surface simultaneously, can shorten conductive path greatly, reduces the influence to signal transmission.
Optionally, the outer side wall of the heat dissipation shell is provided with heat dissipation fins.
Through adopting above-mentioned technical scheme, heat that produces the chip through the heat dissipation shell is outside conduction, and heat is conducted to radiator fin through the heat dissipation shell to further promote the area of heat dissipation shell and air contact, and then promote the radiating effect of heat dissipation shell.
Optionally, the heat dissipation shell opening one end is sealed with the base plate.
Through adopting above-mentioned technical scheme, seal between heat dissipation shell and the base plate, avoid water oxygen to get into inside the heat dissipation shell as far as possible to effectively promote packaging structure's airtight performance, so that packaging structure can adapt to multiple environment.
Optionally, the metal bump is any one of tin solder, silver solder or gold-tin alloy solder.
A method of fabricating a semiconductor package, comprising:
providing a substrate;
manufacturing a conductive component with a circuit layer, wherein each surface of the conductive component is provided with a connection point electrically connected with the circuit layer, and the conductive component is fixed on the surface of the substrate so as to electrically connect the substrate with the conductive component;
arranging chips on each surface of the conductive component to electrically connect the chips with the conductive component; and
and providing a heat dissipation shell, wherein the heat dissipation shell is in a cylindrical shape with one end open, and is fixed on the surface of the substrate, so that the heat dissipation shell wraps the conductive assembly and the chips to form a semiconductor packaging structure.
Through adopting above-mentioned technical scheme, make electrically conductive subassembly in advance to make electrically conductive subassembly each surface have circuit layer and the tie point that can electrically conduct, only need paste the chip dress in electrically conductive subassembly surface, can realize the chip installation, package up chip and electrically conductive subassembly with the radiating shell and can accomplish packaging structure, the packaging structure of this application can encapsulate a plurality of chips integrated, and the integrated level is high, and process flow is simple.
Optionally, the manufacturing the conductive component with the circuit layer specifically includes:
and manufacturing a plurality of unit layers in a laminated manner, wherein conductive circuits are arranged on the surface of the unit layers, a plurality of the conductive circuits are electrically connected, and the unit layers are sequentially laminated to form a conductive assembly.
Through adopting above-mentioned technical scheme, by the conductive component that the unit range upon range of constitution was made, can conveniently electroplate copper deposition and form conductive path in conductive component is inside, the chip of being convenient for and conductive component electric connection also can form conductive path on conductive component surface simultaneously, can shorten conductive path greatly, reduces the influence to signal transmission.
Optionally, the surface of the unit layer is provided with a conductive circuit, which specifically comprises:
providing a photosensitive dry film or photosensitive ink;
covering the photosensitive dry film or the photosensitive ink on the unit layer;
exposing and developing the photosensitive dry film or the photosensitive ink to form a preset conductive circuit;
electroplating copper deposition in the preset conductive circuit to form the conductive circuit; and
and carrying out film stripping treatment on the photosensitive dry film or the photosensitive ink, and covering the unit layer with a dielectric material to obtain a circuit layer.
By adopting the technical scheme, the unit layer can be formed rapidly only by forming the preset conductive circuit on the surface of the unit layer, electroplating copper deposition on the preset conductive circuit to form the conductive circuit and covering the conductive circuit with the dielectric material, and the process flow is simple and convenient for production.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the multiple chips are integrated on the functional surface of the polyhedral conductive component with multiple surfaces, the surface of the conductive component is provided with a circuit layer electrically connected with the substrate and is electrically connected with the chips through connection points, so that the multi-chip package can be realized only by correspondingly attaching the chips on the surface of the conductive component, the packaging efficiency of the chips can be effectively improved, the conductive component and the multiple chips are arranged in the cylindrical heat dissipation shell, and the chips are attached to the inner side walls of the heat dissipation shell, so that the attaching area of the chips and the heat dissipation shell is increased, the heat dissipation performance of the semiconductor package structure is improved, and meanwhile, the semiconductor package structure is compact in size and smaller by the close fit of the chips, the conductive component and the heat dissipation shell, and can adapt to more application scenes;
2. the conductive assembly is manufactured in advance, a circuit layer and a connecting point which can conduct electricity exist on the surface of the conductive assembly, chip installation can be achieved only by mounting the chip on the surface of the conductive assembly, and the heat dissipation shell wraps the chip and the conductive assembly to complete the packaging structure.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor package structure provided in the present application;
FIG. 2 is a cross-sectional view taken in the direction A-A' of FIG. 1;
FIG. 3 is a schematic diagram of the conductive assembly of FIG. 2;
FIG. 4 is a cross-sectional view of the conductive assembly B-B' of FIG. 3;
fig. 5 is a cross-sectional view of the conductive member C-C' of fig. 3.
Reference numerals illustrate: 1. a substrate; 2. a conductive assembly; 21. a circuit layer; 211. a connection point; 212. a conductive line; 22. a metal bump; 3. a chip; 4. a heat dissipation housing; 41. and the heat dissipation fins.
Detailed Description
A further detailed description of a semiconductor package structure is provided herein below with reference to fig. 1-5. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate a relative positional relationship, which changes accordingly when the absolute position of the object to be described changes.
Referring to fig. 1 and 2, an embodiment of the present application provides a semiconductor package structure including a substrate 1, a conductive assembly 2, a plurality of chips 3, and a heat dissipation case 4.
The conductive component 2 is fixed on the surface of the substrate 1, the conductive component 2 is a polyhedron, wherein the conductive component 2 can be any one of a cube, a cuboid or a polygon, and the conductive component 2 can be attached with chips 3 on the conductive component 2 as much as possible by adopting the shape, so that more chips 3 can be attached in one semiconductor packaging structure, and the packaging effect is improved.
The conductive component 2 is provided with a circuit layer 21 electrically connected with the substrate 1, and the circuit layer 21 is used for electrically connecting the substrate 1 and the chip 3. In one example, the circuit layer 21 may penetrate the conductive component 2 or the circuit layer 21 may be disposed on the surface of the conductive component 2, and the circuit layer 21 may penetrate the conductive component 2, so that the conductive channel is formed inside the conductive component, so that the chip 3 and the conductive component 2 are electrically connected, and meanwhile, the circuit layer 21 may also be disposed on the surface of the conductive component 2, so that the conductive path may be greatly shortened, and the influence on signal transmission is reduced. The circuit layer 21 disposed on the surface of the conductive component 2 may be formed by electrically connecting a plurality of special-shaped bonding wires.
As shown in fig. 3, each surface of the conductive component 2 is provided with a connection point 211 electrically connected to the circuit layer 21, and the functional surfaces of the chips 3 are in one-to-one correspondence with each surface of the conductive component 2 and are electrically connected to the connection point 211. Wherein. The material of the conductive component 2 is a dielectric material of a mechanical mixture of epoxy resin and silicon dioxide, ABF or polyimide. The conductive element 2 made of dielectric material can perform an insulating function so that the lines between the line layers 21 do not interfere with each other.
The connection point 211 is provided with a metal bump 22, and the metal bump 22 is electrically connected with the functional surface of the chip 3, so as to realize the electrical extraction of the circuit layer 21, and avoid bad contact between the functional layer of the chip 3 and the circuit layer 21 of the conductive component 2 when the chip 3 is attached. The metal bump 22 may be a metal ball structure, and the material of the metal bump 22 is any one of tin solder, silver solder or gold-tin alloy solder.
The heat dissipation shell 4 is one end open-ended tubular structure, and heat dissipation shell 4 open-ended one end is fixed in base plate 1 surface, and conductive component 2 and a plurality of chip 3 all are located heat dissipation shell 4 inside, and heat dissipation shell 4 inside wall and a plurality of chip 3 looks adaptation to make each chip 3 laminating in each inside wall of casing.
The outer side wall of the heat dissipation shell 4 is provided with heat dissipation fins 41, the heat dissipation shell 4 conducts the heat generated by the chip 3 to the outside, and the heat is conducted to the heat dissipation fins 41 through the heat dissipation shell 4, so that the contact area between the heat dissipation shell 4 and the air is further increased, and the heat dissipation effect of the heat dissipation shell 4 is further improved.
Specifically, in practical application, the heat dissipation case 4 may be any one of a metal square tube or a soaking square tube. A graphite film or a graphene film can be paved on the outer side wall of the heat dissipation shell 4, and heat generated by the chip 3 is firstly transferred to the graphite film or the graphene film through the heat dissipation shell 4 and then transferred to the space through the heat dissipation fins 41, so that a high-efficiency heat dissipation system is formed.
The heat dissipation shell 4 is sealed between the open end and the substrate 1, so that water and oxygen are prevented from entering the heat dissipation shell 4 as much as possible, and the sealing performance of the packaging structure is effectively improved, so that the packaging structure can adapt to various environments.
The chip 3 is integrated on the functional surface of the polyhedral conductive component 2 with a plurality of surfaces, the circuit layer 21 electrically connected with the substrate 1 is arranged on the surface of the conductive component 2 and is electrically connected with the chip 3 through the connection point 211, so that the multi-chip 3 package can be realized only by correspondingly attaching the chip 3 on the surface of the conductive component 2, the package efficiency of the chip 3 can be effectively improved, the conductive component 2 and the chip 3 are arranged in the cylindrical heat dissipation shell 4, the chip 3 is attached to each inner side wall of the heat dissipation shell 4, the attachment area of the chip 3 and the heat dissipation shell 4 is increased, the heat dissipation performance of the semiconductor package structure is improved, and meanwhile, the semiconductor package structure is compact in size and smaller by tightly matching the chip 3, and can adapt to more application scenes.
Based on the surface acoustic wave filter, the application also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps:
in step S110, a substrate 1 is provided.
In step S120, the conductive component 2 having the circuit layer 21 is manufactured, each surface of the conductive component 2 has a connection point 211 electrically connected to the circuit layer 21, and the conductive component 2 is fixed on the surface of the substrate 1, so that the substrate 1 is electrically connected to the conductive component 2.
In this step, a plurality of unit layers can be manufactured through lamination, the surface of the unit layer is provided with a conductive circuit 212, the plurality of conductive circuits 212 are electrically connected, and the plurality of unit layers are sequentially laminated to form a conductive assembly 2, and the conductive assembly 2 manufactured through lamination of the unit layer can facilitate electroplating copper deposition to form a conductive channel inside the conductive assembly 2, so that the chip 3 and the conductive assembly 2 are electrically connected, and meanwhile, the conductive channel can also be formed on the surface of the conductive assembly 2, so that a conductive path can be greatly shortened, and the influence on signal transmission is reduced.
Referring to fig. 4, the circuit layer 21 on the surface of the conductive component 2 may be perforated by a photosensitive dry film or a photosensitive ink, so that the holes penetrate through the conductive component 2, and plated with copper to form the conductive circuits 212, so that the metal bumps 22 on the surface of the conductive component 2 can be electrically connected with the substrate.
Referring to fig. 5, the circuit layer 21 located at the side of the conductive component 2 may be formed by only laying the formed conductive circuit 212 on the surface of the conductive component 2, and the conductive circuit 212 may be formed by plating copper deposition on the corresponding unit layer, or by electrically connecting the conductive circuit 212 with a special-shaped bonding wire, so that multiple surfaces of the conductive component 2 may be electrically connected in the above manner, and further more chips may be attached.
In step S130, the chips 3 are disposed on the respective surfaces of the conductive elements 2 to electrically connect the chips 3 with the conductive elements 2.
In this step, the chip 3 is connected to the metal bumps 22 disposed on the connection points 211 on the surfaces of the conductive elements 2, so that the chip 3 is electrically connected to the substrate 1 through the conductive elements 2.
In step S140, a heat dissipation case 4 is provided, the heat dissipation case 4 is in a cylindrical shape with an opening at one end, and the heat dissipation case 4 is fixed on the surface of the substrate 1, so that the heat dissipation case 4 wraps the conductive component 2 and the plurality of chips 3 to form a semiconductor package structure.
In this step, a graphite film or a graphene film may be laid on the outer side wall of the heat dissipation case 4, or the heat dissipation fins 41 may be directly provided on the outer side wall of the heat dissipation case 4.
The conductive component 2 is manufactured in advance, the circuit layer 21 and the connection point 211 which can conduct electricity exist on the surface of the conductive component 2, the chip 3 can be installed only by mounting the chip 3 on the surface of the conductive component 2, the heat dissipation shell 4 wraps the chip 3 and the conductive component 2, and the packaging structure can be used for packaging and integrating a plurality of chips 3.
Wherein the method for manufacturing the conductive component 2 with the circuit layer 21 comprises the following steps:
step S121, providing a photosensitive dry film or photosensitive ink.
In step S122, the photosensitive dry film or the photosensitive ink is covered on the unit layer.
And step S123, exposing and developing the photosensitive dry film or photosensitive ink to form a preset conductive circuit.
In step S124, copper is plated on the predetermined conductive trace to form the conductive trace 212.
In this step, the circuit layer can be made by punching a photosensitive dry film or photosensitive ink and plating copper deposition, so that the influence of the laser punching process on the circuit can be reduced, or the conductive circuit 212 is formed by adopting a plurality of special-shaped bonding wires for electric connection, and the conductive circuit 212 is encapsulated by using a dielectric material, so that the circuit layer 21 is obtained.
In step S125, the photosensitive dry film or photosensitive ink is subjected to film stripping treatment, and the unit layer is covered with a dielectric material, so as to obtain the circuit layer 21.
The cell layer can be formed rapidly only by forming a preset conductive line on the surface of the cell layer, electroplating copper deposition on the preset conductive line to form a conductive line 212 and covering the conductive line with a dielectric material, and the process flow is simple and convenient for production.
The embodiments of the present invention are all preferred embodiments of the present application, and are not intended to limit the scope of the present application in this way, therefore: all equivalent changes in structure, shape and principle of this application should be covered in the protection scope of this application.
Claims (10)
1. A semiconductor package structure, comprising: the circuit board comprises a substrate (1), a conductive component (2), a plurality of chips (3) and a heat dissipation shell (4), wherein the conductive component (2) is fixed on the surface of the substrate (1), the conductive component (2) is a polyhedron, the conductive component (2) is provided with circuit layers (21) electrically connected with the substrate (1), each surface of the conductive component (2) is provided with connection points electrically connected with the circuit layers (21), the functional surfaces of each chip (3) are in one-to-one correspondence with each surface of the conductive component (2) and are electrically connected with the connection points, and the circuit layers (21) are used for electrically connecting the substrate (1) with the chips (3); the heat dissipation shell (4) is of a cylindrical structure with one end open, one end of the opening of the heat dissipation shell (4) is fixed on the surface of the substrate (1), the conductive component (2) and the chips (3) are located inside the heat dissipation shell (4), and the inner side wall of the heat dissipation shell (4) is matched with the chips (3) so that the chips (3) are attached to the inner side walls of the heat dissipation shell (4).
2. The semiconductor package according to claim 1, wherein: the conductive component (2) is any one of a cube, a cuboid or a polygon prism.
3. The semiconductor package according to claim 1, wherein: the connection point (211) is provided with a metal bump (22), and the metal bump (22) is electrically connected with the functional surface of the chip (3).
4. A semiconductor package according to claim 3, wherein: the circuit layer (21) penetrates through the conductive component (2) or the circuit layer (21) is arranged on the surface of the conductive component (2).
5. The semiconductor package according to claim 1, wherein: and radiating fins (41) are arranged on the outer side wall of the radiating shell (4).
6. The semiconductor package according to claim 1, wherein: the opening end of the heat dissipation shell (4) and the substrate (1) are arranged in a sealing mode.
7. A semiconductor package according to claim 3, wherein: the metal bump (22) is any one of tin solder, silver solder or gold-tin alloy solder.
8. A method of manufacturing a semiconductor package, comprising the steps of:
providing a substrate (1);
manufacturing a conductive component (2) with a circuit layer (21), wherein each surface of the conductive component (2) is provided with a connection point (211) electrically connected with the circuit layer (21), and the conductive component (2) is fixed on the surface of the substrate (1) so that the substrate (1) is electrically connected with the conductive component (2);
arranging chips (3) on each surface of the conductive component (2) so that the chips (3) are electrically connected with the conductive component (2); the method comprises the steps of,
the method comprises the steps of providing a heat dissipation shell (4), wherein the heat dissipation shell (4) is in a cylindrical shape with one end open, fixing the heat dissipation shell (4) on the surface of a substrate (1), and enabling the heat dissipation shell (4) to wrap the conductive component (2) and the chips (3) to form a semiconductor packaging structure.
9. The method according to claim 8, characterized in that the production of the electrically conductive component (2) with the wiring layer (21) is in particular:
and manufacturing a plurality of unit layers in a laminated manner, wherein conductive circuits (212) are arranged on the surface of the unit layers, the conductive circuits (212) are electrically connected, and the unit layers are sequentially laminated to form a conductive assembly (2).
10. The method according to claim 9, wherein: the surface of the unit layer is provided with a conductive circuit (212), specifically:
providing a photosensitive dry film or photosensitive ink;
covering the photosensitive dry film or the photosensitive ink on the unit layer;
exposing and developing the photosensitive dry film or the photosensitive ink to form a preset conductive circuit;
electroplating copper deposition in the preset conductive line to form the conductive line (212); and
and (3) carrying out film stripping treatment on the photosensitive dry film or the photosensitive ink, and covering the unit layer with a dielectric material to obtain a circuit layer (21).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310019662.2A CN116314065A (en) | 2023-01-06 | 2023-01-06 | Semiconductor package structure including heat spreader and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310019662.2A CN116314065A (en) | 2023-01-06 | 2023-01-06 | Semiconductor package structure including heat spreader and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116314065A true CN116314065A (en) | 2023-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310019662.2A Pending CN116314065A (en) | 2023-01-06 | 2023-01-06 | Semiconductor package structure including heat spreader and method of manufacturing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116544202A (en) * | 2023-07-06 | 2023-08-04 | 广东汇芯半导体有限公司 | High-integration superconductive heat semiconductor circuit module and manufacturing method |
| CN117374026A (en) * | 2023-12-08 | 2024-01-09 | 深圳辰达半导体有限公司 | Car-standard MOS tube with low on-resistance and preparation method thereof |
-
2023
- 2023-01-06 CN CN202310019662.2A patent/CN116314065A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116544202A (en) * | 2023-07-06 | 2023-08-04 | 广东汇芯半导体有限公司 | High-integration superconductive heat semiconductor circuit module and manufacturing method |
| CN117374026A (en) * | 2023-12-08 | 2024-01-09 | 深圳辰达半导体有限公司 | Car-standard MOS tube with low on-resistance and preparation method thereof |
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