CN113380613A - Wafer thinning processing method - Google Patents
Wafer thinning processing method Download PDFInfo
- Publication number
- CN113380613A CN113380613A CN202110604117.0A CN202110604117A CN113380613A CN 113380613 A CN113380613 A CN 113380613A CN 202110604117 A CN202110604117 A CN 202110604117A CN 113380613 A CN113380613 A CN 113380613A
- Authority
- CN
- China
- Prior art keywords
- wafer
- grinding
- film layer
- front surface
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000003292 glue Substances 0.000 claims abstract description 24
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims description 35
- 239000002313 adhesive film Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 150
- 238000010586 diagram Methods 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
Abstract
The embodiment of the invention relates to the field of semiconductor manufacturing, and discloses a wafer thinning processing method. The invention discloses a wafer thinning processing method, which comprises the following steps of firstly attaching a grinding glue film layer on the front side of a wafer, adsorbing the front side of the wafer attached with the grinding glue film layer on a grinding table top, enabling the outer diameter of the grinding table top to be matched with the outer diameter of the front side of the wafer, then grinding the back side of the wafer to enable the wafer to reach the final thickness, then attaching the glue film layer on the back side of the ground wafer, attaching an iron ring on the glue film layer, finally fixing the iron ring on a wafer frame, and removing the grinding glue film layer on the front side of the wafer. According to the wafer thinning processing method, the diameter of the grinding table surface is equivalent to the outer diameter of the front surface of the wafer, the metal layer of the front surface of the wafer is completely adsorbed on the grinding table surface when the wafer is ground, the problems of breakage and surface blackening when the wafer is ground are solved, the abnormal processing time of a machine table is shortened, and the utilization rate of the machine table is improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a wafer thinning processing method.
Background
Integrated circuit chips are continuously developed towards high density, light weight and thin shape, and in order to meet the requirements, wafers need to be thinned and cut. The wafer thinning technology is a key technology for packaging the stacked chips, and the number of stacked layers of the chips is continuously increased, so that the thickness of the chips is gradually thinned, and the capacity of the chips is increased more and more.
The wafer comprises a metal layer on the front side and a silicon layer on the back side, and steps are generated on the edge of the metal layer on the front side of the wafer in the process of machining and forming the wafer.
When a wafer is placed on a grinding table top to be ground and thinned in the prior art, the vacuum of the grinding table top is low due to the steps at the edge of the wafer, and the risk of wafer breakage during grinding is caused.
Disclosure of Invention
The present invention is directed to a wafer thinning method to solve the above problems in the background art.
The embodiment of the invention provides a wafer thinning processing method, which comprises the following steps:
s10 providing a wafer, the wafer comprising: the metal layer on the front side and the silicon layer on the back side, and steps are arranged on the edges of the metal layer;
s20, attaching a grinding glue film layer on the front surface of the wafer;
s30, adsorbing the front surface of the wafer attached with the grinding glue film layer on the grinding table surface, wherein the outer diameter of the grinding table surface is matched with the outer diameter of the front surface of the wafer;
s40, grinding the back of the wafer to make the wafer reach the final thickness;
s50 attaching a film layer to the back of the ground wafer and attaching an iron ring to the film layer;
s60, fixing the iron ring on the wafer frame, and removing the grinding glue film layer on the front surface of the wafer.
Based on the scheme, the wafer thinning processing method disclosed by the invention is characterized in that the wafer thinning processing is improved, the grinding glue film layer is firstly attached to the front side of the wafer, the front side of the wafer is adsorbed on the grinding table top, the outer diameter of the grinding table top is matched with that of the front side of the wafer, then the back side of the wafer is ground, the wafer is made to reach the final required thickness, and finally the grinding glue film layer on the front side of the wafer is removed. According to the wafer thinning processing method, the diameter of the grinding table top is equivalent to the outer diameter of the metal layer on the front side of the wafer, the metal layer of the wafer is completely adsorbed on the grinding table top when the wafer is ground, the problems of breakage of the wafer during grinding and surface scorching during grinding caused by wafer steps are solved, the packaging yield of chips is improved, the abnormal processing time of a machine table due to vacuum alarming is reduced, and the utilization rate of the machine table is improved.
In a possible solution, in step S40, the method specifically includes:
s41, roughly grinding the back side of the wafer attached with the grinding glue film layer until the thickness of the wafer reaches the final wafer thickness of +60 μm;
s42, finely grinding the back surface of the roughly ground wafer until the thickness of the wafer reaches the final wafer thickness of +2 μm;
s43 polishing the back side of the wafer after finish grinding until the thickness of the wafer reaches the final wafer thickness.
In one possible solution, in step S20, the polishing adhesive film layer is a UV adhesive film.
In one possible solution, in step S50, the adhesive film layer is a DAF adhesive film.
In one possible solution, in step S10, a wafer is provided, and the front surface of the wafer is provided with a plurality of longitudinal pre-cuts and a plurality of transverse pre-cuts, and the plurality of longitudinal pre-cuts and the plurality of transverse pre-cuts are staggered in a # -shape.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic view of a wafer according to the present invention;
FIG. 2 is a schematic diagram illustrating a wafer polishing process according to the background art of the present invention;
FIG. 3 is a process flow diagram of a wafer thinning method according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a wafer according to an embodiment of the invention;
FIG. 5 is a diagram illustrating a wafer with a polishing pad layer attached thereon according to an embodiment of the present invention;
FIG. 6 is a schematic view of the wafer placement during polishing according to an embodiment of the present invention;
FIG. 7 is a schematic view illustrating a state of wafer polishing according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a wafer after being polished and thinned according to an embodiment of the present invention;
fig. 9 is a schematic view of a wafer with an adhesive film layer and an iron ring attached thereon according to an embodiment of the invention.
Reference numbers in the figures:
100. a wafer; 110. a metal layer; 120. a silicon layer; 200. grinding the adhesive film layer; 300. grinding the table top; 400. a glue film layer; 500. an iron ring.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," and the like are used in the indicated orientations and positional relationships based on the drawings for convenience in describing and simplifying the description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention.
In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication connection; either directly or indirectly through intervening media, either internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
As described in the background of the present application, in the conventional wafer, an edge trimming (edge trim) process is used during the process of forming, as shown in fig. 1, so that a step with a width of about 2mm-3mm and a depth of about 20 μm is formed at the edge of the metal layer on the front surface of the wafer.
The inventor of the present application finds that when a wafer with steps is placed on a grinding table for grinding and thinning, as shown in fig. 2, due to the existence of the steps, the vacuum between the edge steps of the wafer and the grinding table is low due to the leakage of gaps, so that the wafer has a risk of breakage during grinding, and the surface of the wafer is scorched during grinding
In order to solve the above problems, the inventor of the present application proposes a technical solution of the present application, and specific embodiments are as follows:
fig. 3 is a process flow diagram of a wafer thinning method in an embodiment of the present invention, fig. 4 is a schematic cross-sectional view of a wafer in an embodiment of the present invention, fig. 5 is a schematic view of a wafer with a polishing glue film layer attached thereto in an embodiment of the present invention, fig. 6 is a schematic view of a wafer being placed during polishing in an embodiment of the present invention, fig. 7 is a schematic view of a state of polishing the wafer in an embodiment of the present invention, fig. 8 is a schematic view of the wafer after being polished and thinned in an embodiment of the present invention, and fig. 9 is a schematic view of the wafer with the glue film layer and an iron ring attached thereto in an embodiment of the present invention. As shown in fig. 3 to 9, the wafer thinning method in the embodiment of the present invention includes the following steps:
s10 providing a wafer, the wafer comprising: the metal layer on the front side and the silicon layer on the back side, and steps are arranged on the edges of the metal layer.
Specifically, as shown in fig. 1, 3 and 4, the wafer 100 in this embodiment includes a metal layer 110 on the front surface and a silicon layer 120 on the back surface. In the processing process of the wafer 100, a step with a width of about 2mm-3mm and a depth of about 20 μm is formed at the edge of the metal layer 110 on the front surface, and the step makes the outer diameter of the metal layer 110 on the front surface of the wafer 100 smaller than the outer diameter of the silicon layer 120 on the back surface.
S20, a polishing glue film layer is attached to the front surface of the wafer.
As shown in fig. 5, the polishing adhesive film layer 200 is attached to the outer surface of the metal layer 110 on the front surface of the wafer 100, and the polishing adhesive film layer has a certain viscosity, and is attached to the metal layer 110 on the front surface of the wafer 100 to protect the metal layer 110 on the front surface of the wafer 100, so as to prevent the wafer 100 from damaging the functional region on the front surface of the wafer 100 in the subsequent polishing and thinning processes. When adhering, it is necessary to ensure that the polishing adhesive film layer 200 is tightly adhered to the metal layer 110, and no air bubbles are generated between the polishing adhesive film layer 200 and the metal layer 110.
S30, the front surface of the wafer with the grinding glue film layer is absorbed on the grinding table surface, and the outer diameter of the grinding table surface is matched with the outer diameter of the front surface of the wafer.
Specifically, as shown in fig. 6 and 7, the front surface of the wafer 100 with the polishing adhesive film layer 200 attached thereon is adsorbed on the polishing table 300, that is, one surface of the polishing adhesive film layer 200 is placed on the polishing table 300, and the outer diameter of the polishing table 300 is adapted to (corresponding to) the outer diameter of the step bottom of the metal layer 110 on the front surface of the wafer 100, the polishing table 300 is provided with a vacuum adsorption system, so that the metal layer 110 on the front surface of the wafer 100 is completely contacted with the polishing table 300, the metal layer 110 of the wafer 100 is completely adsorbed on the polishing table 300, and no gap exists between the metal layer 110 and the polishing table 300.
S40, the back side of the wafer is polished to a final thickness.
As shown in fig. 8, the silicon layer 120 on the back surface of the wafer 100 is polished by a full-automatic thinning machine so that the wafer 100 is gradually thinned until the final thickness of the wafer 100 (chip) is reached.
S50 attaching a film layer to the back surface of the polished wafer, and attaching an iron ring to the film layer.
As shown in fig. 9, after the wafer 100 is ground and thinned to a final thickness, the adhesive film layer 400 is attached to the outer surface of the silicon layer 120 on the back surface of the wafer 100, and when the adhesive film layer 400 is attached to the silicon layer 120, the adhesive film layer 400 is tightly attached to the silicon layer 120 without bubbles and impurities, and then the iron ring 500 is attached to the adhesive film layer 400, so that the wafer 100 is fixed on the iron ring 500.
S60, fixing the iron ring on the wafer frame, and removing the grinding glue film layer on the front surface of the wafer.
Specifically, the wafer 100 is fixed on the wafer holder by the iron ring 500, and then the polishing adhesive film layer 200 on the front surface of the wafer is removed. Since the polishing adhesive film layer 200 has a certain viscosity with the front surface of the wafer 100, when the polishing adhesive film layer 200 is removed, the polishing adhesive film layer needs to be lifted up slowly from one side of the polishing adhesive film layer 200, so as to avoid damage to the wafer.
And finally, cutting the front surface of the wafer through laser to obtain the required chip.
It is obvious from the above description that, in the method for thinning a wafer according to this embodiment, the wafer thinning process is improved, the grinding glue film layer is firstly attached to the front surface of the wafer, the front surface of the wafer is adsorbed on the grinding table, the outer diameter of the grinding table is adapted (equal) to the outer diameter of the front surface of the wafer, then the back surface of the wafer is ground, the wafer is made to reach the final required thickness, and finally the grinding glue film layer on the front surface of the wafer is removed. According to the wafer thinning processing method, the outer diameter of the grinding table top is equivalent to that of the metal layer on the front side of the wafer, the metal layer of the wafer is completely adsorbed on the grinding table top when the wafer is ground, vacuum leakage caused by edge steps is avoided, the problems of breakage of the wafer during grinding and surface scorching during grinding caused by the wafer steps are solved, the packaging yield of chips is improved, the abnormal processing time of a machine table due to vacuum alarm is shortened, and the utilization rate of the machine table is improved.
Optionally, in step S40, the wafer thinning method in this embodiment specifically includes:
s41, rough grinding the back surface of the wafer with the polishing glue film layer until the thickness of the wafer reaches the final wafer thickness +60 μm, that is, the thickness of the wafer is roughly ground to have a margin of about 60 μm.
And S42, finely grinding the back surface of the wafer after rough grinding until the thickness of the wafer reaches the final wafer thickness of +2 μm, namely, the wafer is finely ground until the thickness of the wafer has a margin of about 2 μm.
S43 polishing the back surface of the wafer after finish grinding until the thickness of the wafer reaches the final wafer thickness, i.e. the wafer is made to reach the thickness of the final size by polishing.
Through the processes of coarse grinding, fine grinding and polishing, the wafer reaches the thickness of the final size, the stress in the process of grinding and thinning the wafer is reduced, and the quality of the wafer is improved.
Optionally, in the wafer thinning method in this embodiment, in step S20, the polishing adhesive film layer attached to the front surface of the wafer is a UV adhesive film.
Adopt the UV glued membrane, can carry out UV (ultraviolet) to the UV membrane through the ultraviolet lamp when getting rid of and shine, the UV glued membrane after shining loses adhesive force, conveniently grinds the glued membrane layer and gets rid of from the metal level.
Optionally, in the wafer thinning method in this embodiment, in step S50, the adhesive film layer attached to the back of the wafer is a DAF adhesive film.
Optionally, in the method for thinning a wafer in this embodiment, in step S10, a wafer is provided, and the front surface of the wafer is provided with a plurality of longitudinal pre-cuts and a plurality of transverse pre-cuts, and the plurality of longitudinal pre-cuts and the plurality of transverse pre-cuts are staggered in a # -shape.
The metal layer 110 on the front surface of the wafer 100 is provided with a plurality of longitudinal pre-cut marks and a plurality of transverse pre-cut marks, the longitudinal pre-cut marks are arranged on the wafer 100 at equal intervals, the transverse pre-cut marks are arranged on the wafer 100 at equal intervals, the longitudinal pre-cut marks and the transverse pre-cut marks are arranged in a staggered manner in a # -shape, and a plurality of uniformly distributed square chips to be separated are formed on the front surface of the wafer 100. And grinding the thinned wafer, and continuously cutting the wafer along the longitudinal pre-cut mark and the transverse pre-cut mark of the wafer 100 by laser to obtain mutually separated chips, so that the subsequent cutting processing of the wafer is facilitated.
In the present invention, unless otherwise explicitly specified or limited, the first feature "on" or "under" the second feature may be directly contacting the first feature and the second feature or indirectly contacting the first feature and the second feature through an intermediate.
Also, a first feature "on," "above," and "over" a second feature may mean that the first feature is directly above or obliquely above the second feature, or that only the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lower level than the second feature.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A wafer thinning processing method is characterized by comprising the following steps:
s10 providing a wafer, the wafer comprising: the metal layer on the front side and the silicon layer on the back side, and steps are arranged on the edges of the metal layer;
s20, attaching a grinding glue film layer on the front surface of the wafer;
s30, adsorbing the front surface of the wafer attached with the grinding glue film layer on the grinding table surface, wherein the outer diameter of the grinding table surface is matched with the outer diameter of the front surface of the wafer;
s40, grinding the back of the wafer to make the wafer reach the final thickness;
s50 attaching a film layer to the back of the ground wafer and attaching an iron ring to the film layer;
s60, fixing the iron ring on the wafer frame, and removing the grinding glue film layer on the front surface of the wafer.
2. The wafer thinning method according to claim 1, wherein in step S40, the method specifically comprises:
s41, roughly grinding the back side of the wafer attached with the grinding glue film layer until the thickness of the wafer reaches the final wafer thickness of +60 μm;
s42, finely grinding the back surface of the roughly ground wafer until the thickness of the wafer reaches the final wafer thickness of +2 μm;
s43 polishing the back side of the wafer after finish grinding until the thickness of the wafer reaches the final wafer thickness.
3. The wafer thinning processing method of claim 1, wherein in step S20, the polishing adhesive film layer is a UV adhesive film.
4. The wafer thinning method according to claim 1, wherein in step S50, the adhesive film layer is a DAF adhesive film.
5. The wafer thinning processing method according to claim 1, wherein in step S10, a wafer is provided, and the front surface of the wafer is provided with a plurality of longitudinal pre-cuts and a plurality of transverse pre-cuts, and the plurality of longitudinal pre-cuts and the plurality of transverse pre-cuts are staggered in a # -shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110604117.0A CN113380613A (en) | 2021-05-31 | 2021-05-31 | Wafer thinning processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110604117.0A CN113380613A (en) | 2021-05-31 | 2021-05-31 | Wafer thinning processing method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113380613A true CN113380613A (en) | 2021-09-10 |
Family
ID=77575029
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110604117.0A Pending CN113380613A (en) | 2021-05-31 | 2021-05-31 | Wafer thinning processing method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113380613A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117524870A (en) * | 2023-12-29 | 2024-02-06 | 物元半导体技术(青岛)有限公司 | Wafer processing method and wafer |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW556279B (en) * | 1999-12-01 | 2003-10-01 | Sharp Kk | Method of thinning semiconductor wafer capable of preventing its front from being contaminated and back grinding device for semiconductor wafers |
TW561542B (en) * | 2002-10-18 | 2003-11-11 | Chipmos Technologies Bermuda | Process and apparatus for grinding a wafer backside |
JP2005288569A (en) * | 2004-03-31 | 2005-10-20 | Shin Nippon Koki Co Ltd | Double-side polishing device and method |
TW201308411A (en) * | 2011-08-12 | 2013-02-16 | Powertech Technology Inc | Wafer dicing method to avoid thinned wafer breaking |
CN109559983A (en) * | 2018-11-16 | 2019-04-02 | 紫光宏茂微电子(上海)有限公司 | The cutting method of wafer |
CN110729186A (en) * | 2019-10-24 | 2020-01-24 | 东莞记忆存储科技有限公司 | Processing method for wafer cutting and separating |
CN111489966A (en) * | 2020-06-15 | 2020-08-04 | 紫光宏茂微电子(上海)有限公司 | Method for cutting wafer |
CN111564367A (en) * | 2020-05-21 | 2020-08-21 | 江苏汇成光电有限公司 | Method for processing wafer cracking abnormity before wafer grinding |
-
2021
- 2021-05-31 CN CN202110604117.0A patent/CN113380613A/en active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW556279B (en) * | 1999-12-01 | 2003-10-01 | Sharp Kk | Method of thinning semiconductor wafer capable of preventing its front from being contaminated and back grinding device for semiconductor wafers |
TW561542B (en) * | 2002-10-18 | 2003-11-11 | Chipmos Technologies Bermuda | Process and apparatus for grinding a wafer backside |
JP2005288569A (en) * | 2004-03-31 | 2005-10-20 | Shin Nippon Koki Co Ltd | Double-side polishing device and method |
TW201308411A (en) * | 2011-08-12 | 2013-02-16 | Powertech Technology Inc | Wafer dicing method to avoid thinned wafer breaking |
CN109559983A (en) * | 2018-11-16 | 2019-04-02 | 紫光宏茂微电子(上海)有限公司 | The cutting method of wafer |
CN110729186A (en) * | 2019-10-24 | 2020-01-24 | 东莞记忆存储科技有限公司 | Processing method for wafer cutting and separating |
CN111564367A (en) * | 2020-05-21 | 2020-08-21 | 江苏汇成光电有限公司 | Method for processing wafer cracking abnormity before wafer grinding |
CN111489966A (en) * | 2020-06-15 | 2020-08-04 | 紫光宏茂微电子(上海)有限公司 | Method for cutting wafer |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117524870A (en) * | 2023-12-29 | 2024-02-06 | 物元半导体技术(青岛)有限公司 | Wafer processing method and wafer |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI484544B (en) | Method of thinning a semiconductor wafer | |
US7592235B2 (en) | Semiconductor device including semiconductor memory element and method for producing same | |
KR101905199B1 (en) | Processing method of device wafer with bump | |
JP2002100588A (en) | Production method for semiconductor device | |
CN111489966A (en) | Method for cutting wafer | |
JP6956788B2 (en) | Board processing method and board processing system | |
WO2006008824A1 (en) | Method for manufacturing semiconductor integrated circuit device | |
CN103117250A (en) | Methods for de-bonding carriers | |
US8052505B2 (en) | Wafer processing method for processing wafer having bumps formed thereon | |
CN113380613A (en) | Wafer thinning processing method | |
JP7412131B2 (en) | Substrate processing method and substrate processing system | |
JP4074758B2 (en) | Processing method of semiconductor wafer | |
TW201635337A (en) | Method of dividing wafer into dies | |
TW200425232A (en) | Semiconductor device fabrication method | |
US20240096704A1 (en) | Processing method of wafer | |
US20230096486A1 (en) | Method of manufacturing layered device chip assembly | |
CN112959211B (en) | Wafer processing apparatus and processing method | |
CN213401146U (en) | Wafer bearing table and wafer embedding structure | |
JP2018206936A (en) | Substrate processing system and substrate processing method | |
US8157621B2 (en) | Wafer back side grinding process | |
JP7258175B2 (en) | Substrate processing method and substrate processing system | |
CN111613545B (en) | Wafer test structure and wafer test method | |
CN111463141B (en) | Method for improving utilization rate of wafer probe station | |
JP5356896B2 (en) | Manufacturing method of semiconductor device | |
TWI460780B (en) | Grinding and dicing method of wafer and production line apparatus thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: No. 9688, Songze Avenue, industrial park, Qingpu District, Shanghai, 201799 Applicant after: ChipMOS Technologies (Shanghai) Co.,Ltd. Address before: No. 9688, Songze Avenue, industrial park, Qingpu District, Shanghai, 201799 Applicant before: UNIMOS MICROELECTRONICS(SHANGHAI) Ltd. |