CN117524870A - Wafer processing method and wafer - Google Patents
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- CN117524870A CN117524870A CN202311852331.3A CN202311852331A CN117524870A CN 117524870 A CN117524870 A CN 117524870A CN 202311852331 A CN202311852331 A CN 202311852331A CN 117524870 A CN117524870 A CN 117524870A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Ceramic Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention relates to a wafer processing method and a wafer, wherein the wafer processing method comprises the following steps: providing a wafer, wherein the thickness of the wafer is 775um; grinding the edge area on the back of the wafer to form a step shape with the central area, wherein the width of the grinding edge area is 1mm-5mm, and the depth of the grinding edge area is 100um-500um; depositing a hard mask layer on the back of the wafer to cover the edge area and the central area of the back of the wafer; grinding the central region of the back surface of the wafer so that the thickness of the central region of the back surface of the wafer is greater than or equal to the thickness of the edge region; etching the center area of the back surface of the wafer after grinding to enable the thickness of the center area to be smaller than that of the edge area, wherein the thickness of the center area of the back surface of the wafer after etching is 30um-150um; ion implantation, annealing and metal deposition processes are performed on the back side of the wafer. The invention solves the technical problems of broken pieces and rough surface in the wafer thinning process.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a wafer processing method and a wafer.
Background
In recent years, insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviated as "IGBT") technology has been developed rapidly, and has become one of the most important high-power mainstream devices in the field of power electronics. The earliest IGBT species were of the punch through type (abbreviated as "PT") and non-punch through type (abbreviated as "NPT"). In recent years, an IGBT of a Field Stop (FS) structure has been developed, in which the FS region is an N-type doped region, and the FS region has a higher doping concentration than the N-region in the IGBT, and the effect is to rapidly reduce the electric Field strength at high voltage in the layer to achieve electric Field termination. The FS IGBT has low conduction voltage drop or conduction loss, and the conduction voltage drop temperature coefficient is positive, so that the high-power parallel connection is convenient.
Currently, the most common method for fabricating FS type IGBTs, see fig. 8, is: firstly, manufacturing a MOSFET device on the front side of a silicon substrate, then removing part of the silicon substrate of a residual layer left when manufacturing the MOSFET from the back side of a silicon wafer by a grinding method, wherein the residual layer generally comprises SiN, si02 and polysilicon, and the purpose of grinding part of the silicon substrate is to enable the thickness of the final silicon wafer to reach a value required by design, so as to obtain ideal breakdown voltage, switching characteristics and the like; respectively injecting N-type and P-type impurities from the back surface of the silicon wafer by using an ion implanter; and activating the implanted impurities by adopting thermal annealing or laser annealing to form the FS region and the collector electrode. The existing processing method is easy to cause problems of silicon wafer chipping and surface roughness after grinding due to stress during processing.
Disclosure of Invention
Aiming at the defects existing in the related art, the invention provides a wafer processing method and a wafer, and solves the technical problems of broken pieces and rough surface in the wafer thinning process.
According to a first aspect of the present application, there is provided a wafer processing method, in one possible embodiment, the method comprising: in step S10, a wafer is provided, the thickness of the wafer being 775um; in step S20, grinding the edge area of the back surface of the wafer so that the edge area and the central area of the back surface of the wafer form a step shape, wherein the width of the edge area of the back surface of the ground wafer is 1mm-5mm, and the depth of the edge area of the back surface of the ground wafer is 100um-500um; in step S30, a hard mask layer is deposited on the back surface of the wafer, and covers the edge area and the central area of the back surface of the wafer; in step S40, the center area of the back surface of the wafer is polished, and the thickness of the center area of the wafer after polishing the center area of the back surface of the wafer is greater than or equal to the thickness of the edge area of the wafer; in step S50, etching the center area of the wafer after the back grinding to make the thickness of the center area of the wafer smaller than the thickness of the edge area of the wafer, wherein the thickness of the center area of the etched wafer is 30um-150um; and, in step S60, ion implantation, annealing, and metal deposition processes are performed on the back surface of the wafer.
In one possible implementation, the etching of the thinned center region of the back side of the wafer may be performed by one or more of the following etching methods: dry etching, wet etching, ion beam etching, electron beam etching, and plasma etching.
In one possible implementation, the wafer is an IGBT wafer.
According to another aspect of the present application, there is provided a wafer, with the wafer processing method according to any one of the above embodiments, having an initial thickness of 775um and a diameter of 300mm; the thickness of the wafer in the central region after etching the central region and before depositing the metal layer is 30um-150um.
Based on the technical scheme, the wafer processing method and the wafer in the embodiment of the invention reduce broken pieces, improve the evenness and uniformity of the wafer surface and improve the yield in the wafer processing process.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a flow chart of a wafer processing method;
FIG. 2 is a schematic view of a wafer structure;
FIG. 3 is a schematic view of the structure of a thinned wafer edge;
FIG. 4 is a schematic diagram of a structure of a wafer after a hard mask layer is deposited after the wafer is thinned;
FIG. 5 is a schematic view of the structure after thinning the center region of the wafer;
FIG. 6 is a schematic diagram of the structure after etching the center region of the wafer;
FIG. 7 is a schematic diagram of a structure of a wafer after ion implantation, annealing, and metal deposition processes;
fig. 8 is a flow chart of a wafer processing process in the prior art.
In the figure:
10. a wafer; 11. a step; 12. hard mask layer, 13, metal layer.
Detailed Description
The technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or a third "may explicitly or implicitly include one or more such feature.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In order to solve the problems of broken pieces and rough surfaces in the wafer thinning process in the prior art, the application provides a wafer processing method.
Referring to fig. 1, in one possible embodiment, the method comprises: in step S10, a wafer is provided; in step S20, an edge region of the back surface of the wafer is polished; in step S30, a hard mask layer is deposited and formed on the back surface of the wafer; in step S40, polishing a center region of the back surface of the wafer; in step S50, etching the center area of the wafer after the back surface is polished; and, in step S60, the wafer is subjected to ion implantation, annealing, and metal deposition processes.
In one possible embodiment, in step S20, the edge region of the back surface of the wafer is thinned by using a chemical mechanical polishing CMP process, so that the edge region of the back surface of the wafer forms a step with the center region, see fig. 3.
In one possible embodiment, the wafer is provided with a thickness of 775um.
In the above solution, a wafer 10 is first provided, see fig. 2, where the material may be silicon or other semiconductor material, and the initial thickness of the wafer 10 is 775um, and here a large-sized IGBT wafer with a diameter of 300mm, which is 12 inches, is used; thinning the edge area of the back surface of the wafer by a mechanical or chemical method, wherein the edge area of the thinned wafer is ground by adopting a Chemical Mechanical Polishing (CMP) mode, so that the edge area forms a step 11 structure, and the process can be controlled accurately to ensure consistency and precision; then, a hard mask layer 12 is deposited on the back of the wafer, see fig. 4, which may use materials such as silicon nitride or silicon oxide to protect the back of the wafer; continuing to polish the center region of the back side of the thinned wafer to a desired thickness, see FIG. 5, wherein, as one embodiment, a chemical mechanical polishing CMP process is employed to thin the center region of the wafer; and processing the central region by etching techniques to form a specific microstructure or pattern, see fig. 6; finally, the wafer is subjected to ion implantation, annealing and metal deposition processes to form a circuit or other desired microstructure; referring to fig. 7, in step S60, a metal layer 13 is deposited.
In the above embodiment, the initial thickness of the wafer is 775um, which is the standard thickness of a wafer with a diameter of 300mm, which is 12 inches, and is the larger size of the existing large-size IGBT wafer, and the wafer has the advantages of high utilization rate and low cost of a single chip, so the research on the processing technology of the large-size IGBT wafer, especially the 12-inch wafer, accords with the development trend of processing and application of the large-size wafer.
In the above scheme, the edge area of the back surface of the wafer is thinned to form a step-like structure which is relatively lower than the central area. This structure is advantageous for subsequent process steps such as etching or metal deposition, as it provides a well defined working area for these processes. The stepped shape design also helps to improve mechanical stability of the wafer and reliability during processing.
During wafer fabrication, particularly in process steps performed at high temperatures, the wafer material is subjected to non-uniform thermal stresses. The stepped structure helps to more evenly distribute these stresses, reducing the risk of wafer bending or cracking due to thermal expansion; the wafer edge is generally more prone to defects such as scratches or microcracks than the center region. By forming a step-shaped structure, the edge area can be protected to a certain extent, and the occurrence of edge defects in the processing process is reduced; the stepped structure facilitates subsequent etching, metal deposition or other surface treatment steps, so that the processes are easier to control in the edge area, and the overall machining precision is improved.
In general, by forming a stepped structure in the edge region of the wafer, the mechanical and thermal stress distribution of the wafer can be optimized, defects in the edge region can be reduced, device performance can be improved, subsequent processing can be facilitated, and material loss can be reduced, thereby improving overall processing efficiency and device quality.
In one possible embodiment, in step S40, the center region of the back surface of the thinned wafer is polished, and the thickness of the polished center region is greater than or equal to the thickness of the edge region of the wafer.
In the above embodiments, the central region of the wafer back is thinned to a specific thickness that is greater than or equal to the thickness of the edge regions. Such a design may ensure that there is sufficient material in the center region of the wafer to support subsequent processing steps, such as etching or integrated circuit formation, while maintaining the integrity and mechanical strength of the edge regions.
Referring to fig. 3, in one possible embodiment, the width W1 of the edge region of the back side of the thinned wafer is 1mm to 5mm and the depth H1 of the edge region of the back side of the thinned wafer is 100um to 500um.
In the above embodiment, the thinned width of the edge region of the back surface of the wafer is between 1mm and 5mm, and the depth is between 100um and 500um, and such control of accuracy is critical to ensure uniformity and reliability of the wafer during subsequent processing.
In the above scheme, the thickness H2 of the thinned rear edge is 275um-675um.
In one possible embodiment, the edge thinning dimension in the wafer processing method is 1mm-5mm in width and 100um-500um in depth of the edge region, and the thickness of the thinned edge is 275um-675um respectively. There is a relationship between the size of such edge thinning and the final thickness of the finished wafer, which can affect the performance and results of the process.
The dimensions of the edge thinning are generally determined by the thickness of the finished wafer and the specific application requirements.
The relationship between the width of the edge region and the thickness of the center region of the finished wafer is also important. As a possible implementation, the width of the edge area is in positive relation to the thickness of the center area of the finished wafer; thicker wafer products correspond to wider edge regions to balance stress distribution, while thinner wafer products correspond to narrower edge regions.
The relationship between the dimension of the edge reduction and the thickness of the wafer is determined according to the requirements of a particular application. The appropriate dimensions are selected to improve processing results and to improve wafer performance and quality.
In the above-mentioned scheme, in step S30, the hard mask layer 12 is formed on the back surface of the wafer, and referring to fig. 4, the hard mask layer 12 covers the edge area and the center area of the back surface of the wafer.
In the above embodiment, the hard mask layer 12 covers the entire area of the back surface of the wafer, including the edge and the center. The layer of mask provides protection for the wafer, and prevents unnecessary damage or pollution in the subsequent process steps; in addition, it can also be used as a mask for subsequent etching or deposition processes to form precise microstructures.
In the above scheme, in step S40, only the central area of the IGBT wafer is polished and thinned, leaving the hard mask layer on the wafer edge, and using the hard mask layer on the wafer edge/wafer edge as the barrier layer for etching the back surface of the IGBT wafer, see fig. 5 and 6.
In one possible implementation, the etching of the thinned center region of the back surface of the wafer may be performed by one or more of the following etching methods: dry etching, wet etching, ion beam etching, electron beam etching, and plasma etching. Under the condition that a TaiKO process or a Glass bonding Glass bond process for grinding the inner circle of the wafer is not used, the back etching process of the wafer thinning process is completed, so that the wafer has better surface evenness and uniformity.
Dry etching: the material on the surface of the wafer is removed by using chemical reaction, and different gases and reaction conditions, such as nitrogen oxide, hydrofluoric acid, chlorine and the like, can be adopted in the dry etching to realize different etching effects; the dry etching has the characteristics of high precision and high selectivity, and is widely used in the fields of semiconductor manufacturing and the like.
Wet etching: wet etching uses a liquid chemical solution to remove material from the wafer surface. This may include wet etching or wet etching, depending on the solution and conditions used, for some materials, such as metals, oxides, etc.; wet etching has the advantage of being relatively simple, but may not be as accurate as dry etching.
Ion beam etching: the method involves aiming an ion beam at the wafer surface to remove material by ion bombardment; the ion beam etching can realize high-precision etching, and is suitable for high-precision and high-selectivity etching. It is commonly used in micro-nano processing.
Electron beam etching: the electron beam etching uses a high-energy electron beam to remove material from the wafer surface, and is suitable for high-resolution etching.
Plasma etching: plasma etching involves generating a plasma in a low pressure environment and using ions and radicals in the plasma to remove material;
atomic layer etching (ALD/ALE): atomic layer etching is a highly controlled process suitable for preparing ultra-thin films or performing high precision etching.
In the above scheme, in step S50, the center area of the back surface of the wafer that is ground and thinned is etched, so that the thickness of the center area of the wafer is smaller than the thickness of the edge area of the wafer, and the thickness of the center area of the back surface of the etched wafer is 30um-150um.
In the scheme, the thickness of the thinned large-size IGBT wafer can be smaller than or equal to 100um, the thin size reduces the process difficulty of subsequent processes such as cutting small chips, and the yield is improved.
In the scheme, for large-size IGBT wafers, particularly wafers with the diameter of 12 inches, namely 300mm and the thickness of 775um, the wafer processing method can reduce broken pieces, improve the uniformity and flatness of the back surface of the wafers and improve the quality of wafer products.
In the above scheme, the width of the edge area/step of the wafer and the thickness of the central area of the whole wafer finished product have a corresponding relationship, and the proportional relationship between the parameters in the above embodiment not only relates to the feasibility and effectiveness of wafer processing, but also has important influence on optimizing the mechanical strength, stress distribution, device performance and material utilization rate of the wafer. By adopting the corresponding relation of the parameters, the whole efficiency and the product quality of wafer processing are improved while meeting different application requirements.
In the above embodiment, the thickness of the thinned Insulated Gate Bipolar Transistor (IGBT) wafer may be 100um or less for a large-sized IGBT wafer. Such thickness control is critical to achieving high performance IGBT devices because it directly affects the electrical characteristics of the device, such as switching speed and power loss; thinned wafers are lighter, which is important for applications requiring lightweight solutions, such as aerospace and portable electronic devices.
In the above embodiments, the wafer used is an IGBT wafer, and is widely used in power electronics.
In one possible embodiment, the method further comprises: after step S60, an electrical test is performed on the wafer.
In another aspect, the present application provides a wafer, where the wafer is processed by using the wafer processing method according to any one of the foregoing embodiments, and the wafer has an initial thickness of 775um and a diameter of 300mm; the thickness of the wafer in the central region after etching the central region and before depositing the metal layer 13 is 30um-150um.
As an embodiment, the thickness of the wafer in the central region after etching the central region and before depositing the metal layer 13 is 100um.
In the above embodiments, the steps and parameters of any of the above embodiments are applied, the initial thickness 775um of the wafer; the edge area of the back surface of the wafer is thinned mechanically or chemically to form a step-shaped structure, the width of the polished thinned edge area is usually controlled between 1mm and 5mm, the depth is controlled between 100um and 500um, and the polishing process is controlled accurately to ensure consistency and precision. Then, depositing and covering a hard mask layer on the back of the wafer, wherein the hard mask layer can use materials such as silicon nitride or silicon oxide and the like to protect the back of the wafer; the hard mask layer covers the entire area of the wafer backside, including the edges and center, provides additional protection against unwanted damage or contamination during subsequent processing steps, and may act as a mask for subsequent etching or deposition processes.
Next, adopting a Chemical Mechanical Polishing (CMP) process to continuously polish the central area of the back surface of the thinned wafer to reach the required thickness, wherein in the scheme, the thickness of the central area of the thinned wafer is greater than or equal to that of the edge area of the wafer; the central region is then processed by etching techniques to form a specific microstructure or pattern. Etching the thinned center region of the back surface of the wafer by adopting a specific etching technology, such as Reactive Ion Etching (RIE), wet chemical etching or laser etching, wherein the specific selection depends on the required pattern precision, material compatibility and process efficiency; the thickness of the etched wafer center area is 30um-150um, which is smaller than the edge area of the wafer.
Finally, the wafer is subjected to ion implantation, annealing, and metal deposition processes to form circuits or other desired microstructures.
The wafer can be a large-size Insulated Gate Bipolar Transistor (IGBT) wafer, the thickness of the thinned wafer can reach 100um or below, so that the wafer has thinner thickness, fragments are reduced, and the yield is improved on the premise of ensuring the electrical performance of a high-performance IGBT device.
Finally, it should be noted that: in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same; while the invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present invention or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the invention, it is intended to cover the scope of the invention as claimed.
Claims (4)
1. A method of processing a wafer, the method comprising:
in step S10, a wafer is provided, the thickness of the wafer being 775um;
in step S20, grinding the edge area of the back surface of the wafer so that the edge area and the central area of the back surface of the wafer form a step shape, wherein the width of the edge area of the back surface of the ground wafer is 1mm-5mm, and the depth of the edge area of the back surface of the ground wafer is 100um-500um;
in step S30, a hard mask layer is deposited on the back surface of the wafer, and covers the edge area and the central area of the back surface of the wafer;
in step S40, the center area of the back surface of the wafer is polished, and the thickness of the center area of the back surface of the wafer is greater than or equal to the thickness of the edge area of the wafer;
in step S50, etching the center area of the wafer after the back grinding to make the thickness of the center area of the wafer smaller than the thickness of the edge area of the wafer, wherein the thickness of the center area of the etched wafer is 30um-150um; the method comprises the steps of,
in step S60, ion implantation, annealing, and metal deposition processes are performed on the wafer backside.
2. The wafer processing method according to claim 1, wherein: in step S50, etching is performed on the center area of the ground wafer back, and one or more of the following etching methods are adopted: dry etching, wet etching, ion beam etching, electron beam etching, and plasma etching.
3. The wafer processing method according to claim 2, wherein the wafer is an IGBT wafer.
4. A wafer, applying the wafer processing method of any one of claims 1-3, wherein the wafer has an initial thickness of 775um and a diameter of 300mm; the thickness of the wafer in the central region after etching the central region and before depositing the metal layer is 30um-150um.
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