CN107039459A - SOI and body silicon mixing crystal circle structure and preparation method thereof - Google Patents
SOI and body silicon mixing crystal circle structure and preparation method thereof Download PDFInfo
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- CN107039459A CN107039459A CN201610092270.9A CN201610092270A CN107039459A CN 107039459 A CN107039459 A CN 107039459A CN 201610092270 A CN201610092270 A CN 201610092270A CN 107039459 A CN107039459 A CN 107039459A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
Abstract
The invention discloses SOI and body silicon mixing wafer structure and preparation method, using silicon-on-insulator (SOI) wafer as substrate, the mixing wafer that soi structure coexists with body silicon structure is prepared, using the substrate as light path circuit monolithic die.Soi structure and body silicon structure and the mixing wafer deposited, it is characterised in that mixing wafer is made up of soi structure part and the mixing of body silicon part；Silicon-on-insulator part includes top silicon layer, oxygen buried layer and silicon substrate, and body silicon part is monocrystal silicon structure；SOI regions are optical path area, and bulk silicon region is circuit region.Preparation method is included in the window for being produced in starting SOI wafer by photoetching and etching and preparing bulk silicon region, and growing bulk silicon region by the method for conventional epitaxial, then remove unwanted polysilicon by flatening process makes surfacing；Preparation method is further characterized in that the selection isolated between SOI regions and bulk silicon region, the selection of epitaxy technique and the selection of flatening process.
Description
Technical field
The present invention relates to integrated optics and microelectronics techniques, especially SOI and body silicon mixing wafer knot
Structure and preparation method thereof.
Background technology
In recent years, as silicon substrate integrated optics develops, silicon-on-insulator (SOI) material is good with its
Guided wave performance be increasingly widely applied in terms of Wave Guiding Optics device and opto-electronic device,
Light path circuit single-chip integration turns into inexorable trend.And microelectronic foundries processing circuit is exhausted big
Partial mature technique is that, based on body silicon substrate, the technique based on SOI substrate is developed again needs one again
The fixed construction cycle.Therefore exploitation SOI and body silicon mix wafer substrate to be used as light path circuit monolithic collection
Into the substrate of chip, you can SOI wafer is served as a contrast with meeting the light path part in light path circuit single-chip integration
The need for bottom, the need for its circuit part can also be met to body silicon substrate, make existing light path devices
With existing integrated circuit process flow can separate carry out, finally realize light path circuit single-chip integration into
For possibility.
At present, there is a kind of more complicated mixing wafer substrate fabrication method (bibliography
" US8877600 B2 "), it is necessary to body silicon layer is grown by selective epitaxial process (SEG), and
Need to perform etching the polysilicon region between body silicon structure and soi structure, formed shown in Figure 22
Structure.In addition to the requirement of complicated SEG techniques, the shortcoming for having deposited method also resides in shortage effectively
Planarization and final SOI push up the control method of silicon layer thickness.
The present invention is opened by the analysis to microelectronic foundries processing technology, and actual technology
Hair, it is proposed that easily realize and be prepared by the controllable mixing wafer based on flatening process of machining accuracy
Method.On requiring that the brief description of shielded embodiment is stated below in the present invention, but not
It is used as limitation of the scope of the invention.The other details for the embodiments of the invention being briefly summarized, and
/ or the other embodiment of the present invention hereinafter will be stated in " embodiment ".
The content of the invention
It is an object of the invention to provide the mixing wafer system of a kind of soi structure and body silicon structure common substrate
Preparation Method, can make optical device and the single chip integrated standard process flow of integrated circuit, make full use of
The existing integrated circuit process flow of microelectronic foundries, acceleration is entered in commercial CMOS foundries
Process prepared by row photoelectricity integrated chip.
The present invention is to provide SOI and body silicon to solve the technical scheme that above-mentioned technical problem is used
The preparation method of wafer is mixed, is mainly comprised the following steps：S1：In SOI wafer to be processed
Surface deposits one layer of mask layer；S2：Remove mask layer, top silicon layer andOxygen buried layerA part,
Form a window for exposing body silicon substrate；S3：Conventional growing epitaxial silicon is carried out, in window
Growing single-crystal silicon layer, on mask layer growing polycrystalline silicon layer or do not grow (depend on use
The method of extension)；S4：If desired, removing the polycrystalline on mask layer using flattening method
Silicon layer, and it is total to the upper surface of the monocrystalline silicon layer grown in window and the upper surface of mask layer
Face；S5：Lift-off mask layer is to the upper surface for exposing SOI wafer top silicon layer；And again using flat
Smoothization method is surface-treated, and is made in window on monocrystalline silicon upper surface and SOI wafer top silicon layer
Surface co-planar, obtains mixing wafer disclosed by the invention.
Above-mentioned technique preparation process, if full implementation, will obtain SOI and body shown in Fig. 3
Silicon mixing crystal circle structure.If S5 steps saved, the mixing wafer shown in Fig. 8 is obtained
Structure.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, S4 planarisation steps can be adopted
With cmp flatening process and photoresist etching flatening process.Such as use photoresist
Flatening process is etched, i.e., planarizing surface of wafer is treated in covering with photoresist, then carries out whole Zhang Jing
Round etching, the etching selection ratio between photoresist and silicon is 0.8: 1 to 1: 1.2.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, growth in the window
The upper surface of monocrystalline silicon is higher than the mask layer upper surface.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, growth in the window
The upper surface of monocrystalline silicon is higher than the top silicon layer upper surface of the starting SOI wafer, and less than covering
Film layer upper surface.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, the institute after lift-off mask layer
The flatening process of implementation, injects and peels off on hydrogen ion implantation layer including the use of hydrogen ion
The step of silicon layer.
Another SOI and body silicon mixing crystal circle structure preparation method：S1：In insulator to be processed
Upper silicon wafer surface deposits one layer of mask layer；S2：Remove mask layer, top silicon layer andOxygen buried layer's
A part, forms a window for exposing body silicon substrate；S3：On the wafer after forming window
Spacer medium layer is deposited, the one direction etching for spacer medium layer is carried out afterwards until silicon
Surface so that remaining spacer medium exists only in the window side wall；S4：Carry out selective silicon
Epitaxial growth, the growing single-crystal silicon layer in the window；S5：Using flattening method to mask
Layer；S6：Lift-off mask layer is to the upper surface for exposing SOI wafer top silicon layer；And again using flat
Smooth chemical industry skill is surface-treated, and makes monocrystalline silicon upper surface and SOI wafer top layer in the window
Silicon upper surface is coplanar.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, epitaxial growth institute in the window
The monocrystalline silicon upper surface of formation is higher than mask layer upper surface.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, epitaxial growth institute in the window
The monocrystalline silicon upper surface of formation higher than starting SOI wafer top silicon layer upper surface, and less than covering
Film layer upper surface.
Above-mentioned SOI and body silicon mixing wafer preparation method, wherein, implemented after lift-off mask layer
Flatening process, including the use of hydrogen ion inject and peel off hydrogen ion implantation layer on silicon layer step
Suddenly.
Present invention contrast prior art has following beneficial effect：The invention provides mixing wafer substrate
Preparation method, using the mixing wafer substrate for preparing of the present invention, pass through certain photoetching alignment mark
After design and the adjustment of layout design rules, optical device technological process and integrated circuit can not changed
Under conditions of technological process, the making of photoelectricity integrated chip is realized.Meanwhile, the present invention is compared with reference to text
Offer the difficulty of processing reduced in mixing wafer preparation process, and the body of the mixing wafer finally prepared
The upper surface in silicon structure and soi structure region is coplanar, and the mix-crystal for using bibliography method to prepare
Circle upper surface is non-coplanar.
Brief description of the drawings
Fig. 1-2 is process chart prepared by SOI disclosed by the invention and body silicon mixing wafer.
Fig. 3 is SOI disclosed by the invention and body silicon mixing wafer schematic diagram.
Fig. 4-11 is one embodiment stream of SOI disclosed by the invention and body silicon mixing wafer preparation method
Journey schematic diagram.
Figure 12~13 are epitaxial growth schematic diagrames in another embodiment disclosed by the invention.
Figure 14 is SOI derivative on the basis of Fig. 3 disclosed by the invention and body silicon mixing crystal circle structure
Schematic diagram.
Figure 15~21 are another implementation of SOI disclosed by the invention and body silicon mixing wafer preparation method
Example schematic flow sheet.
Figure 22~23 are a kind of existing mixing crystal circle structures.
Embodiment
The present invention can be embodied by number of different ways, some of the invention be also described specific
Embodiment.This description is simply to principle of the present invention for example, rather than limit the present invention to spy
In fixed scope of embodiments.
For the purpose of the present invention, unless otherwise specified, identical numeral should point to same spy in accompanying drawing
Levy.
The present invention is described in detail below by specific embodiment and with reference to accompanying drawing：
Herein, our this structures of body Silicon Wafer are called body silicon structure；Claim SOI wafer
This structure is soi structure.
Fig. 3 is SOI disclosed by the invention and body silicon mixing wafer schematic diagram.As shown in figure 3,
SOI and body silicon mixing wafer 100 disclosed by the invention includes body silicon structure part 1 and SOI
Structure division 2.Body silicon structure part 1 is by body silicon substrate 11, the and of single-crystal Si epitaxial layers 51
The polysilicon epitaxial layer 55 on bulk silicon region periphery is constituted, wherein single-crystal Si epitaxial layers 51 and polycrystalline
Silicon epitaxy layer 55 is prepared on body silicon substrate 11 by epitaxy technique.Soi structure
2 are made up of body silicon substrate 11, oxygen buried layer 31 and top silicon layer 21.Disclosed by the invention mixed
In synthetic circle 100, body silicon substrate 11, oxygen buried layer 31 and top silicon layer 21 are all from same
SOI wafer.Fig. 1 is the process chart of the SOI and the processing of body silicon mixing crystal circle structure, in detail
Thin process is as follows：
It is SOI disclosed by the invention and body silicon mixing wafer preparation method from Fig. 4 to Figure 11
One embodiment flow chart.
Fig. 4 is the SOI wafer to be processed of a standard, the wafer be by body silicon substrate 11,
Oxygen buried layer 31 and top silicon layer 21 are constituted.
One of emphasis of the present invention is planarization process.Due to (page 2 last of planarization
9 rows：Planarization after S5 lift-off masks layer) need to consume a part of SOI tops silicon layer, it is to be added
The thickness of the top silicon layer 21 of the SOI wafer of work must be selected more thick than target thickness.Most
Good selection grinds away certain thickness SOI top silicon layers and the list of body silicon structure when being planarization
Crystal silicon layer, it is ensured that the top upper surface of silicon layer 21 of soi structure and the upper surface of body silicon structure 1 are total to
Face.The SOI tops silicon layer thickness ground away in planarization process can not be blocked up, excessive top silicon
Layer amount of grinding can cause grinding endpoint control accuracy to be deteriorated, while can cause the top silicon of soi structure
Top silicon layer thickness difference of the layer 21 at crystal circle center and edge is increased, and influences the yields of product.
The selection top silicon layer thickness SOI wafer thicker than required thickness, the thickness exceeded is according to final flat
The technological ability of smoothization is determined, is generally selected top silicon layer thickness and is exceeded required thickness 20nm~60nm
SOI wafer.Type and the resistivity selection of the body silicon substrate 11 of SOI wafer to be processed,
Formulated according to the demand of IC substrate to be produced, selection and integrated circuit to be produced
Required substrate type and resistivity require consistent body silicon substrate 11.
Fig. 5 is using chemical vapor deposition method one layer of mask layer 41 of deposition in SOI wafer.
Mask layer 41 can be any suitable material, such as silica or silicon nitride material.
In another embodiment, mask layer 41 can also be combined by multilayer material, such as
One layer of silica material is first deposited, redeposited one layer of silicon nitride material also or first deposits one layer
Silica material, redeposited one layer of polycrystalline silicon material.The material of mask layer 41 disclosed by the invention is simultaneously
It is not limited to above-mentioned illustrated material.
In another embodiment, the silica material in mask layer 41 can also be by thermal oxide
Technique growth is obtained.
Fig. 6 is to remove to be located in mask layer 41 that the part of body silicon structure overlying regions will be made, and is led to
Photoetching process and the pattern transfer technology formation etching window 33 of etching technics are crossed, covering for window area
The partial etching of film layer 41, top silicon layer 21 and oxygen buried layer 31 falls, until exposing body silicon substrate 11.
The method for removing oxygen buried layer 31 can be dry etching or dry etching plus wet etching.Bury oxygen
The thickness of layer 31 is typically 0.15um~2um, and special product has thicker oxygen buried layer.Individually
Dry etching oxygen buried layer 31 is easily operated, but the upper surface of destructible body silicon substrate 11, is caused rear
Epitaxial layer quality during continuous growing epitaxial silicon declines.Control the dry etching time surplus to oxygen buried layer 31
Remaining thickness is less than 0.1um, and then use wet etching is handled, and understands the upper of keeping body silicon substrate 11
Surface is not damaged, the defects count of epitaxial layer during reduction subsequently epitaxial growing.
Fig. 7 is to use epitaxy technique to grow silicon epitaxy layer in above-mentioned finished SOI wafer,
In the present embodiment, conventional epitaxial or embedment extension (BEG) technique are used so that positioned at quarter
Growth is more on growing single-crystal silicon epitaxial layer 51 on body silicon substrate 11 at fenetre mouthful 33, mask layer 41
The polysilicon epitaxial of about 51 degree of extension in crystal silicon epitaxial layer 52, the oriented window of boundary of etching window
Layer 55.In etching window 33, the single-crystal Si epitaxial layers 51 and polysilicon epitaxial of growth layer 55 it is upper
Surface is higher than the upper surface of mask layer 41.
In another embodiment, in etching window 33, single-crystal Si epitaxial layers 51 of growth and many
The upper surface of crystal silicon epitaxial layer 55 can be less than the upper surface of mask layer 41, but higher than the top of SOI wafer
The upper surface of silicon layer 21.
" method in US8877600 B2 " is similar to shown in Figure 12, in etching window bibliography
Selective epitaxial (SEG) is used in 33, it is raw in window during using selective epitaxial growth silicon epitaxy layer
The upper surface of long monocrystalline silicon layer 51 and polysilicon epitaxial layer 55 is uneven, it is necessary to make single in window
The minimum point of the upper surface of crystal silicon layer 51 and polysilicon epitaxial layer 55 is equal to or higher than the top of SOI wafer
Silicon layer upper surface, the top silicon layer of body silicon structure 1 and soi structure 2 is made by final planarization process
21 upper surface is coplanar, and this " is not proposed, according to ginseng in bibliography in US8877600 B2 "
There is tens nanometers of height in the soi structure surface and body silicon structure surface for examining the mixing wafer of document preparation
Degree is poor.Flattening method proposed by the present invention, with reference to Figure 10 structure, may be constructed the present invention's
Another embodiment.But the implementation condition of selective epitaxial (SEG) is generally than conventional epitaxial or embedment
(BEG) harsher, it is desirable to low temperature, low pressure and different reacting gas environment, and SEG
Extension speed ratio BEG it is many slowly.SEG will not be at non-silicon material (such as silica or silicon nitride)
Mask layer 41 on deposit polycrystalline silicon (if mask layer 41 uses the last composite construction for polysilicon,
Then SEG effect will be similar with BEG), therefore, subsequent planarization S4 and S5 reality
Shi Huihe is different using BEG flow.
Fig. 8 is that the crystal column surface externally delayed is planarized.Until exposing mask layer 41
Upper surface, that is, remove the single-crystal Si epitaxial layers 51 for being higher than the surface of mask layer 41, polysilicon epitaxial
Layer 55 and polysilicon epitaxial layer 52.
The planarization of this step can be that cmp (CMP) technique or photoresist etching are flat
Smooth chemical industry skill.When etching flatening process using photoresist, first applied on the surface of above-mentioned wafer
One layer of photoresist, the selection of photoresist makes the rising inside and outside step of the photoresist upper surface after coating
Volt minimum is preferred, and the etching operation of whole surface is carried out afterwards, etches into be completely exposed always and covers
The upper surface of film layer 41.In above-mentioned process, the selection ratio of regulation etching technics is to close
Key is, it is necessary to which the selection for adjusting etches polycrystalline and etching photoresist is compared from 0.8: 1 to 1: 1.2.
In further embodiments, due in etching window 33, the monocrystalline silicon epitaxy of growth
The upper surface of layer 51 and polysilicon epitaxial layer 55 can be less than the upper surface of mask layer 41, so
When being planarized to crystal column surface, the polysilicon higher than the surface of mask layer 41 has only been ground off
Epitaxial layer 52.
In another embodiment, due to growing silicon epitaxy layer using selective epitaxial (SEG),
There is no growing polycrystalline silicon epitaxial layer on the surface of mask layer 41, when monocrystalline silicon in etching window 33
When the upper surface of layer 51 and polysilicon epitaxial layer 55 is not higher than 41 upper surface of mask layer, i.e., not
The coplanar processing for carrying out body silicon structure surface and mask layer upper surface is needed to be put down, it is necessary to skip this step
Smooth chemical industry skill procedure of processing.
Fig. 9 is to inject hydrogen ion in above-mentioned crystal column surface, due to blocking for mask layer 41, only
Hydrogen ion is formed in single-crystal Si epitaxial layers 51 and the polysilicon epitaxial layer 55 of etching window 33
Layer 60, it is generally the case that the lower surface of hydrogen ion layer 60 is slightly above the top silicon layer of SOI wafer
21 upper surface.Note, must be according to monocrystalline silicon layer 51 in window and polysilicon epitaxial layer 55
Upper surface is higher by the thickness of the top upper surface of silicon layer 21 of SOI wafer, decides whether using injection
Hydrionic pretreatment mode.
In another embodiment, the lower surface slightly below SOI of hydrogen ion layer 60 can also be made
The upper surface of the top silicon layer 21 of wafer.This processing mode can when it is required prepare SOI and
When the area of body silicon structure is more than the area of soi structure in body silicon mixing wafer.Now, hydrogen from
The lower surface of sublayer 60 is slightly below the upper surface of the top silicon layer 21 of SOI wafer, the raised area
SOI tops silicon layer can be consumed quickly in ensuing planarization process, beneficial to the flat of entirety
Change terminal precision controlling.
Figure 10 is the mask layer 41 for removing crystal column surface.Mask layer 41 can for silica material or
Silicon nitride material, silica material can be removed using hydrofluoric acid (BOE) wet etching, nitrogen
Silicon nitride material can be removed using hot phosphoric acid wet etching.
Figure 11 is, by above-mentioned wafer load to heat-treatment furnace, (to be led to by the temperature for being heated to certain
Often it is higher than 400 degrees Celsius) so that the local structure containing hydrogen ion layer of wafer is at hydrogen ion layer 60
Fracture, then above-mentioned crystal column surface is handled using flatening process, so as to obtain mixing such as Fig. 3
Synthetic circle 100.If foregoing hydrogen ion injection is omitted, flatening process is directly entered.
This step flatening process is mainly cmp (CMP) technique.It is required that the chemistry of this step
The speed of mechanical milling tech grinding monocrystalline silicon is slow, for the grinding of the single crystal silicon material of different resistivity
Speed difference is small, can be accurately controlled the thickness of the monocrystalline silicon ground away.
It is slightly above top silicon layer in the upper surface of single-crystal Si epitaxial layers 51 and the polysilicon epitaxial layer 55 of growth
In 21 upper surface embodiment (as shown in figure 13), it is therefore not required to inject hydrogen ion in monocrystalline silicon
Hydrogen ion layer 60, the mask layer that only need to externally delay are formed in epitaxial layer 51 and polysilicon epitaxial layer 55
The polysilicon epitaxial layer 52 on 41 surfaces carries out planarization removal, until expose the upper surface of mask layer 41,
Remove the polysilicon epitaxial layer 52 higher than the surface of mask layer 41.Then covering for crystal column surface is removed again
Film layer 41, and being handled surface using cmp (CMP) technique, thus obtain as
Fig. 3 SOI and body silicon mixing wafer 100.
It is slightly below top silicon layer in the upper surface of single-crystal Si epitaxial layers 51 and the polysilicon epitaxial layer 55 of growth
(such as when the area of prepared body silicon structure is more than soi structure in the embodiment of 21 upper surface
During area, this embodiment can be used).The polysilicon epitaxial on the surface of mask layer 41 externally delayed
Layer 52 carries out planarization removal, until exposing the upper surface of mask layer 41, that is, removes and is higher than mask layer
The polysilicon epitaxial layer 52 on 41 surfaces.The mask layer 41 of crystal column surface is removed again, and using chemical machine
Tool grinding (CMP) technique is handled surface, so as to obtain the mixing wafer 100 such as Fig. 3.
Another SOI and body silicon mixing crystal circle structure disclosed by the invention is as shown in figure 14.In this mixing
In crystal circle structure, with 47 (Spacer) of spacer medium layer between body silicon structure 1 and soi structure 2.
Specific forming step is as follows：
Complete after the processing of structure shown in above-mentioned Fig. 6, in one layer of dielectric layer 47 of surface deposition, form figure
Structure shown in 15.Dielectric layer 47 can be silica or silicon nitride.The thickness foundation of dielectric layer 47
The demand of separation layer thickness is determined, common thickness range is 0.05um~1um.
The dry etching of full wafer is carried out to the wafer shown in Figure 15, the medium except the surface of mask layer 41 is carved
The dielectric layer 47 of layer 47 and the bottom surface portions of etching window 33, leaves the dielectric layer 47 on window periphery,
Obtain structure as shown in figure 16 (now remaining 47 be spacer medium layer 47).
Figure 17 is using selective epitaxial process (SEG) growth silicon on the basis of Figure 16 crystal circle structure
Epitaxial layer, the growing single-crystal silicon epitaxial layer 51 on the body silicon substrate 11 at etching window 33 is raw
Length direction is from the bottom to top.Method different from the past, due to the presence in side wall spacer medium layer 47,
An epitaxial growth direction is only existed in etching window 33, is not in as that polycrystalline in Figure 12
Silicon part.
If the growth thickness of monocrystalline silicon is higher than the upper surface of mask layer 41 in etching window 33,
Both sides on monocrystalline silicon island 51, it may appear that a little polysilicon 555.In certain embodiments,
The upper surface on monocrystalline island 51 that can also be in selective etching window 33 is less than mask layer 41
Upper surface, such polysilicon 555 would not occur, and can now simplify follow-up planarization step
Suddenly.
Figure 18 is in the case that monocrystalline silicon island 51 in fig. 17 are higher than mask layer 41, right
The crystal column surface delayed outside is planarized, until exposing the upper surface of mask layer 41., that is, go
Except the single-crystal Si epitaxial layers 51 and polysilicon 555 higher than the surface of mask layer 41.
In certain embodiments, Figure 18 structure can be selected as the knot of last mixing wafer
Structure.For example, before SOI and body silicon mixing wafer Making programme, the light channel structure such as fiber waveguide
Completed in the SOI wafer (such as Figure 14) of starting.Under this situation, it is not necessary to
SOI tops silicon layer 21 is etched in follow-up circuit technology flow, can select to be put
Under the protection of mask layer 41.
Figure 19 is the crystal column surface injection hydrogen ion after Figure 18, in etching window 33
Hydrogen ion layer 60 is formed in single-crystal Si epitaxial layers 51, the lower surface of hydrogen ion layer 60 is slightly above
The upper surface of the top silicon layer 21 of SOI wafer.
Figure 20 is the mask layer 41 for removing crystal column surface.Mask layer 41 can for silica material or
Silicon nitride material, silica material is removed using hydrofluoric acid (BOE) wet etching, silicon nitride
Material is removed using hot phosphoric acid wet etching.
Figure 21 is by above-mentioned wafer load to heat-treatment furnace, by being heated to certain temperature
(be usually above 400 degrees Celsius) so that the local structure containing hydrogen ion layer of wafer hydrogen from
It is broken, then above-mentioned crystal column surface is handled at sublayer 60 using flatening process, so that
Obtain the mixing wafer 100a such as Figure 14.
When the upper surface of monocrystalline island 51 in the etching window 33 in Figure 17 is slightly above SOI tops
During silicon layer upper surface, Figure 19 hydrogen ion injection can select to skip, and directly carry out in Figure 20
Mask layer 41 peel off.Then flatening process is used, the SOI and body silicon for obtaining Figure 14 are mixed
Synthetic justifies 100a.
The present invention is described in detail embodiment of above, and exhaustive.It is general in this area
Logical technical staff can make many variations example to the present invention according to the above description.Thus, embodiment party
Some of formula details should not constitute limitation of the invention, and the present invention will be with appended claims
The scope that book is defined is as protection scope of the present invention.
Claims (15)
1.SOI and body silicon mixing crystal circle structure, it is characterised in that wafer is made up of silicon-on-insulator (SOI) structure division and the mixing of body silicon part；Silicon-on-insulator part includes top silicon layer, oxygen buried layer and body silicon substrate, and body silicon part is monocrystal silicon structure；There are polysilicon and defect area band between silicon-on-insulator part and body silicon part.
2. the method for preparing SOI as claimed in claim 1 and body silicon mixing wafer, its step includes：S1：One layer of mask layer is deposited on silicon-on-insulator wafer surface to be processed；S2：Remove mask layer, top silicon layer andOxygen buried layerA part, form a window for exposing body silicon substrate；S3：Conventional growing epitaxial silicon is carried out, the growing single-crystal silicon layer in the window；S4：Using flatening process to mask layer.
3. forming the process of SOI and body silicon mixing wafer described in claim 2, its subsequent step includes：S5：Lift-off mask layer is to the upper surface for exposing SOI wafer top silicon layer；And be surface-treated again using flatening process, make monocrystalline silicon upper surface and SOI wafer top layer silicon upper surface in window coplanar.
4. a kind of process of formation SOI and body silicon mixing wafer described in claim 2, wherein the flatening process of S4 steps can be cmp (CMP) flatening process or photoresist etching flatening process, the photoresist etches flatening process, i.e. planarizing surface of wafer is treated in covering with photoresist, whole Zhang Jingyuan etching is carried out again, and the etching selection ratio between photoresist and silicon is 0.8: 1~1: 1.2.
5. a kind of process of formation SOI and body silicon mixing wafer described in claim 2, wherein the upper surface of the monocrystalline silicon of growth is higher than the mask layer upper surface in the window.
6. a kind of process of formation SOI and body silicon mixing wafer described in claim 2, wherein the upper surface of the monocrystalline silicon of growth is higher than the top silicon layer upper surface of the starting SOI wafer in the window, and less than mask layer upper surface.
7. a kind of process of formation SOI and body silicon mixing wafer described in claim 3, wherein the flatening process implemented after lift-off mask layer, the step of being injected including the use of hydrogen ion and peel off the upper silicon layer of hydrogen ion implantation layer.
8.SOI and body silicon mixing crystal circle structure, it is characterised in that wafer is made up of silicon-on-insulator (SOI) structure division and the mixing of body silicon part；Silicon-on-insulator part includes top silicon layer, oxygen buried layer and body silicon substrate up of three layers, and body silicon part is monocrystal silicon structure；There is spacer medium layer (Spacer) between silicon-on-insulator part and body silicon part.
9. SOI described in claim 8 and body silicon mixing crystal circle structure, being further characterized in that on silicon on insulated substrate part has mask layer protection, and the upper surface and mask layer upper surface of body silicon part are coplanar.
10. the method for preparing SOI as claimed in claim 8 and body silicon mixing wafer, its step includes：S1：One layer of mask layer is deposited on silicon-on-insulator wafer surface to be processed；S2：A part for mask layer, top silicon layer and oxygen buried layer is removed, a window for exposing body silicon substrate is formed；S3：The deposition spacer medium layer on the wafer after forming window, carries out the one direction etching for spacer medium layer until silicon face so that remaining spacer medium exists only in the window side wall afterwards；S4：Selective silicon epitaxial growth is carried out, the growing single-crystal silicon layer in the window；S5：Using flatening process to mask layer.
11. a kind of process of formation SOI and body silicon mixing wafer described in claim 10, its subsequent step includes：S6：Lift-off mask layer is to the upper surface for exposing SOI wafer top silicon layer；And be surface-treated again using flatening process, make monocrystalline silicon upper surface and SOI wafer top silicon layer upper surface in the window coplanar.
12. a kind of process of formation SOI and body silicon mixing wafer described in claim 10, wherein the monocrystalline silicon upper surface that epitaxial growth is formed in the window is higher than mask layer upper surface.
13. a kind of process of formation SOI and body silicon mixing wafer described in claim 10, wherein upper surface of the monocrystalline silicon upper surface that epitaxial growth is formed in the window higher than starting SOI wafer top silicon layer, and less than mask layer upper surface.
14. a kind of process of formation SOI and body silicon mixing wafer described in claim 10, the wherein flatening process of S5 steps can be cmp (CMP) flatening process or photoresist etching flatening process.
15. a kind of process of formation SOI and body silicon mixing wafer described in claim 11, wherein the flatening process implemented after lift-off mask layer, the step of being injected including the use of hydrogen ion and peel off the upper silicon layer of hydrogen ion implantation layer.
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