CN104078357A - Method for manufacturing fin type field effect tube - Google Patents
Method for manufacturing fin type field effect tube Download PDFInfo
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- CN104078357A CN104078357A CN201310105896.5A CN201310105896A CN104078357A CN 104078357 A CN104078357 A CN 104078357A CN 201310105896 A CN201310105896 A CN 201310105896A CN 104078357 A CN104078357 A CN 104078357A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 230000005669 field effect Effects 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000126 substance Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 300
- 150000002500 ions Chemical class 0.000 claims description 115
- -1 germanium ion Chemical class 0.000 claims description 69
- 238000000227 grinding Methods 0.000 claims description 66
- 238000002513 implantation Methods 0.000 claims description 40
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 32
- 239000007788 liquid Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 239000008393 encapsulating agent Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 238000003701 mechanical milling Methods 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 14
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical group [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 10
- 229910001439 antimony ion Inorganic materials 0.000 claims description 10
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 239000008119 colloidal silica Substances 0.000 claims description 8
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 5
- 239000003085 diluting agent Substances 0.000 claims description 4
- 230000009969 flowable effect Effects 0.000 claims description 3
- 239000002346 layers by function Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 239000012535 impurity Substances 0.000 description 7
- 239000000243 solution Substances 0.000 description 5
- 238000003801 milling Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 229930002839 ionone Natural products 0.000 description 3
- 150000002499 ionone derivatives Chemical class 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
A method for manufacturing a fin type field effect tube comprises the steps that a semiconductor substrate is provided, a plurality of independent fins are arranged on the semiconductor substrate, isolating structures are arranged between the adjacent fins, and the surfaces of the isolating structures are lower than the top surfaces of the fins; a sacrificial layer covering the fins and the isolating structures is formed; the sacrificial layer is subjected to ion implantation to form an ion doped layer in the sacrificial layer; the chemical mechanical lapping technology is used for flattening the sacrificial layer, and the ion doped layer is used as a stop layer; the rest of the sacrificial layer is etched to form a fake gate which crosses over the surfaces of the tops and the surfaces of the side walls of the fins. The ion doped layer is used as the stop layer, and therefore the thickness of the rest of the sacrificial layer can be accurately controlled.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of fin field effect pipe.
Background technology
MOS transistor, by applying voltage at grid, regulates and produces switching signal by the electric current of channel region.But in the time that semiconductor technology enters 30 nanometers with lower node, traditional plane formula MOS transistor dies down to the control ability of channel current, causes serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multiple-grid device, it generally comprises the semiconductor fin that protrudes from semiconductor substrate surface, the top of fin and the grid structure of sidewall described in cover part, be positioned at source region and the drain region of the fin of described grid structure both sides.
In order to reduce the parasitic capacitance of fin formula field effect transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in fin formula field effect transistor.The gate stack structure of existing metal gates and high K gate dielectric layer adopts " rear grid (gate last) " technique to make conventionally.
Fig. 1～Fig. 2 shows the cross-sectional view of the forming process of a kind of fin formula field effect transistor of prior art.
First, please refer to Fig. 1, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, there is the fin 101 of some projections; Then, in the Semiconductor substrate 100 between adjacent fin 101, form isolation structure 102, the top surface of described isolation structure 102 is lower than the top surface of described fin 101; Then, form the sacrifice layer 103 covering on described fin 101 and isolation structure 102.In rear grid (Gate-last) technique, described sacrifice layer 103 is follow-up is used to form pseudo-grid.
Because the top surface of described isolation structure 102 is lower than the top surface of described fin 101, between adjacent fin 101, there is groove, in the time forming sacrifice layer 103, can make the surface of sacrifice layer of isolation structure 102 tops lower than the surface of the sacrifice layer of fin 101 tops, cause sacrifice layer 103 surface irregularities, the thickness evenness of grid sacrifice layer 103 is poor, is unfavorable for the control to depth of focus in photoetching, affects follow-up manufacturing process.
And in order to address this problem; existing conventionally can to form sacrifice layer 103 carry out flatening process; with reference to figure 2; described in the polishing of employing cmp (CMP) technique, sacrifice layer 103(as shown in Figure 1); form pseudo-gate material layer 104; the surface ratio of the pseudo-gate material layer 104 forming is more smooth, and the uniformity of thickness is better.Follow-up by the pseudo-gate material layer 104 of etching, form across the sidewall of fin 101 and the pseudo-grid of top surface.
But, described in existing cmp in the process of sacrifice layer 103, be difficult to control the thickness of the pseudo-gate material layer 104 of formation after polishing, make the thickness of pseudo-gate material layer 104 there is uncertainty, the thickness of the pseudo-grid that form by the pseudo-gate material layer 104 of etching also has uncertainty, causes the removal degree of depth of follow-up pseudo-grid and the depth of cracking closure of metal gate to have uncertainty.
Other are about the formation method of fin formula field effect transistor, the U.S. Patent application that can also be US2011/0147812A1 with reference to publication number.
Summary of the invention
The problem that the present invention solves is accurately to control the height of the pseudo-grid of fin formula field effect transistor.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of fin formula field effect transistor, comprise: Semiconductor substrate is provided, in described Semiconductor substrate, there are some discrete fins, between adjacent fin, have isolation structure, the surface of described isolation structure is lower than the top surface of fin; Form the sacrifice layer that covers described fin and isolation structure; Described sacrifice layer is carried out to Implantation, in described sacrifice layer, form ion doped layer; Sacrifice layer described in the planarization of employing chemical mechanical milling tech, using ion doped layer as stop-layer; The remaining sacrifice layer of etching, forms the pseudo-grid across described fin top and sidewall surfaces.
Optionally, the material of described sacrifice layer is polysilicon or amorphous silicon.
Optionally, the thickness of described sacrifice layer is more than or equal to 600 nanometers.
Optionally, when the material of described sacrifice layer is polysilicon, the foreign ion of described Implantation is the one in germanium ion, silicon ion and carbon ion, the ion doped layer forming is amorphous layer, described in cmp when sacrifice layer, in the time detecting that the speed of grinding changes, stop the carrying out of grinding.
Optionally, described in cmp when sacrifice layer, when detecting that grinding rate increases gradually from certain speed, reach while reducing gradually again after maximum, stop the carrying out of grinding.
Optionally, when the material of described sacrifice layer is polysilicon or amorphous silicon, the foreign ion of described Implantation is the one in oxonium ion, nitrogen ion, arsenic ion, boron ion and antimony ion, described in cmp when sacrifice layer, in the time the change in concentration of foreign ion in lapping liquid being detected, stop the carrying out of grinding.
Optionally, described in cmp when sacrifice layer, when the concentration that the foreign ion in lapping liquid detected first increases gradually, reach while reducing gradually again after maximum, stop the carrying out of grinding.
Optionally, the energy of described Implantation is 1～20Kev, and dosage is more than or equal to 1E15/cm
2
Optionally, form encapsulant layer in described sacrificial layer surface, the depression forming to fill sacrificial layer surface, carries out Implantation to described sacrifice layer and encapsulant layer, forms ion doped layer in sacrifice layer.
Optionally, the thickness of described sacrifice layer is 30～200 nanometers.
Optionally, the foreign ion of described Implantation is germanium ion, silicon ion, carbon ion, oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion, and the energy of described Implantation is 1～20Kev, and dosage is more than or equal to 1E15/cm
2.
Optionally, described encapsulant layer is amorphous carbon.
Optionally, the thickness of described encapsulant layer is 200～400 nanometers.
Optionally, the formation technique of described encapsulant layer is flowable chemical vapour deposition (CVD).
Optionally, the main body composition of the lapping liquid that described chemical mechanical milling tech adopts is colloidal silica, and diluent is NaOH, and the quality percentage composition of colloidal silica is 10%～20%, and the pH value of lapping liquid is 10～13.
Optionally, also comprise: form the dielectric layer that covers described fin and pseudo-grid; Dielectric layer described in planarization, exposes the top surface of pseudo-grid; Remove described pseudo-grid, form groove; In groove, fill full metal, form metal gates.
Optionally, fill metal in groove before, form high-K gate dielectric layer in sidewall and the lower surface of groove, on high-K gate dielectric layer, form functional layer.
Optionally, in the fin of described metal gates both sides, form the source/drain region of fin field effect pipe.
Optionally, described source/drain region is embedded source-drain area.
Compared with prior art, technical solution of the present invention has the following advantages:
Forming after the sacrifice layer that covers described fin and isolation structure, described sacrifice layer is carried out to Implantation, in described sacrifice layer, form ion doped layer, when described in adopting chemical mechanical milling tech planarization when sacrifice layer, using ion doped layer as stop-layer, then the remaining sacrifice layer of etching, forms the pseudo-grid across described fin top and sidewall surfaces.Because ion doped layer forms by injection technology, injection technology can be controlled at the position of the ion doped layer forming in sacrifice layer comparatively accurately, when the ion doped layer in sacrifice layer as grind stop-layer time, in the process of grinding sacrifice layer, even if grinding rate can change, the thickness of remaining sacrifice layer also can be controlled more accurately, makes the height of the pseudo-grid that the remaining sacrifice layer of etching forms also more accurate.
Further, the material of described sacrifice layer is polysilicon, while carrying out Implantation, the foreign ion of injection is germanium ion, silicon ion or carbon ion, make to inject the polysilicon that ion position is corresponding decrystallized, the ion doped layer forming is amorphous layer, polysilicon is amorphous the fusing point of the amorphous layer of rear formation, density and hardness all can be starkly lower than polysilicon, due to the amorphous layer physical characteristic different from polysilicon layer, in the time carrying out cmp, the grinding rate of polysilicon can be less than the grinding rate of amorphous layer, because the amorphous layer forming is to be arranged in sacrifice layer, in the time grinding downwards from sacrificial layer surface, can there is significant change in the grinding rate while being ground to amorphous layer, therefore by detecting the rate variation of grinding in process of lapping, can judge whether to be ground to amorphous layer, thereby stop the carrying out of grinding, so that the comparatively accurate thickness of controlling remaining sacrifice layer.
Further, in the time that the material of described sacrifice layer is polysilicon or amorphous silicon, the foreign ion of described Implantation is oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion one, and described doping ion is not identical with the composition of lapping liquid and the material composition of sacrifice layer, in the ion doped region forming, contain wherein a certain doping ion (such as boron ion), ion doped layer is to be arranged in sacrifice layer, grind downwards from sacrificial layer surface, in the time being ground to ion doped layer, the concentration of certain foreign ion in lapping liquid (such as boron ion) can be grown out of nothing, and increase gradually, therefore in the time the change in concentration of foreign ion in lapping liquid being detected, stop the carrying out of grinding.
Further, the main body composition of the lapping liquid that described chemical mechanical milling tech adopts is colloidal silica, diluent is NaOH, the quality percentage composition of colloidal silica is 10%～20%, the pH value of lapping liquid is 10～13, reduce the impact of concentration impurity ion in impact on grinding rate in process of lapping or lapping liquid, be conducive to judge grinding endpoint by the variation of grinding rate or the variation of concentration impurity ion, improve the efficiency of grinding and the accuracy of grinding endpoint judgement.
Brief description of the drawings
Fig. 1～Fig. 2 is the cross-sectional view of the forming process of prior art fin formula field effect transistor;
Fig. 3～Fig. 6 is the cross-sectional view of the forming process of first embodiment of the invention fin formula field effect transistor;
Fig. 7～Figure 10 is the cross-sectional view of the forming process of second embodiment of the invention fin formula field effect transistor.
Embodiment
Inventor is adopting prior art to find in making fin formula field effect transistor process, when adopting chemical mechanical milling tech planarization sacrifice layer, because sacrificial layer surface is uneven, can make in process of lapping, the grinding rate of cmp is different, and in process of lapping, there is not grinding stop-layer, in the time being undertaken by control milling time termination grinding, make the thickness of remaining sacrifice layer (or pseudo-gate material layer) there is uncertainty, the thickness of remaining sacrifice layer and the deviation of desired value are larger, in the time that the remaining sacrifice layer of etching forms pseudo-grid, the precision of the height of pseudo-grid is significantly lowered, finally make removing pseudo-grid formation groove, and the precision of the height of the metal gates forming in groove also significantly reduces, be unfavorable for the raising of device stability and the management and control of technique.
Based on above-mentioned research, inventor proposes a kind of formation method of fin formula field effect transistor, forming after the sacrifice layer that covers described fin and isolation structure, described sacrifice layer is carried out to Implantation, in described sacrifice layer, form ion doped layer, when described in adopting chemical mechanical milling tech planarization when sacrifice layer, using ion doped layer as stop-layer, then the remaining sacrifice layer of etching, forms the pseudo-grid across described fin top and sidewall surfaces.Because ion doped layer forms by injection technology, injection technology can be controlled at the position of the ion doped layer forming in sacrifice layer comparatively accurately, when the ion doped layer in sacrifice layer as grind stop-layer time, if grind in the process of sacrifice layer, even if grinding rate can change, the thickness of remaining sacrifice layer also can be controlled more accurately, makes the height of the pseudo-grid that the remaining sacrifice layer of etching forms also more accurate.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Describing in detail when the embodiment of the present invention, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
The first embodiment
Fig. 3～Fig. 6 is the cross-sectional view of the forming process of first embodiment of the invention fin formula field effect transistor.
First, with reference to figure 3, Semiconductor substrate 300 is provided, in described Semiconductor substrate 300, there are some discrete fins 301, in Semiconductor substrate 301 between adjacent fin 301, have isolation structure 302, the surface of described isolation structure 302 is lower than the top surface of fin 301.
Described Semiconductor substrate 300 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 300 can be also germanium, germanium silicon, GaAs or germanium on insulator.
In the present embodiment, described fin 301 forms by etching semiconductor substrate 300, and in other embodiments of the invention, described fin 301 forms by epitaxy technique.
Described isolation structure 302 is for the adjacent fin 301 of electric isolation, and the material of described isolation structure 302 is silica, silicon nitride or silicon oxynitride.The detailed process that isolation structure 302 forms is: first form the spacer material layer that covers described Semiconductor substrate 300 and fin 301; Then adopt spacer material layer described in chemical mechanical milling tech planarization, taking the top surface of fin 301 as stop-layer; Then remaining spacer material layer described in etching, forms isolation structure 302, and the surface of described isolation structure 302 is lower than the top surface of fin 301.Forming isolation structure 302, be connected and can there is a groove between fin 301, so that follow-up formation is across pseudo-grid or the grid structure of the top surface of described fin 301 and the sidewall of exposure.
Then, please refer to Fig. 4, form the sacrifice layer 303 that covers described fin 301 and isolation structure 302.
The follow-up pseudo-grid that are used to form fin field effect pipe of described sacrifice layer 303, the formation technique of described sacrifice layer 303 is chemical vapor deposition (CVD), because isolation structure 302 surfaces are lower than fin 301 top surfaces, between adjacent fin 301, there is groove, therefore in the time that deposition forms sacrifice layer 303, the surface of the sacrifice layer 303 that sacrifice layer 303 surfaces that fin 301 tops form can form higher than isolation structure 302 tops, the surface that makes finally to form sacrifice layer 303 can be uneven, and the evenness on sacrifice layer 303 surfaces is poor.
In the present embodiment, the thickness of described sacrifice layer 303 is more than or equal to 600 nanometers, by forming thicker sacrifice layer 303, to reduce the impact on sacrifice layer 303 surface smoothnesss that form of difference in height between isolation structure 302 surfaces and fin 301 top surfaces, reduce the difference between the apparent height of sacrifice layer 303 of isolation structure 302 tops and the height on sacrifice layer 303 surfaces of fin 301 tops, follow-up sacrifice layer 303 is carried out to Implantation, form ion doped layer in sacrifice layer 303 time, make the uniformity of the distribution of ion doped layer in sacrifice layer 303 be subject to sacrifice layer 303 surfaces evenness affect minimum, so that the stop-layer of ion doped layer can be more accurately as planarization sacrifice layer 303 time.It should be noted that, be originally in embodiment, and the thickness of described sacrifice layer 303 refers to the thickness of the sacrifice layer 303 of fin 301 top surface tops.
The material of described sacrifice layer 303 is polysilicon or amorphous silicon, and in the present embodiment, the material of described sacrifice layer 303 is polysilicon.
Then, please refer to Fig. 5, described sacrifice layer 303 is carried out to Implantation, in described sacrifice layer 303, form ion doped layer 304.
The material of sacrifice layer 303 described in the present embodiment is polysilicon, while carrying out Implantation, the foreign ion of injection is germanium ion, silicon ion or carbon ion, make to inject the polysilicon that ion position is corresponding decrystallized, the ion doped layer 304 forming is amorphous layer, polysilicon is amorphous the fusing point of the amorphous layer of rear formation, density and hardness all can be starkly lower than polysilicon, due to the amorphous layer physical characteristic different from polysilicon layer, in the time carrying out cmp, the grinding rate of polysilicon can be less than the grinding rate of amorphous layer, in the present embodiment, because the amorphous layer (ion doped layer 304) forming is to be arranged in sacrifice layer 303, in the time grinding downwards from sacrifice layer 303 surfaces, can there is significant change in the grinding rate while being ground to amorphous layer, therefore by detecting the rate variation of grinding in process of lapping, can judge whether to be ground to amorphous layer (ion doped layer 304), thereby stop the carrying out of grinding, so that the comparatively accurate thickness of controlling remaining sacrifice layer 303.
In other embodiments of the invention, in the time that the material of described sacrifice layer 303 is polysilicon or amorphous silicon, the foreign ion of described Implantation is oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion one, and described doping ion and the composition of lapping liquid and the material composition of sacrifice layer otherwise identical, in the ion doped region 304 forming, contain wherein a certain doping ion (such as boron ion), ion doped layer 304 is to be arranged in sacrifice layer 303, grind downwards from sacrifice layer 303 surfaces, in the time being ground to ion doped layer 304, the concentration of certain foreign ion in lapping liquid (such as boron ion) can be grown out of nothing, and increase gradually, therefore in the time the change in concentration of foreign ion in lapping liquid being detected, stop the carrying out of grinding.
The energy of described Implantation is 1～20Kev, and dosage is more than or equal to 1E15/cm
2by controlling the energy of Implantation, the degree of depth of the control ion doped layer 304 forming in sacrifice layer 303 comparatively accurately, when after the Depth determination of ion doped layer 304, when sacrifice layer 303 is carried out to planarization, the thickness of remaining sacrifice layer has also just been determined, by controlling the dosage of Implantation, makes the concentration of foreign ion in ion doped layer 304 be more than or equal to 10E18/cm
3the concentration of the foreign ion to be detected when improving decrystallized degree or to grind in remaining lapping liquid, in the time being ground to ion doped layer 304, thereby improve the sensitivity that detects the change in concentration of foreign ion in grinding rate variation or lapping liquid, improve the precision of the grinding endpoint judgement detecting.
In specific embodiment, the energy of described Implantation and dosage make one's options according to the different implanting impurity ions for the treatment of, the ion doped layer 304 forming after different foreign ions is injected all can reach as the effect of grinding stop-layer, and be beneficial to the severity control of ion doped layer 304, in the time that the foreign ion injecting is germanium ion, silicon ion or carbon ion, the energy of Implantation is 5～20Kev, and dosage is more than or equal to 1E15/cm
2, in the time that the foreign ion injecting is oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion, the energy of Implantation is 1～20Kev, dosage is more than or equal to 1E15/cm
2.
Then,, with reference to figure 6, adopt sacrifice layer 303 described in chemical mechanical milling tech planarization, using ion doped layer 304 as stop-layer.
In the present embodiment, described ion doped layer 304 is amorphous layer, while adopting described in chemical mechanical milling tech planarization sacrifice layer 303, when detecting that grinding rate increases gradually from certain speed, reach while reducing gradually again after maximum, stop the carrying out of grinding, during with respect to cmp, using ion doped layer 304 as stop-layer.In the present embodiment, carry out the milling apparatus that cmp adopts and can detect in real time the rate that tests the speed of grinding, and by testing result Real-time Feedback the main control unit to milling apparatus, main control unit can send the signal that stops grinding according to the variation of grinding rate, thereby stops the carrying out of grinding.
In other embodiments of the invention, described ion doped layer 304 is during doped with the polysilicon of foreign ion or amorphous silicon, while adopting described in chemical mechanical milling tech planarization sacrifice layer 303, when the concentration that a certain foreign ion in lapping liquid detected first increases gradually, reach while reducing gradually again after maximum, stop the carrying out of grinding, during with respect to cmp, using ion doped layer 304 as stop-layer.In the present embodiment, carry out the milling apparatus that cmp adopts and have spectral detection unit, a certain concentration impurity ion in lapping liquid is determined by the variation that detects the reflectance spectrum of a certain foreign ion in lapping liquid in spectral detection unit.
The main body composition of the lapping liquid that described chemical mechanical milling tech adopts is colloidal silica, diluent is NaOH, the quality percentage composition of colloidal silica is 10%～20%, the pH value of lapping liquid is 10～13, reduce the impact of concentration impurity ion in impact on grinding rate in process of lapping or lapping liquid, be conducive to judge grinding endpoint by the variation of grinding rate or the variation of concentration impurity ion, improve the efficiency of grinding and the accuracy of grinding endpoint judgement.
In the time grinding, described ion doped layer 304 can all be ground or part residue.
Finally, after sacrifice layer described in planarization 303, the remaining sacrifice layer 303 of etching, forms the pseudo-grid (not shown) across described fin top and sidewall surfaces; Also comprise: form the dielectric layer (not shown) that covers described fin 301 and pseudo-grid; Dielectric layer described in planarization, exposes the top surface of pseudo-grid; Remove described pseudo-grid, form groove (not shown); In groove, fill full metal, form metal gates (not shown); In the fin of described metal gates both sides, form the source/drain region of fin field effect pipe.
Fill metal in groove before, form high-K gate dielectric layer in sidewall and the lower surface of groove, on high-K gate dielectric layer, form functional layer, regulate the work function of fin field effect pipe.
Described source/drain region is embedded source-drain area, to improve the performance of fin field effect pipe.
The second embodiment
Please refer to Fig. 7, Semiconductor substrate 300 is provided, in described Semiconductor substrate 300, have some discrete fins 301, in the Semiconductor substrate 301 between adjacent fin 301, have isolation structure 302, the surface of described isolation structure 302 is lower than the top surface of fin 301; Form the sacrifice layer 303 that covers described fin 301 and isolation structure 302.
In the present embodiment, the thickness of described sacrifice layer 303 is 30～200 nanometers, due to the thinner thickness of the sacrifice layer 303 forming, while adopting chemical vapor deposition method to form sacrifice layer 303, difference in height between isolation structure 302 surfaces and fin 301 top surfaces is larger on the impact of sacrifice layer 303 surface smoothnesss that form, make differing greatly between the apparent height of sacrifice layer of isolation structure 302 tops and the height of the sacrificial layer surface of fin 301 tops, surperficial uneven (depression) of sacrifice layer 303 is obvious, follow-up sacrifice layer 303 is carried out to Implantation, form ion doped layer in sacrifice layer 303 time, make the impact of the evenness that is subject to sacrifice layer 303 surfaces of the distribution of ion doped layer in sacrifice layer 303 larger, follow-up while carrying out cmp, be unfavorable for grinding the judgement that stops opportunity.
Then, please refer to Fig. 8, form encapsulant layer 307 on described sacrifice layer 303 surfaces, the depression forming to fill sacrifice layer 303 surfaces.
Described encapsulant layer 307 is amorphous carbon, the formation technique of encapsulant layer 303 is flowable chemical vapour deposition (CVD) (FCVD), in the time forming the less amorphous carbon of crystal grain, amorphous carbon has the ability of good filling depression, and makes the encapsulant layer 307 forming have more smooth surface.
The thickness of described encapsulant layer 307 is 200～400 nanometers, and follow-up while carrying out Implantation, encapsulant layer 307 is less on the impact of Implantation, makes the distribution of the ion doped layer forming in sacrifice layer 303 comparatively even.
Then, please refer to Fig. 9, described sacrifice layer 303 and encapsulant layer 307 are carried out to Implantation, in sacrifice layer 303, form ion doped layer 404.
The foreign ion of described Implantation is the one in germanium ion, silicon ion, carbon ion, oxonium ion, nitrogen ion, arsenic ion, boron ion and antimony ion.Owing to there being encapsulant layer 307, in the present embodiment, the energy of Implantation is greater than the energy that the first embodiment intermediate ion injects, to form ion doped layer 404 in sacrifice layer 303, the energy of described Implantation is 1～40Kev, and dosage is more than or equal to 1E15/cm
2.
In the present embodiment, when the material of described sacrifice layer 303 is polysilicon, while carrying out Implantation, the foreign ion of injection is germanium ion, silicon ion or carbon ion, make to inject the polysilicon that ion position is corresponding decrystallized, the ion doped layer 304 forming is amorphous layer, when follow-up grinding encapsulant layer 307 and sacrifice layer 303, in the time that grinding rate changes, can stop the carrying out of grinding.
In other embodiments of the invention, in the time that the material of described sacrifice layer 303 is polysilicon or amorphous silicon, the foreign ion of described Implantation is oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion one, and described doping ion is all not identical with the material composition of sacrifice layer 303 and encapsulant layer 307 with the composition of lapping liquid, in the ion doped region 304 forming, contain wherein a certain doping ion (such as boron ion), ion doped layer 304 is to be arranged in sacrifice layer 303, grind downwards from encapsulant layer 307 surfaces, in the time being ground to ion doped layer 304, the concentration of certain foreign ion in lapping liquid (such as boron ion) can be grown out of nothing, and increase gradually, therefore in the time the change in concentration of foreign ion in lapping liquid being detected, can stop the carrying out of grinding.
In specific embodiment, the energy of described Implantation and dosage make one's options according to the different implanting impurity ions for the treatment of, the ion doped layer 304 forming after different foreign ions is injected all can reach as the effect of grinding stop-layer, and be beneficial to the severity control of ion doped layer 304, in the time that the foreign ion injecting is germanium ion, silicon ion or carbon ion, the energy of Implantation is 5～40Kev, and dosage is more than or equal to 1E15/cm
2, in the time that the foreign ion injecting is oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion, the energy of Implantation is 1～40Kev, dosage is more than or equal to 1E15/cm
2.
With reference to Figure 10, adopt described in chemical mechanical milling tech planarization encapsulant layer 307(as shown in Figure 9) and sacrifice layer 303, using ion doped layer 304 as stop-layer.
When ion doped layer 304 is amorphous layer, because sacrifice layer 303 surfaces of the present embodiment can have encapsulant layer 307, therefore when encapsulant layer 307 and sacrifice layer 303 stacked structures grindings, first grinding rate keeps certain speed, in the time being ground to encapsulant layer 307 and sacrifice layer 303 junction, grinding rate can reduce gradually, in the time being ground to ion doped layer 304th district, grinding rate can increase gradually and the amplitude of variation of rate of change larger, while reducing gradually again, stop the carrying out of grinding after grinding rate reaches maximum.
When described ion doped layer 304 is during doped with the polysilicon of foreign ion or amorphous silicon, its process of lapping please refer to the first embodiment.
After sacrifice layer described in planarization 303, the remaining sacrifice layer 303 of etching, forms the pseudo-grid (not shown) across described fin top and sidewall surfaces; Also comprise: form the dielectric layer (not shown) that covers described fin 301 and pseudo-grid; Dielectric layer described in planarization, exposes the top surface of pseudo-grid; Remove described pseudo-grid, form groove (not shown); In groove, fill full metal, form metal gates (not shown); In the fin of described metal gates both sides, form the source/drain region of fin field effect pipe.
To sum up, the formation method of embodiment of the present invention fin field effect pipe, ion doped layer forms by injection technology, injection technology can be controlled at the position of the ion doped layer forming in sacrifice layer comparatively accurately, when the ion doped layer in sacrifice layer as grind stop-layer time, if grind in the process of sacrifice layer, even if grinding rate can change, the thickness of remaining sacrifice layer also can be controlled more accurately, makes the height of the pseudo-grid that the remaining sacrifice layer of etching forms also more accurate.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a formation method for fin field effect pipe, is characterized in that, comprising:
Semiconductor substrate is provided, has some discrete fins in described Semiconductor substrate, between adjacent fin, have isolation structure, the surface of described isolation structure is lower than the top surface of fin;
Form the sacrifice layer that covers described fin and isolation structure;
Described sacrifice layer is carried out to Implantation, in described sacrifice layer, form ion doped layer;
Sacrifice layer described in the planarization of employing chemical mechanical milling tech, using ion doped layer as stop-layer;
The remaining sacrifice layer of etching, forms the pseudo-grid across described fin top and sidewall surfaces.
2. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the material of described sacrifice layer is polysilicon or amorphous silicon.
3. the formation method of fin field effect pipe as claimed in claim 2, is characterized in that, the thickness of described sacrifice layer is more than or equal to 600 nanometers.
4. the formation method of fin field effect pipe as claimed in claim 2, it is characterized in that, when the material of described sacrifice layer is polysilicon, the foreign ion of described Implantation is the one in germanium ion, silicon ion and carbon ion, the ion doped layer forming is amorphous layer, described in cmp, when sacrifice layer, in the time detecting that the speed of grinding changes, stop the carrying out of grinding.
5. the formation method of fin field effect pipe as claimed in claim 4, is characterized in that, described in cmp when sacrifice layer, when detecting that grinding rate increases gradually from certain speed, reaches while reducing gradually after maximum again, stops the carrying out of grinding.
6. the formation method of fin field effect pipe as claimed in claim 2, it is characterized in that, when the material of described sacrifice layer is polysilicon or amorphous silicon, the foreign ion of described Implantation is the one in oxonium ion, nitrogen ion, arsenic ion, boron ion and antimony ion, described in cmp when sacrifice layer, in the time the change in concentration of foreign ion in lapping liquid being detected, stop the carrying out of grinding.
7. the formation method of fin field effect pipe as claimed in claim 6, it is characterized in that, described in cmp when sacrifice layer, when the concentration that the foreign ion in lapping liquid detected first increases gradually, reach while reducing gradually again after maximum, stop the carrying out of grinding.
8. the formation method of the fin field effect pipe as described in claim 4 or 6, is characterized in that, the energy of described Implantation is 1～20Kev, and dosage is more than or equal to 1E15/cm
2.
9. the formation method of fin field effect pipe as claimed in claim 2, it is characterized in that, also comprise: form encapsulant layer in described sacrificial layer surface, the depression forming to fill sacrificial layer surface, described sacrifice layer and encapsulant layer are carried out to Implantation, in sacrifice layer, form ion doped layer.
10. the formation method of fin field effect pipe as claimed in claim 9, is characterized in that, the thickness of described sacrifice layer is 30～200 nanometers.
The formation method of 11. fin field effect pipes as claimed in claim 9, is characterized in that, the foreign ion of described Implantation is germanium ion, silicon ion, carbon ion, oxonium ion, nitrogen ion, arsenic ion, boron ion or antimony ion.
The formation method of 12. fin field effect pipes as claimed in claim 11, is characterized in that, the energy of described Implantation is 1～40Kev, and dosage is more than or equal to 1E15/cm
2.
The formation method of 13. fin field effect pipes as claimed in claim 9, is characterized in that, described encapsulant layer is amorphous carbon.
The formation method of 14. fin field effect pipes as claimed in claim 9, is characterized in that, the thickness of described encapsulant layer is 200～400 nanometers.
The formation method of 15. fin field effect pipes as claimed in claim 9, is characterized in that, the formation technique of described encapsulant layer is flowable chemical vapour deposition (CVD).
The formation method of 16. fin field effect pipes as claimed in claim 2, it is characterized in that, the main body composition of the lapping liquid that described chemical mechanical milling tech adopts is colloidal silica, diluent is NaOH, the quality percentage composition of colloidal silica is 10%～20%, and the pH value of lapping liquid is 10～13.
The formation method of 17. fin field effect pipes as claimed in claim 1, is characterized in that, also comprises: form the dielectric layer that covers described fin and pseudo-grid; Dielectric layer described in planarization, exposes the top surface of pseudo-grid; Remove described pseudo-grid, form groove; In groove, fill full metal, form metal gates.
The formation method of 18. fin field effect pipes as claimed in claim 17, is characterized in that, before filling metal, forms high-K gate dielectric layer in sidewall and the lower surface of groove in groove, forms functional layer on high-K gate dielectric layer.
The formation method of 19. fin field effect pipes as claimed in claim 17, is characterized in that, forms the source/drain region of fin field effect pipe in the fin of described metal gates both sides.
The formation method of 20. fin field effect pipes as claimed in claim 19, is characterized in that, described source/drain region is embedded source-drain area.
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