CN113178385B - Chip manufacturing method and device and chip - Google Patents
Chip manufacturing method and device and chip Download PDFInfo
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- CN113178385B CN113178385B CN202110348496.1A CN202110348496A CN113178385B CN 113178385 B CN113178385 B CN 113178385B CN 202110348496 A CN202110348496 A CN 202110348496A CN 113178385 B CN113178385 B CN 113178385B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 238000009792 diffusion process Methods 0.000 claims abstract description 278
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 185
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 153
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 153
- 239000010703 silicon Substances 0.000 claims abstract description 153
- 229910052796 boron Inorganic materials 0.000 claims abstract description 120
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 110
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 109
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 108
- 239000011574 phosphorus Substances 0.000 claims abstract description 108
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 94
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 83
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 75
- 238000000576 coating method Methods 0.000 claims abstract description 25
- 239000011248 coating agent Substances 0.000 claims abstract description 24
- 238000005498 polishing Methods 0.000 claims description 46
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- 238000005488 sandblasting Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 8
- 239000002253 acid Substances 0.000 claims description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 112
- 238000011084 recovery Methods 0.000 description 21
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 239000007788 liquid Substances 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- -1 platinum ion Chemical class 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
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- 150000002500 ions Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000012864 cross contamination Methods 0.000 description 2
- 238000005202 decontamination Methods 0.000 description 2
- 230000003588 decontaminative effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000011160 research Methods 0.000 description 2
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- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
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- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
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- 238000005554 pickling Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- 238000003892 spreading Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Abstract
The application discloses a chip manufacturing method, manufacturing equipment and a chip, wherein the manufacturing method comprises the following steps: stacking a phosphorus source and a silicon wafer, diffusing the phosphorus source to the silicon wafer, and forming a phosphorus diffusion structure layer on at least one surface of the silicon wafer; removing the phosphorus diffusion structure layer on one surface of the silicon wafer after phosphorus diffusion; coating a gallium source on one surface of the silicon wafer with the phosphorus diffusion structure layer removed to perform gallium diffusion, so that a gallium diffusion structure layer is formed on one surface of the silicon wafer with the phosphorus diffusion structure layer removed; coating a boron source on one surface of the silicon wafer, which is provided with the gallium diffusion structure layer, so as to carry out boron diffusion, thereby forming a boron diffusion structure layer on one surface of the silicon wafer, which is free from the phosphorus diffusion structure layer; coating a platinum source on one surface of the silicon wafer with the boron diffusion structure layer to perform platinum diffusion; gallium diffusion is carried out before boron diffusion, so that the junction depth formed by a boron junction is smooth, and the voltage discreteness and the voltage drop characteristic of the conventional chip are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip manufacturing method, manufacturing equipment and a chip.
Background
The main circuit in modern power electronic circuit, whether it is a thyristor switched off by commutation or a new power electronic device with self-turn-off capability, needs a power fast recovery diode connected in parallel with it to reduce the charging time of the main switch device capacitor by the reactive current in the load and at the same time suppress the high voltage induced by the parasitic inductance when the load current is instantaneously reversed.
The production process of the semiconductor chip needs to carry out platinum expansion treatment after boron expansion and before GPP production, stir and coat a configured platinum source evenly, then load the chip into a boat, enter a furnace, discharge the furnace and cool the chip, and the problems of large voltage discreteness, poor voltage drop characteristic and the like of the chip are caused by the fact that the generated junction depth is not smooth and gentle because the boron expansion is directly carried out after phosphorus diffusion in the prior art.
Disclosure of Invention
The application aims to provide a chip manufacturing method, manufacturing equipment and a chip, and solves the problems of large voltage discreteness and poor voltage drop of the chip caused by a production process, so that the voltage distribution of the whole chip is more uniform, and the product characteristics are improved.
The application discloses a chip manufacturing method, which comprises the following steps:
stacking a phosphorus source and a silicon wafer, diffusing the phosphorus source to the silicon wafer, and forming a phosphorus diffusion structure layer on at least one surface of the silicon wafer;
removing the phosphorus diffusion structure layer on one surface of the silicon wafer after phosphorus diffusion;
coating a gallium source on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, so as to perform gallium diffusion, thereby forming a gallium diffusion structure layer on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed;
coating a boron source on one surface of the silicon wafer, which is provided with the gallium diffusion structure layer, so as to carry out boron diffusion, and thus forming a boron diffusion structure layer on one surface of the silicon wafer, which is free of the phosphorus diffusion structure layer;
coating a platinum source on one surface of the silicon wafer with the boron diffusion structure layer to perform platinum diffusion;
and preparing the chip by adopting the silicon wafer subjected to platinum diffusion.
Optionally, in the step of coating the gallium source on the surface of the silicon wafer from which the phosphorus diffusion structure layer is removed to perform gallium diffusion, and thus forming a gallium diffusion structure layer on the surface of the silicon wafer from which the phosphorus diffusion structure layer is removed, the temperature for performing gallium diffusion to form the gallium diffusion structure layer is controlled to be 1200-1300 ℃.
Optionally, the gallium source is coated on the surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, to perform gallium diffusion, so that in the step of forming a gallium diffusion structure layer on the surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, the diffusion time of the gallium diffusion is controlled to be 5 to 7 hours.
Optionally, the step of forming a platinum source on one surface of the silicon wafer on which the boron diffusion structure layer is formed to perform platinum diffusion includes:
and polishing one side of the silicon wafer on which the boron diffusion structure layer is formed.
Optionally, after the step of performing platinum ion implantation on the side of the silicon wafer on which the boron diffusion structure layer is formed to perform platinum diffusion, the method includes:
performing platinum deep diffusion in a preset temperature range;
wherein the preset temperature of the platinum during deep diffusion is controlled to be 800-950 ℃.
Optionally, the step of removing the phosphorus diffusion structure layer on one side of the silicon wafer after phosphorus diffusion comprises:
removing phosphorus diffused junctions by sand blasting;
and polishing one surface of the silicon wafer with the phosphorus diffused junctions removed, wherein the thickness of the polished silicon wafer is controlled to be 235-245 micrometers.
Optionally, the step of coating a boron source on the surface of the silicon wafer on which the gallium diffusion structure layer is formed to perform boron diffusion, so as to form a boron diffusion structure layer on the surface of the silicon wafer on which the phosphorus diffusion structure layer is removed includes:
polishing one surface of the silicon wafer containing the boron diffusion structure layer;
cleaning the polished silicon wafer by using mixed acid;
wherein the mixed acid comprises sulfuric acid, acetic acid, hydrofluoric acid, nitric acid and the like.
The application also discloses a chip, which comprises a phosphorus region, a base region and a gallium boron region, wherein the phosphorus region is the cathode of the chip; the base region is arranged on the phosphorus region; the gallium boron region is arranged on the base region and is an anode of the chip; wherein the GaB region includes a gallium junction and a boron junction.
Optionally, the gabor region includes a boron layer and a gabor layer, the boron layer includes a boron junction, and the gabor layer includes a boron junction and a gallium junction.
The application also discloses a chip manufacturing device which comprises a plurality of different diffusion devices and an ion implanter; the different diffusion devices respectively realize phosphorus diffusion, gallium diffusion, boron diffusion and platinum diffusion of the silicon wafer; wherein the chip manufacturing apparatus implements the chip manufacturing method as described above.
Compared with the scheme of directly performing boron diffusion, the gallium diffusion is performed before boron diffusion, and due to the fact that the gallium diffusion concentration is low, the junction depth formed during boron diffusion is far more gentle than that formed by direct boron diffusion, and the problems that the voltage discreteness of a chip is large and the voltage drop characteristic is poor due to the production process of the existing chip are greatly improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic flow chart of a method for manufacturing a chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional diagram of a chip provided by an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a chip provided by another embodiment of the present application;
FIG. 4 is a schematic cross-sectional diagram of a chip provided by an embodiment of the present application;
fig. 5 is a schematic diagram of a manufacturing apparatus of a chip according to an embodiment of the present application.
100, a chip; 110. polishing the surface; 120. a boron region; 130. a base region; 140. a phosphorus region; 150. a platinum ion implantation region; 160. a gallium boron region; 200. a manufacturing apparatus; 210. a diffusion device; 211. a phosphorus diffusion device; 212. a boron diffusion device; 213. a platinum diffusion device; 214. A gallium diffusion device; 220. provided is a polishing device.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and any variations thereof, are intended to cover a non-exclusive inclusion, which may have the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the drawings and alternative embodiments, and it should be noted that any combination of the embodiments or technical features described below can form a new embodiment without conflict.
As shown in fig. 1, as another embodiment of the present application, there is disclosed a method of manufacturing a chip, including the steps of:
s1: stacking a phosphorus source and a silicon wafer, diffusing the phosphorus source to the silicon wafer, and forming a phosphorus diffusion structure layer on at least one surface of the silicon wafer;
s2: removing the phosphorus diffusion structure layer on one surface of the silicon wafer after phosphorus diffusion;
s3: coating a gallium source on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, so as to perform gallium diffusion, and forming a gallium diffusion structure layer on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed;
s4: coating a boron source on one surface of the silicon wafer, which is provided with the gallium diffusion structure layer, so as to carry out boron diffusion, and thus forming a boron diffusion structure layer on one surface of the silicon wafer, which is free of the phosphorus diffusion structure layer;
s5: a platinum source is arranged on one surface of the silicon wafer, on which the boron diffusion structure layer is formed, so as to perform platinum diffusion;
s6: and preparing the chip by adopting the silicon wafer subjected to platinum diffusion.
Carry out gallium earlier and expand before boron diffusion, because gallium diffusion concentration is low, the junction depth that the junction that forms is far more gentle than direct boron diffusion, improved the voltage dispersion and the surge ability of current fast recovery diode product greatly, improve the pressure drop characteristic of chip simultaneously, can specifically refer to following table one:
| voltage distribution | Surge device | Pressure drop | |
| Normal Material 42mil | 190-210V | 45-60 | 1.4-1.6 |
| Experimental Material 42mil | 195-205V | 50-65 | 1.3-1.5 |
In the first table, the normal material is not subjected to gallium diffusion before boron diffusion, and the experimental material is subjected to gallium diffusion before boron diffusion; when the gallium diffusion is carried out, a liquid gallium source is generally selected, the gallium diffusion can be carried out by selecting a gallium ion implantation mode, the diffusion temperature range is 1200-1300 ℃, the diffusion time is 5-7H, the proper temperature and diffusion time ensure the efficiency and uniformity of the gallium diffusion, and the formed gallium junction is not only smooth in junction depth but also more uniform.
Specifically, in step S1, specifically, the following steps may be performed: before phosphorus diffusion, decontamination treatment is carried out on the surfaces of silicon wafers, a phosphorus paper source and the decontaminated silicon wafers are stacked and placed in a diffusion furnace for diffusion reaction, generally, a piece of phosphorus paper source is added between the two silicon wafers, phosphorus in the phosphorus paper source diffuses towards the upper silicon wafer and the lower silicon wafer, and after phosphorus diffusion is carried out on the silicon wafers, a phosphorus diffusion structure layer is formed on one surface, which is in contact with the phosphorus paper source, of each silicon wafer. The thickness of the silicon wafer before and after phosphorus diffusion keeps the original silicon wafer thickness, the original silicon wafer thickness ranges from 245um to 255um, the two silicon wafers forming the phosphorus diffusion structure layer can respectively perform the steps after phosphorus diffusion, wherein the decontamination treatment can be, for example: and (3) pickling and cleaning the silicon wafer to remove dirt, an oxide layer and the like on the surface of the silicon wafer.
In the step S2, removing a phosphorus diffusion junction on one surface of the silicon wafer subjected to phosphorus diffusion through sand blasting, and polishing one surface of the silicon wafer subjected to phosphorus diffusion junction removal, wherein the thickness of the polished silicon wafer is controlled to be 235-245 micrometers, and the silicon wafer is also polished before boron diffusion, so that the boron diffusion is more uniform, and the yield of products is improved; the thickness of the silicon wafer before sand blasting is 245-255, the thickness of the silicon wafer can be reduced by about 10 microns through sand blasting, the effect of subsequent platinum ion diffusion is prevented from being influenced due to too thick thickness of the silicon wafer, in addition, phosphorus diffusion junctions and phosphorus diffusion sources in a phosphorus diffusion structure layer are removed through sand blasting, the next step is carried out after removal, the influence of the phosphorus diffusion junctions on polishing is prevented, and junction depth and thickness change of boron junctions are caused by residual phosphorus diffusion sources.
The silicon wafer can be polished before the phosphorus is diffused, so that the silicon wafer can be polished on the premise of ensuring that the silicon wafer is not damaged, the surface of the silicon wafer, which is in contact with the phosphorus, is smoother, and the phosphorus is diffused more uniformly.
In step S3, a boron source is coated on one surface of the silicon wafer on which the gallium diffusion structure layer is formed to perform boron diffusion, so that a boron diffusion structure layer is formed on one surface of the silicon wafer on which the phosphorus diffusion structure layer is removed; the method specifically comprises the following steps: and coating a liquid boron source on one surface of the silicon wafer with the phosphorus diffusion structure layer removed, and putting the silicon wafer into a diffusion furnace for diffusion reaction, wherein the boron diffusion structure layer is formed after the gallium is diffused, so that the boron junction depth in the boron diffusion structure layer is more gradual.
Before step S4, polishing the surface of the boron diffusion structure layer to form a first polished surface, where the thickness of the silicon wafer on which the first polished surface is formed after polishing is reduced by 3 to 5 micrometers compared with the thickness of the silicon wafer before polishing, where the polishing thickness is represented by X, and controlling the polishing thickness can further improve the recovery characteristics, specifically referring to the following table two:
watch 2
In step S5, a liquid platinum source is uniformly coated on the first polishing surface to perform platinum diffusion, and the temperature in the diffusion furnace is controlled to be 800-950 ℃, so that the liquid platinum source can be more uniformly coated on the polishing surface, and the platinum can be more uniformly diffused after the liquid platinum source is uniformly coated. The temperature is controlled to be 800-950 ℃, so that boron junctions cannot be deeper, the integral structure of the silicon wafer cannot be influenced, and the change of the TRR value caused by the surface concentration transformation cannot be influenced, so that the recovery characteristic is influenced.
Generally, this application is important, carry out the boron diffusion behind the gallium diffusion, form more gentle PN junction, carry out platinum ion implantation at the silicon chip that the surface is the boron junction, when carrying out the platinum diffusion, platinum can be even spread in the silicon chip, carry out platinum deep diffusion in a predetermined temperature range, platinum that is evenly spread to each region of silicon chip, prevent that platinum from spreading other structures in the inhomogeneous destruction silicon chip, platinum has fabulous turn-on velocity simultaneously, preventing that platinum from distributing the original structure of inhomogeneous destruction silicon chip, can also improve the recovery characteristic of chip simultaneously.
Generally, step S5 may further include: and introducing nitrogen at the rate of 5-7L/min during platinum diffusion, wherein the nitrogen is pure nitrogen to prevent other gases from entering and influencing the diffusion uniformity.
In step S6, a chip is prepared by using a silicon wafer after platinum diffusion, which may specifically be: and etching, sintering, coating and the like are carried out on the silicon wafer subjected to platinum diffusion to prepare the chip. The chip prepared by using the silicon wafer after platinum diffusion can be a fast recovery diode and the like.
In the embodiment, the surface for platinum diffusion is polished and then coated with the liquid platinum source, so that the liquid platinum source can be more uniformly distributed on the surface for platinum diffusion, and the diffusion can be more uniform. However, because the polishing cost is too high and the platinum is not used excessively, researches show that the internal structure of the silicon wafer is greatly influenced by the non-uniform platinum diffusion, and the internal structure is damaged when the platinum is not uniform, the polishing treatment is carried out before the platinum is diffused so as to prevent the internal structure of the silicon wafer from being damaged by the non-uniform platinum diffusion, and meanwhile, the rapid recovery diode has an outstanding effect on the recovery characteristic of the rapid recovery diode after the platinum is uniformly diffused.
As another embodiment of the present application, there is disclosed a method of manufacturing a chip, including the steps of:
s1: stacking a phosphorus source and a silicon wafer, diffusing the phosphorus source to the silicon wafer, and forming a phosphorus diffusion structure layer on at least one surface of the silicon wafer;
s2: removing the phosphorus diffusion structure layer on one surface of the silicon wafer after phosphorus diffusion;
s3: coating a gallium source on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, so as to perform gallium diffusion, and forming a gallium diffusion structure layer on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed;
s41: coating a boron source on one surface of the silicon wafer, which is provided with the gallium diffusion structure layer, so as to carry out boron diffusion, and thus forming a boron diffusion structure layer on one surface of the silicon wafer, which is free of the phosphorus diffusion structure layer;
s42: polishing one surface of the silicon wafer containing the boron diffusion structure layer;
s51: performing platinum source coating injection on one surface of the silicon wafer on which the boron diffusion structure layer is formed to perform platinum diffusion;
s52: performing platinum deep diffusion in a preset temperature range;
s6: and preparing the chip by adopting the silicon chip subjected to platinum diffusion.
The platinum is used as a heavy metal, the internal structure of the silicon wafer can be seriously damaged if the platinum is unevenly diffused in the silicon wafer, platinum ions are implanted into the silicon wafer with the boron junction on the surface for platinum diffusion, so that the platinum diffusion is more uniform, the original structure of the silicon wafer is prevented from being damaged due to uneven platinum distribution, and the recovery characteristic of the chip is improved.
We can carry out the polishing on the one side that platinum expands for the platinum diffusion surface is smooth even, carries out platinum diffusion in a predetermined temperature range in addition, so when platinum diffusion, platinum can each region of more even diffusion to the silicon chip, prevents that platinum ion diffusion is inhomogeneous to destroy other structures in the silicon chip, and platinum has fabulous conduction velocity simultaneously, prevents that platinum distributes inhomogeneous original structure of destroying the silicon chip, can also improve the recovery characteristic of chip simultaneously, can refer to table three below:
| take 200V SF50mil product as an example | TRR |
| Normal abrasive sheet (unpolished) | 29-35 |
| Experimental polishing pad (polishing) | 30-32 |
Watch III
Wherein TRR is the reverse recovery time of the diode, the diode can reversely flow current in the process of conducting in the forward direction to blocking in the reverse direction, the time required by the recombination of internal carriers is TRR, the TRR value generally refers to the standard of 30-35, the more concentrated the TRR value in the standard range represents the better recovery characteristic, namely the less discrete recovery characteristic is high, after polishing, the TRR value is obviously superior to the non-polished TRR value,
in addition, in step S42, the polished silicon wafer is cleaned, and the residues on the polished surface are removed by cleaning, so that the polished surface can be cleaner and smoother, and the surface smoothness of the polished surface is not affected, and the thickness of the polished silicon wafer is smaller than that of the silicon wafer before polishing by 3-5 microns, and the polishing thickness is represented by X, and the recovery characteristic that the polishing thickness can be controlled is further improved, specifically referring to the following table four:
watch four
As can be seen from the table, if the polishing thickness is less than 3 microns or greater than 5 microns, the standard cannot be met, the recovery characteristic is weaker than that of a chip with the thickness of 3-5 microns, and if the thinning thickness is too large, platinum ions directly diffuse through a silicon wafer, so that the whole silicon wafer is completely scrapped.
Through the embodiment, the polishing can enable the diffusion surface to be diffused to be smooth, the diffusion surface can be more uniform in the diffusion process, however, the polishing cost is too high, excessive use is avoided generally, researches show that platinum diffusion nonuniformity has large influence on the internal structure of the silicon wafer, the internal structure can be damaged in the nonuniform process, and therefore before platinum diffusion, polishing is conducted to prevent the platinum diffusion nonuniformity from causing damage to the internal structure of the silicon wafer, and meanwhile, the recovery characteristic of the fast recovery diode has a prominent effect after platinum diffusion is uniform.
As another embodiment of the present application, there is disclosed a method of manufacturing a chip, including the steps of:
(1) Treating the surface of a primary silicon wafer, and immersing the primary silicon wafer into hydrofluoric acid for acid cleaning;
(2) Stacking the processed silicon wafer and a phosphorus paper source together, placing the silicon wafer and the phosphorus paper source together in a diffusion furnace after arrangement, so that the phosphorus source is diffused to the silicon wafer, and forming a phosphorus diffusion structure layer on at least one surface of the silicon wafer;
(3) Putting the silicon wafer from which phosphorus is diffused into hydrofluoric acid for slicing treatment and cleaning treatment;
(4) Carrying out sand blasting treatment on the silicon wafer after the phosphorus fragmentation to remove phosphorus diffusion junctions, and controlling the thickness of the silicon wafer to be 235-245um;
(5) Cleaning the material subjected to sand blasting, and coating a boron source on one surface of the silicon wafer, which is provided with the gallium diffusion structure layer, so as to carry out boron diffusion, thereby forming a boron diffusion structure layer on one surface of the silicon wafer, which is free of the phosphorus diffusion structure layer;
(6) And (3) polishing the surface of the boron zone surface of the boron-expanded material to be about 3-5um, and cleaning after polishing.
(7) Coating the polished silicon wafer with a liquid platinum source, uniformly coating the platinum source on the polished surface, and performing platinum diffusion after coating, wherein the temperature is controlled at 800-950 ℃.
(8) After platinum diffusion, the silicon wafer is cleaned, coated with photoresist, exposed and developed, and then etched by mixed acid at the temperature of-5-1 ℃ to form a groove.
(9) And preparing the chip by adopting the silicon wafer subjected to platinum diffusion.
Wherein the step (9) is followed by the following specific steps:
(91): after the trench was opened, the chip was RCA cleaned, and then LPCVD was performed to form a SIPOS film (semi-insulating polysilicon film) on the surface.
(92) And (4) coating photoresist glass after SIPOS, and carrying out glass sintering after exposure and development.
(93) LTO (low temperature oxidation) is performed after glass sintering to grow a silicon dioxide film.
(94) And (4) removing the mesa oxide layer of the chip after the step (11) through gluing, exposing and developing.
(95) And (4) carrying out primary nickel plating, sintering, carrying out secondary nickel plating and then carrying out gold plating on the chip obtained in the step (12).
(96) After gold plating, the chip is cut into single crystal grains by a laser cutting machine.
(97) The grains are cleaned and then packaged.
Wherein, in the step (1), the surface dirt, oxide layer and the like of the original silicon wafer are mainly removed, in the step (2), when phosphorus is diffused, the temperature is 1150-1250 ℃, oxygen 2.5LPM nitrogen 10LPM is introduced according to the proportion of 1; boron diffusion, namely in the step (5), introducing oxygen 12LPM and nitrogen 3LPM according to the ratio of 4; the surface polishing treatment is added after boron expansion, so that the surface is smoother, a platinum source can be enabled to be a more uniform and flat polishing surface in the platinum coating process, finally, the TRR value of the whole silicon wafer is more uniform, and the discreteness is small.
In the step (8), the mixed acid comprises the following components in a ratio of 9:9:12:7 nitric acid, hydrofluoric acid, acetic acid and sulfuric acid.
As another embodiment of the present application, a method for manufacturing a chip is disclosed, which is different from the above embodiments in that a material after sandblasting is cleaned, a gallium material is added, and gallium diffusion is performed; then, the related steps such as boron-phosphorus diffusion and the like are carried out.
Wherein, before the gallium diffusion or the boron diffusion, the polishing treatment can be carried out so as to lead the diffusion to be more uniform; in all the embodiments, the gallium diffusion and the boron diffusion can be performed simultaneously, and the gallium material and the boron material are added into the same diffusion furnace at the same time, so that the time of the manufacturing method can be saved, the production efficiency can be improved, and the PN junction can be formed more smoothly by performing the diffusion at the same time.
As shown in fig. 2, as another embodiment of the present application, a chip is disclosed, which includes a phosphorus region 140, a base region 130, and a gallium boron region 160, where the phosphorus region 140 is a cathode of the chip; the base region 130 is disposed on the phosphor region; the gallium boron region 160 is arranged on the base region and is the anode of the chip; wherein the gallium boron region comprises a gallium junction and a boron junction.
Further, the gallium-boron region comprises a boron layer and a gallium-boron layer, the boron layer comprises a boron junction, the gallium-boron layer comprises a boron junction and a gallium junction, and gallium diffusion is carried out to form the gallium junction before boron diffusion to form the boron junction, so that the boron junction formed during boron diffusion can be more gentle.
As shown in fig. 3 and 4, as another embodiment of the present application, a chip 100 is disclosed, which includes a phosphorus region 140, a base region 130, and a boron region 120, wherein the phosphorus region 140 is a cathode of the chip; the base region 130 is disposed on the phosphor region; the boron region 120 is arranged on the base region and is an anode of the chip; and a polishing surface is formed on one surface of the boron region far away from the base region, and platinum is uniformly distributed in each region after being diffused from the polishing surface.
The polishing surface is formed before platinum diffusion, so that the platinum can be more uniformly diffused into the silicon wafer during the platinum diffusion, the TRR value is more uniform, and a chip with good recovery characteristics is obtained.
As shown in fig. 5, as another embodiment of the present application, a chip manufacturing apparatus 200 is disclosed, which includes a plurality of different diffusion devices 210, the plurality of different diffusion devices 210 respectively implementing phosphorus diffusion, gallium diffusion, boron diffusion and platinum diffusion of a silicon wafer;
the manufacturing apparatus further includes an ion implanter and polishing device 220; the polishing device is used for polishing the silicon wafer subjected to boron diffusion; the manufacturing equipment of the chip uses the manufacturing method in any embodiment to manufacture the chip, and the ion implanter performs platinum ion implantation on a silicon wafer with a boron junction on the surface after boron diffusion, and performs platinum diffusion.
It should be noted that the above-mentioned phosphorus diffusion, boron diffusion and platinum diffusion are all performed in different diffusion furnaces, and each diffusion is performed in a separate diffusion furnace to prevent mutual contamination, and it is noted that the phosphorus diffusion cannot be performed in the same diffusion furnace because the product from the boron source is wasted.
The plurality of diffusion devices 210 are respectively a phosphorus diffusion device 211 for phosphorus diffusion, a boron diffusion device 212 for boron diffusion, a platinum diffusion device 213 for platinum diffusion and a gallium diffusion device 214 for gallium diffusion, each diffusion device is independent, cross contamination caused by sharing one diffusion device is prevented, the production yield of products is influenced, generally, gallium diffusion is carried out before boron diffusion, the formed junction is far more gentle than the junction depth formed by direct boron diffusion, the voltage discreteness and surge capacity of the existing fast recovery diode product are improved, and meanwhile, the voltage drop characteristic of the fast recovery diode is improved; of course, the gallium diffusion and the boron diffusion can be carried out in a single diffusion furnace without cross-contamination with each other.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (8)
1. A method of manufacturing a chip, comprising the steps of:
stacking a phosphorus source and a silicon wafer, diffusing the phosphorus source to the silicon wafer, and forming a phosphorus diffusion structure layer on at least one surface of the silicon wafer;
removing the phosphorus diffusion structure layer on one surface of the silicon wafer after the phosphorus diffusion and polishing;
coating a gallium source on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, so as to perform gallium diffusion, and forming a gallium diffusion structure layer on one surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed;
coating a boron source on one surface of the silicon wafer, which is provided with the gallium diffusion structure layer, so as to carry out boron diffusion, and thus forming a boron diffusion structure layer on one surface of the silicon wafer, which is free of the phosphorus diffusion structure layer;
polishing one surface of the silicon wafer containing the boron diffusion structure layer;
coating a platinum source on one surface of the silicon wafer, which is provided with the boron diffusion structure layer, so as to perform platinum diffusion, and thus platinum atoms are uniformly distributed in the silicon wafer;
preparing a chip by adopting the silicon wafer subjected to platinum diffusion;
the gallium diffusion is carried out firstly, the diffusion time of the gallium diffusion is controlled to be 5-7 hours, and the boron diffusion is carried out after the gallium diffusion is finished;
the thickness of the silicon wafer after polishing treatment of the side of the boron diffusion structure layer formed after boron diffusion is 3-5 microns smaller than that before polishing.
2. The method for manufacturing a chip according to claim 1, wherein in the step of applying a gallium source to a side of the silicon wafer from which the phosphorus diffusion structure layer is removed to perform gallium diffusion, thereby forming a gallium diffusion structure layer on the side of the silicon wafer from which the phosphorus diffusion structure layer is removed, the temperature required for performing gallium diffusion to form the gallium diffusion structure layer is controlled to be 1200 to 1300 ℃.
3. The method for manufacturing a chip as claimed in claim 1, wherein the step of performing platinum diffusion by polishing a side of the silicon wafer on which the boron diffusion structure layer is formed comprises:
performing platinum deep diffusion in a preset temperature range;
wherein the preset temperature of the platinum during deep diffusion is controlled to be 800-950 ℃.
4. The method for manufacturing the chip as claimed in claim 1, wherein the step of removing the phosphorus diffusion structure layer on one side of the silicon wafer after the phosphorus diffusion comprises:
removing phosphorus diffused junctions by sand blasting;
and polishing one surface of the silicon wafer with the phosphorus diffused junctions removed, wherein the thickness of the polished silicon wafer is controlled to be 235-245 microns.
5. The method for manufacturing the chip according to claim 1, wherein the step of coating the boron source on the side of the silicon wafer with the gallium diffusion structure layer to perform boron diffusion so as to form the boron diffusion structure layer on the side of the silicon wafer with the phosphorus diffusion structure layer removed comprises the following steps:
polishing one surface of the silicon wafer containing the boron diffusion structure layer;
cleaning the polished silicon wafer by using mixed acid;
wherein the mixed acid comprises sulfuric acid, acetic acid, hydrofluoric acid and nitric acid.
6. A chip produced by the method for producing a chip according to any one of claims 1 to 5, comprising:
a phosphorus region which is a cathode of the chip;
a base region disposed on the phosphorus region;
the gallium boron region is arranged on the base region and is an anode of the chip;
wherein the gallium boron region comprises a gallium junction and a boron junction.
7. The chip of claim 6, wherein the GaB region comprises a boron layer comprising a boron junction and a GaB layer comprising a boron junction.
8. An apparatus for manufacturing a chip, comprising:
the different diffusion devices are used for respectively realizing phosphorus diffusion, gallium diffusion, boron diffusion and platinum diffusion of the silicon wafer;
wherein the manufacturing apparatus of the chip implements the manufacturing method of the chip according to any one of claims 1 to 5.
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