CN101359595A - Method for flattening wafer surface - Google Patents
Method for flattening wafer surface Download PDFInfo
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- CN101359595A CN101359595A CNA2007100443866A CN200710044386A CN101359595A CN 101359595 A CN101359595 A CN 101359595A CN A2007100443866 A CNA2007100443866 A CN A2007100443866A CN 200710044386 A CN200710044386 A CN 200710044386A CN 101359595 A CN101359595 A CN 101359595A
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Abstract
The invention discloses a method for smoothening the surface of a wafer, including the following steps: providing a wafer which is provided with a medium layer on the surface and is composed of a central area and a marginal area surrounding the central area; removing the medium layer at the marginal area; and chemically and mechanically rubbing the whole medium layer on the surface of the wafer; wherein the thickness of the medium layer at the marginal area after being rubbed by a test piece is bigger than the depth of the etched through hole; and the removed thickness of the medium layer at the marginal area is larger than or equal to the average thickness difference tested by a test piece between the medium layer at the central area and the marginal area of the chemically and mechanically rubbed wafer. The method for smoothening the surface of the wafer reduces thickness difference between the medium layer at the central area and the marginal area of the wafer after chemically and mechanically rubbing the surface of the medium layer on the surface of the wafer, thus improving the smoothness of the surface of the wafer.
Description
Technical field
The present invention relates to a kind of method of flattening wafer surface.
Background technology
In the manufacture craft of large scale integrated circuit and very lagre scale integrated circuit (VLSIC), for closeness and its speed of service that will improve element, the element of semiconductor crystal wafer, metal connecting line, the structure that distributes in order to the isolated component groove all needs through design, to meet the requirement of various elements even.But these elements and structure often are not equally distributed on the surface of semiconductor crystal wafer, thereby have the comparatively dense intensive element region of some elements and structure and element and the comparatively sparse loose element region of structure distribution.Therefore on the other hand, these elements and structure all have certain thickness, can make the profile that the surface of semiconductor crystal wafer has some just to rise and fall.Therefore, just need carry out the step of planarization.
At present the most frequently used planarisation step is to use chemical mechanical milling method to carry out, and utilizes some chemical reagent as grinding slurry, and wafer to be ground is fixed on the bistrique, has on the grinding table of grinding pad crystal column surface is carried out comprehensive grinding on one.For example, the patent No. is the method that the Chinese patent of ZL 98123006.7 discloses a kind of flattening surface, be included in before the surface of carrying out chemical mechanical milling method planarization wafer, above insulating barrier, apply one deck spin-on glasses, and carry out hot baking procedure, make crystal column surface comparatively smooth, grind crystal column surface with chemical mechanical milling method again.
Yet; existing use chemical mechanical milling method carries out the method for planarization because the relation of abrasive disc speed generally all can't reduce to the thickness of crystal round fringes the thickness of requirement fully; the dielectric layer regular meeting at the edge of wafer is many on the medium bed thickness than crystal circle center zone because planarization is incomplete; and more near crystal round fringes; thickness is big more; like this at subsequent technique; for example will make through hole can't be communicated with the material layer that should be communicated with etching vias the time, and make the circuit on the wafer open circuit occur.Therefore, how to make the flatening process of crystal round fringes fully just become a major issue that must solve.
Summary of the invention
The present invention promptly is in order to solve the problem that the prior art crystal round fringes can't reach the planarization requirement.
For addressing the above problem, the invention provides a kind of method of flattening wafer surface, the wafer that provides the surface to have dielectric layer is provided, comprise the central area and around the fringe region of central area; Remove the dielectric layer of fringe region part thickness; Dielectric layer for whole crystal column surface carries out cmp; Wherein said fringe region is that the dielectric layer zone of back thickness of dielectric layers greater than the etching vias degree of depth ground in test piece, the fringe region dielectric layer remove thickness more than or equal to the cmp that records by test piece after the average thickness gap of dielectric layer in the dielectric layer in crystal circle center zone and crystal round fringes zone.
The dielectric layer of described removal crystal round fringes segment thickness adopts etching method.
The etched process of described dielectric layer for crystal round fringes comprises the following steps,
On the dielectric layer of crystal column surface, form photoresist layer; Photoresist layer exposure, development for crystal round fringes form the photoresist recess; With the photoresist layer is mask, removes the dielectric layer of segment thickness for the dielectric layer etching of crystal round fringes in the photoresist indent; Remove photoresist layer.
Described photoresist layer exposure for crystal round fringes adopts high-pressure mercury lamp, excimer laser, X ray or electron beam as exposure light source.
Described dielectric layer for crystal round fringes develops and forms employing dry process development of photoresist recess or wet development.
Dry etching or wet etching are adopted in described dielectric layer etching for crystal round fringes.
Photoresist layer on the described removal wafer adopts dry method in conjunction with wet chemical process.
Compared with prior art, such scheme has the following advantages: such scheme is by carrying out the dielectric layer of etching removal segment thickness earlier for the dielectric layer of crystal round fringes before carrying out cmp at the dielectric layer for crystal column surface, revise that prior art only adopts cmp and the dielectric layer of crystal round fringes and the thickness of dielectric layers gap in crystal circle center zone after the grinding that causes, thereby make the dielectric layer of crystal column surface through after the cmp, the thickness of dielectric layers gap in the dielectric layer of crystal round fringes and crystal circle center zone is dwindled, even can be, thereby have improved the flattening wafer surface degree so that the thickness of dielectric layers of crystal round fringes reaches the specification requirement that equates with the thickness in crystal circle center zone.
Description of drawings
Fig. 1 is an embodiment of the invention flattening wafer surface method flow diagram;
Fig. 2 is that the embodiment of the invention is removed the segment thickness flow chart for the crystal round fringes dielectric layer;
Fig. 3 to Fig. 9 is an embodiment of the invention flattening wafer surface method schematic diagram.
Embodiment
The essence of flattening wafer surface method of the present invention is that first dielectric layer for the crystal round fringes zone carries out the dielectric layer that etching removes segment thickness before the dielectric layer for crystal column surface carries out cmp, reach the purpose of revising for the thickness disparity of the dielectric layer in dielectric layer that grinds crystal round fringes zone, back and crystal circle center zone, wherein said fringe region is that the dielectric layer zone of back thickness of dielectric layers greater than the etching vias degree of depth ground in test piece, and dielectric layer is removed the average thickness gap of thickness more than or equal to the dielectric layer in the dielectric layer in the crystal circle center zone that records by test piece and crystal round fringes zone.
Come to be elaborated below by preferred embodiment for the method for flattening wafer surface of the present invention.
Described with reference to Fig. 1, embodiment of the invention flattening wafer surface method comprises the following steps,
Step s1, the wafer that provides the surface to have dielectric layer comprises the central area and around the fringe region of central area;
Step s2, the dielectric layer of removal crystal round fringes area part thickness;
Step s3 carries out cmp for the dielectric layer of whole crystal column surface;
Wherein said fringe region is that the dielectric layer zone of back thickness of dielectric layers greater than the etching vias degree of depth ground in test piece, described dielectric layer remove thickness more than or equal to the cmp that records by test piece after the average thickness gap of dielectric layer in the dielectric layer in crystal circle center zone and crystal round fringes zone.
With reference to shown in Figure 2, the embodiment of the invention comprises the following steps for crystal round fringes zone dielectric layer removal method,
Step s21 forms photoresist layer on the dielectric layer of crystal column surface;
Step s22 is for photoresist layer exposure, the development formation photoresist recess in crystal round fringes zone;
Step s23 is a mask with the photoresist layer, in the dielectric layer etching of photoresist indent for crystal column surface;
Step s24 removes photoresist layer.
Be described in detail below in conjunction with the method for concrete technology for flattening wafer surface of the present invention.
In conjunction with Fig. 1 and shown in Figure 3, the wafer 20 that provides the surface to have dielectric layer 21.In semiconductor technology, before wafer 20 carries out each procedure, all can clean and dry for wafer 20 surfaces because wafer 20 in being transferred into etching machines before, all may be adsorbed onto some particulate contaminants, and these pollutants must be removed.According to the grade of polluting and the needs of technology, can be with several different particulate sweep-out methods, for example, manually air-blowing, machinery are scrubbed water under high pressure splash and wet chemical cleaning.
In conjunction with Fig. 2 and Fig. 4 to Figure 8 shows that the embodiment of the invention removes the method for segment thickness for crystal round fringes zone dielectric layer.
In conjunction with Fig. 2 and shown in Figure 4, after the cleaning and drying finished for crystal column surface, on the dielectric layer 21 on wafer 20 surfaces, form photoresist layer 22.Form photoresist layer and on dielectric layer 21, coat the skim photoresist in fact exactly equably.The method of conventional gluing has brush method, spin coating method and infusion method etc.Wherein, a kind of method of smearing photoresist of optimizing is dynamically to spray the gluing method, before resist coating, wafer 20 can be attracted on the sucker and with lower rotating speed, 500rpm low speed rotation for example, afterwards, wafer 20 surfaces constantly exported and are sprayed at by photoresist by transmission pipeline.The effect of low speed rotation is to help the initial even diffusion of photoresist.After photoresist extended, sucker will drive the wafer high speed rotating and finish final photoresist expansion, thereby obtained thin and uniform photoresist film.
In conjunction with Fig. 2 and shown in Figure 5, after forming photoresist layer 22, for the photoresist layer 22 at the wafer 20 edges formation photoresist recess that exposes, develops.On technology realizes, all be to make mask accurately aim at generally, expose for photoresist layer then with wafer.In the embodiment of the invention, need not to use mask, only need expose and get final product the photoresist layer 22 in wafer 20 fringe regions, as previously mentioned, described fringe region is that the dielectric layer zone of back thickness of dielectric layers greater than the etching vias degree of depth ground in test piece, the present embodiment clock, described fringe region is to the wide annular region of the 2-5mm at wafer 20 centers from wafer 20 edges, the width of wherein said annular region is 2mm or 4mm or 5mm, more preferably be 4mm, make the photoresist in this annular region be subjected to light from soluble to solvable by exposure.At present, exposure light source commonly used has high-pressure mercury lamp, excimer laser, X ray or electron beam.
In conjunction with Fig. 2 and shown in Figure 6, after the exposure of having finished for the photoresist layer 22 at wafer 20 edges, developing for the photoresist layer 22 at wafer 20 edges forms the photoresist recess.Use wet development or dry process development that soluble photoresist is removed in the embodiment of the invention and form the photoresist recess.
In conjunction with Fig. 2 and shown in Figure 7, finishing after exposure imaging forms the photoresist recess, be mask with photoresist layer 22, the operation of removing segment thickness for the dielectric layer 21 on wafer 20 surfaces in the photoresist indent.Remove segment thickness for dielectric layer 21 in the embodiment of the invention and adopt etching method.The thickness of dielectric layers that embodiment of the invention etching is removed is to be determined by the thickness disparity of the dielectric layer of the dielectric layer in crystal circle center zone behind the cmp that records by the section experiment before the etching and crystal round fringes in fact.Described section experiment was meant before carrying out cmp for the crystal column surface dielectric layer; elder generation carries out cmp with the wafer test piece that a slice has the same media layer; the thickness of the dielectric layer of the thickness of the dielectric layer in crystal circle center zone and crystal round fringes after measurement is ground then; as previously mentioned; because the relation of abrasive disc speed, the dielectric layer of crystal round fringes are many on usually can the medium bed thickness than crystal circle center zone.And just can obtain the average thickness gap of the dielectric layer in the dielectric layer of crystal round fringes and crystal circle center zone, and with the minimum thickness of this average thickness gap as removal dielectric layer 21 according to the thickness of the dielectric layer in the dielectric layer of the crystal round fringes that measures of section experiment and crystal circle center zone.
Give an example for one as the embodiment of the invention, the average thickness gap of supposing the dielectric layer of the dielectric layer in the crystal circle center zone that records by slice test and crystal round fringes is about 2000 dusts, and the thickness of the dielectric layer removed of etching need be more than or equal to 2000 dusts so.Here the dielectric layer with etching 2000 dusts is an example, and at present, etch process has two big classes: wet etching and dry etching.Wherein wet etching has methods such as silicon wet etching, silicon dioxide wet etching, aluminium film wet etching, deposited oxide wet etching, silicon nitride wet etching, wet spraying etching and vapor etch.And dry etching has methods such as plasma etching, ion beam milling and reactive ion etching.Etch process can be decided according to the material that concrete needs carry out etched dielectric layer 21.And the thickness of the dielectric layer of removing according to the etch-rate of the etch process that adopts and in conjunction with the etching needs just can obtain the required time of etching, for example etching removal thickness is 2000 dusts, just can obtain etching in conjunction with etch-rate again and remove the required etching period of 2000 dust thickness.In conjunction with before described, after the photoresist indent reaches described etching period for the etching of dielectric layer 21, the dielectric layer 21 of crystal round fringes just has been removed 2000 dusts, and wafer 20 surfaces will form middle height as shown in Figure 9, low step surface all around like this.
In conjunction with Fig. 2 and shown in Figure 8, remove photoresist layer after finishing for the etching of the dielectric layer 21 at wafer 20 edges having finished.Through after the etching, no longer needed as the photoresist layer 22 of etch stop layer, therefore just need remove from wafer 20 surfaces, more common method is with wet chemical process it to be removed.And the method that present embodiment adopts is the chemical technology removal photoresist of dry method in conjunction with wet method.At first at high temperature aerating oxygen and photoresist react and remove photoresist, Here it is described dry process, so be enough in the ordinary course of things remove photoresist, for the technology that guarantees to remove photoresist more perfect, after dry process, also adopted wet chemical process for may further removing by remaining photoresist.
In conjunction with Fig. 1 and shown in Figure 9, carry out cmp for the dielectric layer of whole crystal column surface.The chemical and mechanical grinding method that adopts in the present embodiment is as follows, and bistrique 26 holds wafer, and lapping liquid 24 flows through mill pad 25 and wafer 20 surfaces, and the dielectric layer 21 of crystal column surface is just little by little ground off by the lapping liquid particle, and is washed away by lapping liquid.Because rotating disk 23 rotations, the acting in conjunction of grinding pad 25 rotations and lapping liquid 24 makes wafer 20 surface finish, and higher crystal circle center zone can be at first polished, is only the crystal round fringes zone then, so just can make crystal column surface reach smooth.And, because the dielectric layer of crystal round fringes has passed through etching before, revised the thickness disparity of the dielectric layer in the dielectric layer that originally only adopts the crystal round fringes that cmp causes and crystal circle center zone, therefore, after finishing cmp, the thickness of dielectric layers of crystal round fringes also can reach the requirement of the flattening surface that equates with the thickness in crystal circle center zone.
The method that just is to use the embodiment of the invention as shown in table 1 is carried out the thickness of the dielectric layer that records at crystal round fringes after the flattening surface to wafer,
Table 1
Test position in the table 1 is exactly the distance of test point apart from crystal round fringes in fact, thickness of dielectric layers after the default planarization is 280 ± 35 dusts, from table, can see, the thickness of the dielectric layer of nearly all test position all meets default requirement, therefore, the present invention's method of improving flattening wafer surface can improve the degree of flattening wafer surface really.
In order to verify before the dielectric layer that carries out chemical mechanical milling method planarization semiconductor wafer surface, carry out the effect of crystal round etching for dielectric layer for flattening wafer surface, present embodiment is after the dielectric layer for crystal column surface carries out cmp, and just the dielectric layer for crystal round fringes carries out etching.It is as follows to carry out etched step for the dielectric layer of crystal round fringes, forms photoresist layer on the dielectric layer of crystal column surface; Photoresist layer for crystal round fringes exposes, develops and forms the photoresist recess; With the photoresist layer is mask, carries out etching in the photoresist indent for the dielectric layer of crystal round fringes and removes the dielectric layer of setting thickness; Remove photoresist layer.Wherein, described thickness is the mean value of thickness disparity of the dielectric layer in the dielectric layer of the crystal round fringes that records after cmp and crystal circle center zone.But, because the relation of aforesaid abrasive disc speed, through after the cmp, the dielectric layer of crystal round fringes is not a same thickness yet, but along from the crystal circle center zone to crystal round fringes direction progressive additive, therefore, carrying out etching for the dielectric layer of crystal round fringes again after carrying out cmp for dielectric layer is to make the thickness of dielectric layers of crystal round fringes reach the requirement of the flattening surface that equates with the thickness in crystal circle center zone.It is as shown in table 2 that at first the dielectric layer to crystal column surface carries out cmp in order to adopt the present embodiment method, carry out etching for the dielectric layer of crystal round fringes again after, the thickness of the dielectric layer that records at crystal round fringes,
Table 2
Test position in the table 2 is exactly the distance of test point apart from crystal round fringes in fact, thickness of dielectric layers after the default planarization is 280 ± 35 dusts, can see that from table the thickness that surpasses half test position that records does not all meet default requirement, therefore, the cmp of the dielectric layer dielectric layer etching of crystal column surface was only implemented just can reach the dielectric layer that makes crystal round fringes and crystal circle center zone before carrying out to(for) dielectric layer reaches the flattening wafer surface requirement of same thickness.
In sum, flattening wafer surface method of the present invention was earlier carried out etching for the dielectric layer of crystal round fringes and is removed the dielectric layer of setting thickness before the dielectric layer for crystal column surface carries out cmp, reach the purpose of revising for the thickness disparity of the dielectric layer in dielectric layer that grinds the back crystal round fringes and crystal circle center zone.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. the method for a flattening wafer surface is characterized in that, comprise the following steps,
The wafer that provides the surface to have dielectric layer comprises the central area and around the fringe region of central area;
Remove the dielectric layer of fringe region part thickness;
Dielectric layer for whole crystal column surface carries out cmp,
Wherein said fringe region is that the dielectric layer zone of back thickness of dielectric layers greater than the etching vias degree of depth ground in test piece, described fringe region dielectric layer remove thickness more than or equal to the cmp that records by test piece after the average thickness gap of dielectric layer in the dielectric layer in crystal circle center zone and crystal round fringes zone.
2. the method for flattening wafer surface as claimed in claim 1 is characterized in that, the dielectric layer of described removal crystal round fringes area part thickness adopts etching method.
3. the method for flattening wafer surface as claimed in claim 2 is characterized in that, described etched process also comprises the following steps, forms photoresist layer on the dielectric layer of crystal column surface; Photoresist layer exposure, development for the crystal round fringes zone form the photoresist recess; With the photoresist layer is mask, removes the dielectric layer of segment thickness for the dielectric layer etching of crystal round fringes in the photoresist indent; Remove photoresist layer.
4. the method for flattening wafer surface as claimed in claim 3 is characterized in that, described photoresist layer exposure for the crystal round fringes zone adopts high-pressure mercury lamp, excimer laser, X ray or electron beam as exposure light source.
5. the method for flattening wafer surface as claimed in claim 3 is characterized in that, described photoresist layer for the crystal round fringes zone develops and forms employing dry process development of photoresist recess or wet development.
6. the method for flattening wafer surface as claimed in claim 3 is characterized in that, dry etching or wet etching are adopted in described dielectric layer etching for the crystal round fringes zone.
7. the method for flattening wafer surface as claimed in claim 3 is characterized in that, the photoresist layer on the described removal wafer adopts dry method in conjunction with wet chemical process.
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| CN102637238A (en) * | 2012-05-09 | 2012-08-15 | 中国科学院微电子研究所 | Calculation method for grinding removal rate of wafer surface |
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