TW201009927A - Method for manufacturing a semiconductor device, and a semiconductor device - Google Patents
Method for manufacturing a semiconductor device, and a semiconductor device Download PDFInfo
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- TW201009927A TW201009927A TW98114437A TW98114437A TW201009927A TW 201009927 A TW201009927 A TW 201009927A TW 98114437 A TW98114437 A TW 98114437A TW 98114437 A TW98114437 A TW 98114437A TW 201009927 A TW201009927 A TW 201009927A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Abstract
Description
201009927 * 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有半導體積體電路之半導體裝置 的製造方法及半導體裝置，該半導體積體電路可在低耗電 的ft況下作尚速運行、或是可抑制於高溫區域下之寄生動 作且具有高抗靜電性能。 ⑩ 【先前技術】 雙極系1C，大多用於極其需要高速性能之用途、或大 多用作與包括功率半導體（Power MOS )之功率元件的控 制電路形成一體之1C。 例如，功率積體電路（p〇wer IC)，大多用於惡劣的環境 中。在汽車等領域中，作為潛在要求，要求設置於引擎周 邊之功率1C能夠保證在例如2〇〇、今後240°C左右之溫 度下穩定運行。關於在如此惡劣之條件下使用之1(：，進行 © 元件開發時必須充分考慮到存在於1C電路内之寄生效應。 其中，使用於高頻電路時，必須減小寄生電容，會因 . 接合元件分離而導致出現寄生電容之問題。 先前之矽（Si)之1C技術中，作為各元件間（npn電 晶體、Nch— MOSFET或Pch— MOSFET等）之寄生效應之 對策，已知有利用pn接合來進行絕緣分離之接合分離以 及利用溝槽來進行絕緣分離之溝槽分離等元件分離法。 此外，使用之基板亦有兩種，主要有於通常之si基板 也就是CZ基板上成長磊晶而成之磊晶基板、以及貼合絕 3 201009927 緣層上覆石夕（Silicon-On-Insulator(SOI))基板。 使用Si磊晶基板並實施接合分離之方法，雖然基板自 身的成本以及製造成本較低，但必須實施抑制高溫下之今 生效應的對策。 另一方面，使用貼合SOI基板並實施溝槽介電分離之 方法，雖然基板自身成本高，但具有在電路設計時基本上 無需考慮寄生效應之優點。然而，因貼合SOI基板使用2 片晶圓’故而基板自身之成本始終較高，因此，如何實現 〇 低成本之介電質元件分離技術已成為使介電分離型Ic之 特性的優點得以實用的中心課題。 進而，因功率1C大多用於較惡劣之環境，故而抗靜電 性能係非常重要之特性。 該靜電破壞之機制，基本上係對元件之熱破壞。通常 使用Si磊晶基板之接合分離的結構，可製作下部電極型之 縱型元件’因此與一般使用橫型元件結構之S0I基板的溝 槽介電分離結構相比，容易擴大通電區域之面積，但存在 ® 寄生效應之問題。 而且，使用sm基板時，雖然能夠抑制寄生效應，但 難以實現下部電極結構’輪出段之功率1(:於高抗靜電性能 方面仍然存在問題。因此，雖然業者正在摸索部分SOI等 之結構，但因其成本極高，故難以使其得以實用。 【發明内容】 如上所述，眾所周知（穿·[Technical Field] The present invention relates to a method of fabricating a semiconductor device having a semiconductor integrated circuit and a semiconductor device, which can be used in a low power consumption ft condition It can run at high speed or can inhibit the parasitic action in high temperature areas and has high antistatic performance. 10 [Prior Art] Bipolar system 1C is mostly used for applications that require high-speed performance, or as a 1C that is integrated with a control circuit including power components of power MOS. For example, power integrated circuits (p〇wer ICs) are mostly used in harsh environments. In the field of automobiles and the like, as a potential requirement, it is required that the power 1C provided around the engine can be stably operated at a temperature of, for example, 2 〇〇 and 240 ° C or so. Regarding the use of 1 under such severe conditions (:, the development of © components must fully consider the parasitic effects existing in the 1C circuit. Among them, when used in high-frequency circuits, it is necessary to reduce the parasitic capacitance, which may cause The problem of parasitic capacitance is caused by the separation of components. In the previous 1C technology of 矽 (Si), it is known to use pn as a countermeasure against parasitic effects between devices (npn transistors, Nch-MOSFETs, Pch-MOSFETs, etc.). Element separation method such as joint separation for insulation separation and trench separation for insulation separation using trenches. In addition, there are two types of substrates used, mainly on the Si substrate, which is a CZ substrate. The epitaxial substrate is formed, and the Silicon-On-Insulator (SOI) substrate is bonded to the edge of the 201009927. The method of using the Si epitaxial substrate and performing the bonding separation, the cost and manufacture of the substrate itself. The cost is low, but countermeasures against the effects of high temperature and high temperature must be implemented. On the other hand, the method of bonding the SOI substrate and performing dielectric separation of the trench is used, although The cost of itself is high, but it has the advantage of not needing to consider parasitic effects in circuit design. However, since two wafers are used for bonding SOI substrates, the cost of the substrate itself is always high, so how to achieve low cost The electric component separation technique has become a central issue in which the advantages of the characteristics of the dielectric separation type Ic are practical. Further, since the power 1C is often used in a harsh environment, the antistatic property is a very important characteristic. The mechanism is basically thermal damage to the device. Usually, the structure of the Si epitaxial substrate is used to separate and form the lower electrode type of the vertical element. Therefore, it is dielectrically separated from the trench of the SOI substrate which generally uses the horizontal element structure. Compared with the structure, it is easy to enlarge the area of the energized area, but there is a problem of parasitic effect. Moreover, when the sm substrate is used, although the parasitic effect can be suppressed, it is difficult to realize the power of the lower electrode structure 'rounding section 1 (: in high resistance There are still problems with electrostatic performance. Therefore, although the industry is exploring some SOI structures, it is extremely expensive. It is difficult to make it practical. SUMMARY OF THE INVENTION As described above, it is known (wear ·
、心全）介電分離型之BiCMOS 201009927 系或M〇S系之智慧型功率積體電路⑽啊咖p_r I叫她d Cireuit(IPIC))具有高頻特性，不會形纟寄生間流 體’且環境適應性能等優秀之優點。 但是，其實用化仍受到極大地限制。其主要原因在於， 使用SOI基板或溝槽分離等方法時，其製造成本極高。因 此，僅限定地用於航空或部分汽車之必須具備環境適應性 之領域、或電話交換機之輸入部之保護電路、或PDP掃描 驅動器等必須有高耐壓特性之元件等領域中，其使用受 ❹ 極大地限制。 其中，存在貼合SOI基板的成本較高之問題。 貼合厚膜SOI基板，係貼合2片晶圓製造而成者，因 此自初期起便以2片晶圓之成本作為前提。此點係貼合厚 膜SOI基板於成本方面之本質性弱點。進而，必須通過磨 削、研磨將元件形成層（1層）側除去至特定厚度，但此時 必須將I層的厚度控制於±10%以下，因此實際情況為不得 不於晶圓加工的各階段中實施詳細之厚度管理。 ® 考慮到膜厚控制，而在使用蠢晶層之接合分離型中， 無論採用何種膜厚都可比較容易地實現±5%以下之管理。 與此相對，於貼合2片晶圓時，加工精度以在晶圓内是±〇.5 Mm為其極限，因而無法對應][層厚度小於5 #miS〇i 結構。此外，因外圈部之未貼合的邊界係不規則形狀，因 此還必須用光微影法來去除外圈數毫米之秒層，使其成為 正圓形。因此，存在以下問題：必須有除去外圈部固定寬 度之製程’故而成本增高；無法使用該區域，實際可利用 201009927 之面積減少。 因此作為一部分對策’通過對使用氫離子植入之 SMART CUT晶圓（SMART CUT係註冊商標）實施特定之 磊晶成長，以應對I層較薄的規格。但是，其成本會進一 步增加。 其中’揭示有一種半導體裝置的製造方法，其於對晶 圓背面實施背面磨削來製造元件厚度較薄之IGBT等半導 體元件時’在形成有半導體元件之面上，黏貼保持基板或 〇 高剛性薄片等，然後磨削支撐基板（參照曰本專利特開2004 一 140101號公報此外，在用於ic卡或多晶片封裝用途 時’將1C製程完畢之晶圓（IC製程結束後之晶圓）的厚 度減至50以m左右之同種方法，亦已經部分得到實用。 但是’該等方法都無法將半導體元件完全地介電分離。 本發明係鑒於上述問題開發而成者，其目的在於提供 一種能夠以低成本製造的完全介電分離型1C的半導體裝 置及其製造方法，該半導體裝置的寄生電容小、可高速且 ❹ 低耗電地運行、或是無寄生效應且具有高抗靜電性能的優 秀元件特性。 為了解決上述課題，本發明提供一種半導體装置的製 造方法，其特徵在於至少具有以下製程： 準備使磊晶層成長之單晶矽基板之製程； 於該單晶矽基板的表面，形成用以在其後之蝕刻製程 中使蝕刻停止之蝕刻終止層之製程； 於該姓刻終止層的表面，成長磊晶層之製程； 6 201009927 將於該磊晶層的表面形成之用以將半導體元件介電分 離的溝槽，形成為具有τ貫通上述餘刻終止層之深度後， 於該分離用溝槽内部形成絕緣膜，並且於上述磊晶=的表 面’形成半導體元件之製程； 冑職有上述半導體元件之側的表面與保持基板貼合 之製程； 對上述單晶矽基板之形成有磊晶層的面之背面，實施 磨削、研磨，之後對經過該磨削、研磨之面實施蝕刻，並 Φ 且於上述蝕刻終止層停止蝕刻之製程； 於露出上述蝕刻終止層之側的表面，形成絕緣層之製 程； 將形成有該絕緣層之侧的表面與支撐基板貼合之製 程；以及 剝離上述保持基板之製程。 於單晶矽基板的表面，形成蝕刻終止層後，在其上成 長磊晶層。然後於磊晶層上形成半導體元件，在與保持基 β 板貼合後，磨削、研磨單晶矽基板的背面。利用該磨削、 研磨使單晶矽基板實現一定程度的薄膜化後，再對磨削、 研磨面實施蝕刻。實施該蝕刻時，當蝕刻進行至蝕刻終止 層時，會於該蝕刻終止層停止蝕刻》因為以此種方式來實 施蝕刻，故而與先前之僅利用磨削、研磨來減少單晶矽基 板厚度之方法相比’能夠在厚度方向上高精度地減少單晶 石夕的厚度。此外，藉由利用蝕刻終止層來停止蝕刻，能夠 將單晶矽基板高精度地除去至期望之位置為止。 7 201009927 然後，於露出的面上形成絕緣層。由於先前形成之介 電分離用溝槽，具有貫通蝕刻終止層之深度，因此利用該 溝槽與已形成之絕緣層，能夠將半導體元件完全地電性分 離。 然後’將形成有半導體元件之磊晶層與機械性地支撐 絕緣層之支撐基板黏貼，之後去除保持基板。 藉此’無需採用使用2片晶圓之s〇l基板，即可製造 出形成有元件完全分離型1C之半導體裝置。亦即，因為僅 ® 需使用1片單晶矽晶圓，故而與使用貼合soi基板之情形 相比，能夠降低成本。此外，形成半導體元件之層係磊晶 層，因此能夠實現具有高平坦度且可獲得所期望之厚度的 高品質半導體裝置。 此外’較好的是：準備P型基板來作為上述單晶矽基 板’且形成η型磊晶層來作為上述蝕刻終止層，並實施電 化學蝕刻來作為上述蝕刻製程。 藝如此’藉由使用η型層來作為蝕刻終止層，並藉由電 化學银刻來蝕刻ρ型基板，能容易地僅除去ρ型基板，而 留下η型磊晶層。 此外’較好的是：準備雜質濃度小於上述磊晶層1位 乂上之Ρ型基板來作為上述單晶砍基板’且通過使錄及鱗 擴散至上述單晶砍基板中’於η +層的下側形成作為上述钱 刻終止層之η型廣。 如此’為了形成η型埋設擴散層，於擴散銻之同時， 低遭度地擴散碟’且作為单晶發基板，是使用雜質濃度小 8 201009927 於η型磊晶層1位以上之低濃度的p型基板。藉此可減 小碟向銻擴散層的上部擴散之影響，並且容易於下部藉由 磷擴散而生成η—層。而且，藉由使用該n型層來作為蝕刻 終止層，能夠製造出適合製作縱型雙極電晶體型積體電路 之半導體裝置。 此外，形成上述分離用溝槽及半導體元件之製程可 為如下之製程：於形成上述分離用溝槽後，使11型雜質自 該分離用溝槽内壁擴散，然後形成上述絕緣膜，之後用多 ® 晶矽填充該分離用溝槽，最後形成縱型電晶體及/或橫型電 晶體。 此外，在使用η型層來作為蝕刻終止層時，自溝槽内 侧擴散磷等η型雜質，同樣地能夠防止接通電阻之增大， 並可將電流自元件下部側引出至上部。但是此時於溝槽頂 端部η—層會消失，由於會生成蝕刻終止不完全之部分，因 此必須實施充分確保η-區域的寬度之製程、高精度地磨削 來減少蝕刻量之製程、以及於蝕刻終止後導入研磨等若干 需要非常注意之製程。因為下部電極為n+層，所以適合形 成縱型功率電晶體》 如此，藉由自分離用溝槽的側面擴散摻雜劑，形成用 以減少串聯電阻且自元件下部將電流引出至上面的區域 (没集器（sinker·))，藉此可以將流動高電流之縱型電晶體 與容易高積體化之橫型電晶體形成於同一晶片中。利用該 等方法實現之積體電路’能夠利用分離用溝槽來實施介電 分離，即便對於因元件區域附近存在金屬、雜訊或功率電 9 201009927 帛體的發熱而造成之元件的誤運行，亦具有極高之抗性。 於將P型層用於終止蝕刻時，能夠將其用作IGBT之集極。 此外，較好的是：藉由使高濃度之P雜質擴散至上 述單晶石夕基板中，形成作為上述兹刻終止層之p+型層，並 且作為上述蝕刻製程，使用KOH、NaOH、EDP溶液中至 少1種以上來實施蝕刻。 如此，藉由形成p+型層來作為蝕刻終止層，可使磊晶 層為P型，藉此，能作成適合製作M〇s系智慧型功率ic 0之半導體裝置。此外’藉由使用KOH、NaOH、EDP溶液 中至少1種以上來實施蝕刻，使經過磨削、研磨後之基板 浸凊於該等溶液中，從而可使蝕刻終止於p+型層，因此容 易實施姓刻。而且，因為可利用將基板浸潰於钱刻液之方 法來實施钱刻，所以能夠批次處理餘刻製程，可以一次性 處理大量基板。 此外，形成上述分離用溝槽及半導體元件之製程，可 為如下之製程：於形成上述分離用溝槽後，使P型雜質自 該刀離用溝槽内壁擴散，然後形成上述絕緣膜之後用多 晶矽填充該分離用溝槽，最後形成縱型電晶體及橫型電晶 體。 此外，將P層用於終止蝕刻時，形成上述分離用溝槽 及半導體元件之製程，能夠於形成上述分離用溝槽後，使 硼等p型雜質自溝槽表面擴散，然後形成氧化膜等絕緣 膜，藉此與下部蝕刻終止用P+層連接，將P型之低電阻層 引出至表層。藉此，即便在形成有縱型電晶體時，亦可將 201009927 大電流自下部引出至表層。 亦即’可於經過介電分離後之基板上，同時將橫型電 晶體與縱型電晶體積體化。特別是，縱型電晶體較橫型電 晶體之通電區域更廣，也就是可流動大電流，因此可利用 使用橫方向電晶體之MOSIC來形成控制用ic，實現高輪 出之縱型功率電晶體驅動。例如，藉由於p+擴散基板上使 蟲晶層依n+緩衝層、η-層之順序成長，從而能夠將IGBT 形成於積體電路上。 ® 此外，本發明提供一種半導體裝置，是至少經由絕緣 層將表面形成有半導體元件之磊晶層貼合在支撐基板上而 成之半導體裝置’其特徵在於：於上述絕緣層與上述磊晶 層之間，具有蝕刻終止層。 如此’因為形成有银刻終止層，所以在除去形成蠢晶 層時所使用之單晶矽基板時，能夠在最後實施蝕刻，並利 用蝕刻終止層來停止蝕刻，藉此能夠基本上完全地除去單 晶梦基板。 ❹ 此外，上述所貼合之支撐基板，較好的是鋁基板。 如此’如果作為支撐基板是使用較單晶矽基板廉價之 鋁基板，則可提供較先前更廉價之半導體裝置。 另外，上述蟲晶層之上述半導體元件，較好的是藉由 到達上述絕緣層之深度的分離用溝槽，來實施介電分離者。 如上所述’本發明之半導體裝置’係能夠除去先前殘 留於絕緣層與磊晶層之間之單晶矽者。因此，形成到達絕 緣層之深度之分離用溝槽之目的在於，能夠藉由分離用溝 201009927 槽，將半導體元件與絕緣層完全地介電分離》 如上所述，若根據本發明，能夠以與先前之BiCMOS 製程相近之方法來形成元件，然後黏接保持基板，接著進 行背面精削（背面磨削）以及對背面實施特定量之通常的 姓刻之後，使用蝕刻終止用蝕刻液來實施蝕刻，藉此能夠 高精度地控制元件區域的厚度，並能夠以低成本製造出具 有完全介電分離結構之1C» 對於在如習知般地先貼合2片單晶矽晶圓，然後利用 〇 磨削與研磨來減少其中一方的單晶矽晶圓的厚度而成的貼 合厚膜SOI基板中，其SOI層的膜厚控制困難且厚度為10 从m以下之半導體裝置，亦能夠利用本發明來實現±3%以 下之可控制性。 而且，因為無需使用高純度單晶矽基板來作為支撐基 板，可使用廉價之鋁基板等，因此本半導體裝置的製造方 法能夠廉價地製造出元件完全分離型1C。 β 【實施方式】 以下詳細說明本發明，但本發明並非僅限於這些實施 方式關於本發明之半導體裝置，參照形成有MOS型的智 慧型功率ic結構之半導體裝置的剖面圖也就是第ι圖來加 以說明，但當然並非限定於此。 本實施方式中的本發明之半導體裝置1〇，係於支撐基 板也就疋銘基板20 i，經由作為絕緣層之梦氧化膜38， 形成有p型之磊晶層32者。而且，於矽氧化膜U與表面 12 201009927 形成有半導體元件34之磊晶層也就是？ P+ +型之蝕刻終止層31a。 之間’具有 ^ Jit 个f知疋牛等體裝置，係於製作 止層將形成磊晶層時所使用之單晶 ^藉由蝕刻終 者。 早曰曰矽基板完全除去, the whole heart) dielectric separation type BiCMOS 201009927 system or M〇S system of intelligent power integrated circuit (10) ah coffee p_r I called her d Cireuit (IPIC)) with high frequency characteristics, will not shape parasitic fluid ' And the advantages of environmental adaptability and other excellent. However, its practicality is still greatly limited. The main reason is that when a method such as an SOI substrate or trench separation is used, the manufacturing cost is extremely high. Therefore, it is limitedly used in the field of environmentally adaptable areas of aviation or some automobiles, or the protection circuit of the input part of a telephone exchange, or a component such as a PDP scan driver that must have high withstand voltage characteristics.极大 Greatly limited. Among them, there is a problem that the cost of bonding the SOI substrate is high. When a thick-film SOI substrate is bonded and two wafers are bonded together, the cost of two wafers is premised from the beginning. This point is the essential weakness of the cost of the thick film SOI substrate. Further, it is necessary to remove the element forming layer (one layer) side to a specific thickness by grinding and polishing. However, in this case, the thickness of the I layer must be controlled to ±10% or less. Therefore, the actual situation is that each of the wafer processing has to be performed. Detailed thickness management is implemented during the phase. ® Considers the film thickness control, and in the joint separation type using the stray layer, it is easier to achieve management of ±5% or less regardless of the film thickness. On the other hand, when two wafers are bonded together, the processing accuracy is ±5. 5 Mm in the wafer, and thus it is impossible to correspond to the [layer thickness is less than 5 #miS〇i structure. Further, since the unbonded boundary of the outer ring portion is irregular, it is necessary to remove the layer of the outer ring several millimeters by the photolithography method to make it a perfect circle. Therefore, there is a problem that the process of removing the fixed width of the outer ring portion must be carried out, so that the cost is increased; the area cannot be used, and the area of 201009927 can be actually reduced. Therefore, as a part of the countermeasures, a specific epitaxial growth is performed on a SMART CUT wafer (SMART CUT registered trademark) using hydrogen ion implantation to cope with a thin I-layer specification. However, its cost will increase further. In the method of manufacturing a semiconductor device, when a back surface grinding is performed on a back surface of a wafer to manufacture a semiconductor element such as an IGBT having a thin component thickness, 'on the surface on which the semiconductor element is formed, the substrate is adhered or has high rigidity. A sheet or the like, and then the support substrate is ground (refer to Japanese Laid-Open Patent Publication No. 2004-140101, and the wafer after the 1C process is completed for the ic card or multi-chip package application (wafer after the end of the IC process) The same method of reducing the thickness to about 50 m has also been partially practical. However, none of these methods can completely separate the semiconductor elements from dielectric separation. The present invention has been developed in view of the above problems, and an object thereof is to provide a method. A fully dielectric separation type 1C semiconductor device which can be manufactured at low cost and a method of manufacturing the same, which has a small parasitic capacitance, can be operated at a high speed and with low power consumption, or has no parasitic effect and has high antistatic property. In order to solve the above problems, the present invention provides a method of fabricating a semiconductor device characterized in that it is at least The following processes are: preparing a single crystal germanium substrate for growing an epitaxial layer; forming a process for etching an etch stop layer for etching in a subsequent etching process on the surface of the single crystal germanium substrate; Cutting the surface of the layer and growing the epitaxial layer; 6 201009927 A trench formed on the surface of the epitaxial layer for dielectrically separating the semiconductor element is formed to have a depth of τ through the residual stop layer Forming an insulating film inside the trench for separation, and forming a semiconductor device on the surface of the epitaxial layer; forming a process for bonding the surface of the side of the semiconductor device to the substrate; a surface of the substrate on which the back surface of the epitaxial layer is formed, subjected to grinding and polishing, and then etching the surface subjected to the grinding and polishing, and Φ and stopping etching at the etching stopper layer; exposing the etching stopper layer a process of forming an insulating layer on the side of the surface; a process of bonding the surface on the side on which the insulating layer is formed to the support substrate; and a process of peeling off the substrate After forming an etch stop layer on the surface of the single crystal germanium substrate, an epitaxial layer is grown thereon. Then, a semiconductor element is formed on the epitaxial layer, and after bonding with the sustain base β plate, the single crystal germanium substrate is ground and polished. The back surface of the single crystal germanium substrate is subjected to a certain degree of thinning by the grinding and polishing, and then the grinding and polishing surfaces are etched. When the etching is performed, when the etching proceeds to the etching stopper layer, the etching is performed. Since the termination layer stops etching, since the etching is performed in this manner, it is possible to reduce the single crystal stone in the thickness direction with high precision compared with the conventional method of reducing the thickness of the single crystal germanium substrate by only grinding and polishing. Further, by stopping the etching by using the etching stopper layer, the single crystal germanium substrate can be removed to a desired position with high precision. 7 201009927 Then, an insulating layer is formed on the exposed surface. Since the previously formed dielectric separation trench has a depth penetrating through the etch stop layer, the semiconductor element can be completely electrically separated by the trench and the formed insulating layer. Then, the epitaxial layer on which the semiconductor element is formed is adhered to the support substrate which mechanically supports the insulating layer, and then the holding substrate is removed. Thus, it is possible to manufacture a semiconductor device in which the element-separated type 1C is formed without using a substrate of two wafers. That is, since only one single crystal germanium wafer is required for ®, the cost can be reduced as compared with the case of using a bonded soi substrate. Further, since the layered epitaxial layer of the semiconductor element is formed, it is possible to realize a high-quality semiconductor device having high flatness and obtaining a desired thickness. Further, it is preferable that a P-type substrate is prepared as the single crystal germanium substrate and an n-type epitaxial layer is formed as the etching stopper layer, and electrochemical etching is performed as the etching process. Thus, by using an n-type layer as an etch stop layer and etching the p-type substrate by electroless silver etching, only the p-type substrate can be easily removed, leaving an n-type epitaxial layer. Further, it is preferable to prepare a ruthenium-type substrate having an impurity concentration smaller than that of the epitaxial layer at the position of the epitaxial layer as the single-crystal chopped substrate 'and by diffusing the recorded scales into the single-crystal chopped substrate' in the η + layer The lower side is formed as an n-type wide as the above-mentioned money indentation layer. In order to form the n-type buried diffusion layer, the diffusion plate is diffused at a low level, and the substrate is used as a single crystal substrate. The impurity concentration is small 8 201009927 at a low concentration of 1 or more of the n-type epitaxial layer. P-type substrate. Thereby, the influence of the diffusion of the dish onto the upper portion of the diffusion layer can be reduced, and the η layer can be easily formed by diffusion of phosphorus in the lower portion. Further, by using the n-type layer as an etch stop layer, a semiconductor device suitable for fabricating a vertical bipolar transistor integrated circuit can be manufactured. Further, the process of forming the separation trench and the semiconductor element may be a process of forming the above-described separation trench, diffusing the 11-type impurity from the inner wall of the separation trench, and then forming the insulating film, and then using the insulating film. The wafer is filled with the trench for separation, and finally a vertical transistor and/or a lateral transistor are formed. Further, when an n-type layer is used as the etch-stop layer, an n-type impurity such as phosphorus is diffused from the inner side of the trench, and similarly, an increase in the on-resistance can be prevented, and a current can be drawn from the lower portion side of the element to the upper portion. However, at this time, the η-layer disappears at the tip end portion of the trench, and a portion where the etching termination is incomplete is generated. Therefore, it is necessary to carry out a process of sufficiently ensuring the width of the η-region, high-precision grinding to reduce the etching amount, and After the etching is terminated, a number of processes requiring great care, such as grinding, are introduced. Since the lower electrode is an n+ layer, it is suitable for forming a vertical power transistor. Thus, by diffusing the dopant from the side of the trench for separation, a region for reducing the series resistance and drawing current from the lower portion of the element is formed ( There is no collector (sinker), whereby a vertical transistor that flows a high current can be formed in the same wafer as a lateral transistor that is easily integrated. The integrated circuit implemented by these methods can perform dielectric separation using the trench for separation, even if the component is mis-operated due to the presence of metal, noise, or power in the vicinity of the device region. It also has extremely high resistance. When the P-type layer is used for termination etching, it can be used as a collector of an IGBT. Further, it is preferred that a p+ type layer as the above-described stop layer is formed by diffusing a high concentration of P impurities into the single crystal substrate, and as the etching process, a KOH, NaOH, EDP solution is used. At least one of the above is performed to perform etching. As described above, by forming the p + -type layer as the etch stop layer, the epitaxial layer can be made P-type, whereby a semiconductor device suitable for fabricating the M 〇s-based smart power ic 0 can be produced. In addition, by performing etching using at least one of KOH, NaOH, and EDP solutions, the ground and polished substrate is immersed in the solution, so that etching can be terminated in the p+ layer, which is easy to implement. The surname is engraved. Further, since the engraving can be carried out by the method of immersing the substrate in the engraving liquid, the residual processing can be batch-processed, and a large number of substrates can be processed at one time. Further, the process for forming the separation trench and the semiconductor device may be a process of forming a P-type impurity from the inner wall of the blade separation trench after forming the separation trench, and then forming the insulating film. The polysilicon is filled with the trench for separation, and finally a vertical transistor and a lateral transistor are formed. Further, when the P layer is used for termination etching, the separation trench and the semiconductor device are formed, and after the separation trench is formed, p-type impurities such as boron are diffused from the surface of the trench, and an oxide film or the like is formed. The insulating film is connected to the P+ layer for lower etching termination, and the P-type low resistance layer is taken out to the surface layer. Thereby, even when a vertical transistor is formed, a large current of 201009927 can be taken out from the lower portion to the surface layer. That is, the horizontal transistor and the vertical transistor can be simultaneously bulked on the substrate after dielectric separation. In particular, the vertical transistor has a wider current-carrying region than the lateral transistor, that is, a large current that can be flowed. Therefore, a MOSIC using a lateral transistor can be used to form a control ic to realize a high-powered vertical power transistor. drive. For example, the IGBT can be formed on the integrated circuit by growing the crystal layer on the p+ diffusion substrate in the order of the n+ buffer layer and the η-layer. In addition, the present invention provides a semiconductor device in which an epitaxial layer having a semiconductor element formed on a surface thereof is bonded to a support substrate via at least an insulating layer, wherein the insulating layer and the epitaxial layer are formed Between there, there is an etch stop layer. Thus, since the silver etch stop layer is formed, when the single crystal germanium substrate used for forming the stray layer is removed, the etching can be performed at the end, and the etching is stopped by the etch stop layer, whereby the substantially complete removal can be performed. Single crystal dream substrate. Further, the support substrate to which the above is bonded is preferably an aluminum substrate. Thus, if the support substrate is an aluminum substrate which is cheaper than a single crystal germanium substrate, a semiconductor device which is less expensive than before can be provided. Further, it is preferable that the semiconductor element of the above-mentioned insect layer is subjected to dielectric separation by a trench for separation reaching the depth of the insulating layer. The semiconductor device of the present invention as described above is capable of removing a single crystal defect previously remaining between the insulating layer and the epitaxial layer. Therefore, the purpose of forming the separation trench reaching the depth of the insulating layer is to completely separate the semiconductor element and the insulating layer by the separation trench 201009927. As described above, according to the present invention, The previous BiCMOS process is similar to the method of forming the component, then bonding the substrate, followed by backside refining (back grinding) and performing a specific amount of the usual amount on the back side, and then etching is performed using an etch stop. Thereby, the thickness of the element region can be controlled with high precision, and the 1C» having a completely dielectric separation structure can be manufactured at low cost. For the conventionally, two single crystal germanium wafers are bonded first, and then the honing is performed. In a thick-film SOI substrate obtained by cutting and polishing to reduce the thickness of one of the single crystal germanium wafers, the thickness of the SOI layer is difficult to control, and the semiconductor device having a thickness of 10 m or less can also utilize the present invention. To achieve controllability below ±3%. Further, since it is not necessary to use a high-purity single crystal germanium substrate as the supporting substrate, an inexpensive aluminum substrate or the like can be used. Therefore, the manufacturing method of the semiconductor device can inexpensively manufacture the element completely separated type 1C. [Embodiment] The present invention will be described in detail below, but the present invention is not limited to the semiconductor device of the present invention, and the cross-sectional view of the semiconductor device in which the MOS type smart power ic structure is formed is referred to as the It is explained, but it is of course not limited to this. In the semiconductor device 1 of the present invention in the present embodiment, the support substrate is also a substrate 20i, and a p-type epitaxial layer 32 is formed via the dream oxide film 38 as an insulating layer. Moreover, an epitaxial layer of the semiconductor element 34 is formed on the tantalum oxide film U and the surface 12 201009927. The etch stop layer 31a of the P++ type. There is a Jit device, such as a yak, which is used to form a single crystal to form an epitaxial layer by etching. Early removal of the substrate completely
$前’於元件形成後進㈣以減少單切基 者面磨削_，需實施磨削、研磨。但該等方法中曰：之 内的厚度之均勻化存在限制，無法充分實現薄膜化。面 然而，本發明之半導體裝置，雖然最終通過餘刻來除 去單晶秒基板，但可藉由㈣終止層，殘留下用於元件之 磊晶層，可基本完全地除去單晶矽基板。然後，藉由將絕 緣層形成於蝕刻終止面，能夠獲得已高精度地控制〗層的 厚度之SOI結構。 其中’作為支撐基板20，可使用鋁基板。 如此’使用較單晶矽基板廉價之鋁基板來作為支撐基 板之半導體裝置，與先前之使用單晶矽基板來作為支撐基 板之半導體裝置相比，降低了成本。 此外’如第1圖所示，形成具有到達絕緣層38之深度 之分離用溝槽33，藉此能夠將半導體元件34介電分離。 如此’藉由深度到達絕緣層之分離用溝槽33與絕緣層 38 ’能夠將半導體元件34完全地介電分離。 此外’作為其他實施方式’在第20圖中表示本發明之 半導體裝置之另一例的具有形成有縱型IGBT之智慧蜇功 率1c結構之半導體裝置的剖面概要圖。 13 201009927 於該實施方式中，在支撐基板20上，經由絕緣層形成 有蝕刻終止層31a、η緩衝層55a、以及蟲晶層32。而且於 磊晶層32中形成有電極配線15。 此外，於磊晶層32的表面上形成有：形成有縱型IGBT 之IGBT區域51;以及在藉由分離用溝槽33而與該IGBT 區域介電分離之區域，形成有CMOS之CMOS區域52。而 且，於IGBT區域形成有閘極53或射極14b。Before the component is formed (4) to reduce the single-cut surface grinding, grinding and grinding are required. However, in these methods, the uniformity of the thickness within the crucible is limited, and the thin film formation cannot be sufficiently achieved. However, in the semiconductor device of the present invention, although the single crystal second substrate is finally removed by the residual, the single crystal germanium substrate can be substantially completely removed by (4) terminating the layer and leaving the epitaxial layer for the element. Then, by forming the insulating layer on the etching stopper surface, it is possible to obtain an SOI structure in which the thickness of the layer is controlled with high precision. Among them, as the support substrate 20, an aluminum substrate can be used. Thus, a semiconductor device using an aluminum substrate which is less expensive than a single crystal germanium substrate as a supporting substrate has a lower cost than a conventional semiconductor device using a single crystal germanium substrate as a supporting substrate. Further, as shown in Fig. 1, a separation trench 33 having a depth reaching the insulating layer 38 is formed, whereby the semiconductor element 34 can be dielectrically separated. Thus, the semiconductor element 34 can be completely dielectrically separated by the separation trench 33 and the insulating layer 38' which reach the insulating layer by the depth. Further, Fig. 20 is a cross-sectional schematic view showing a semiconductor device having a structure of a smart 蜇 power 1c in which a vertical IGBT is formed, in another example of the semiconductor device of the present invention. 13 201009927 In this embodiment, an etching stopper layer 31a, an n buffer layer 55a, and a crystal layer 32 are formed on the support substrate 20 via an insulating layer. Further, an electrode wiring 15 is formed in the epitaxial layer 32. Further, on the surface of the epitaxial layer 32, an IGBT region 51 in which a vertical IGBT is formed is formed; and a region in which the IGBT region is dielectrically separated by the separation trench 33 is formed, and a CMOS CMOS region 52 is formed. . Further, a gate 53 or an emitter 14b is formed in the IGBT region.
另外，藉由於形成分離用溝槽33並形成絕緣膜前，使 P型雜質自該分離用溝槽33表面擴散，從而形成雜質擴散 層55b ^該雜質擴散層55b與蝕刻終止層31a連接。因為 此種雜質擴散層55b電阻低，故而於磊晶層32表面形成縱 型電晶體時可用作集極，藉此能夠通過下部的蝕刻終止層 31a、雜質擴散層55b，將大電流引出至表面側。 如此之本發明之半導邇裝置，可藉由以下所示之方法 製造’當然並非限定於此種方法。 首先，準備用於成長磊晶層之單晶矽基板。 此時準備之單晶梦基板，係一般使用者即可，例如可 為自以CZ法育成的單晶石夕棒切片製成者。另外，其導電 型、比電阻率等電性特性值、結晶方位或結晶直徑等可 根據設計之半導體元件來作適當選擇。 w 毕備Further, the P-type impurity is diffused from the surface of the separation trench 33 by forming the separation trench 33 and the insulating film is formed, thereby forming the impurity diffusion layer 55b. The impurity diffusion layer 55b is connected to the etching stopper layer 31a. Since the impurity diffusion layer 55b has a low electric resistance, it can be used as a collector when a vertical transistor is formed on the surface of the epitaxial layer 32, whereby a large current can be extracted to the lower etching stopper layer 31a and the impurity diffusion layer 55b. Surface side. Such a semi-conductive device of the present invention can be manufactured by the method shown below. Of course, it is not limited to such a method. First, a single crystal germanium substrate for growing an epitaxial layer is prepared. The single crystal dream substrate prepared at this time may be a general user, and may be, for example, a single crystal stalk slice produced by the CZ method. Further, electrical characteristics such as conductivity type and specific resistivity, crystal orientation, crystal diameter, and the like can be appropriately selected depending on the designed semiconductor element. w
TfW〜丁 签扳的表面 後之餘刻製程中使㈣停止之_終止層。 作為該蝕刻終止層之形成方法， 電性雜質自所準備之單m 了採用例如藉由使導 備之早s曰矽基板的表面擴散 14 201009927 蟲晶層的方法。 然後，於餘刻終止層之表面，成長磊晶層。 該磊晶層通過一般條件形成即可，另外，其導電型亦 可根據設計之半導體元件來作適當選擇。 然後，將形成於磊晶層表面之半導體元件的介電分離 用溝槽，形成為具有貫通蝕刻終止層之深度後，於分離用 溝槽内部形成絕緣膜。此時，亦可於形成膜前使摻雜劑雜 質自溝槽内面擴散，以形成用來引出下部電極之擴散層。 ® 然後，於溝槽分離型的製程中，在磊晶層表面形成半導體 元件》 之後，將形成有半導體元件側之表面與保持基板貼合。 用於該保持基板之貼合之保持基板，可使用例如玻璃 基板或石英基板等》 此外，較好的是於貼合時，於形成有半導體元件之表 面塗佈黏接劑或蠟，然後再與保持基板貼合。此時，較好 的是使用紫外線硬化型黏接劑來作為黏接劑。而且，較好 • 的是於塗佈黏接劑或蠟之前，於形成有半導體元件之表 面，形成鈍化膜》 然後’將單晶矽基板之形成有磊晶層之面的相反面， 磨削、研磨至特定厚度。該磨削、研磨係指實施磨削與研 磨t之至少一種。 然後’钱刻經過磨削、研磨之面。此時，使用蝕刻終 止層用之钱刻液’必要時可於基板與電解液之間施加電 位’蝕刻至目標的蝕刻終止層之表面。 15 201009927 進而，為了使分離用溝槽的頂端平滑化，較好的是實 施一定程度之研磨。 其後，於露出蝕刻終止層之側的表面，形成絕緣層。 較好的是，採用蒸鍍、濺鍍等低溫製程來形成絕緣層。 例如，較好的是藉由濺鍍、電漿cVD或蒸鍍來形成Si〇2 或 SiN。 無論採用何種手法來形成絕緣層，蝕刻終止面都必須 於形成絕緣層前除去異物、雜質等。而且，即便於低溫處 ® 理時，亦必須實施表面處理，以確保充分的黏接力。因此， 能夠使用例如單片式洗淨機。 此外’為提高黏接力，於形成絕緣層後可實施脈衝退 火。 钱刻終止面是要形成有關元件、元件動作之區域，因 此為確保元件之可靠性等，亦需要考慮確保清潔度、抑制 傷害等之對策。 形成絕緣層後，進行金屬膜的堆積，進而於需要時可 ® 實施退火’但該退火不可使與保持基板黏接之黏接劑（紫 外線硬化型）劣化.於下一製程中，與支撐基板貼合時， 考慮到元件散熱之觀點，較好的是使用焊錫等金屬性黏接 劑。因為使用該等金屬性黏接劑，故而可使用與黏接劑之 濁濕性佳的適當材料例如金屬膜來覆蓋絕緣層。 然後，利用黏接劑，將形成有絕緣層之侧的表面與支 樓基板貼合。較好的是，黏接劑使用熱傳導性佳者，代表 者如淳錫，但需根據基板的材質等來選擇適當之的黏接劑 16 201009927 (亦可為樹脂系）》 此外，該支撐基板的厚度具有必要的機械性強度即 可，而其材質亦可並㈣，而是銘等金屬、樹脂。 黏貼支撐基板後，將黏貼於元件表面侧之保持基㈣ _。此時’是以不會影響形成有元件之以晶層與元件背 ㈣之支撐基板的黏接狀態的方式，來進行剝離。作為其 -例’可列舉透過玻璃保持基板照射雷射光，來剝離該玻 璃保持基板之方法。 ® 於該階段中，在半導體裝置表面會露出元件的圖案。 然後，使用切割機實施切割，形成晶片，藉此獲得完 全分離型之功率ic晶片。 若使用此方法，則即便是製作一種完全介電分離型 1C，其要形成元件之磊晶層的區域較薄，亦可利用控制其 厚度’而能夠獲得所期望之值，因此能夠適用。 、 而且，背面磨削，基本上與先前的背面精削相同因 此僅需添加蝕刻終止製程與元件面側之保持基板之黏接、 粵条J離製程’另外，後者之製程已於IC卡用等晶片製作中得 以實用化，因此從成本方面來看，與使用2片單晶矽晶圓 之接合分離型之製程相比，能夠降低成本。 (實施方式1 ) 作為本發明之實施方式i，包含使用蝕刻終止之不同手 法之事例的說明，以下說明由BiCMOS型的溝槽介電分離 層與形成於基板背面之絕緣膜所包圍之完全介電元件分離 17 201009927 型IC及其製造製程、以及介電分離結構之“〇8型智慧型 功率1C及其製造製程的具體事例。 m '、 第2圖係形成有蝕刻終止層及磊晶層之基板的概余 於η—型蠢晶層12下’具有摻雜有高濃度錦之n+|iib 與摻雜有低濃度磷之η—層11a。基板使用高電阻之f型單 晶矽基板11。較好的是，該單晶矽基板使用雜質濃P度較磊 晶層12小一位以上者。TfW~ Ding The surface of the signboard is used to make the (4) stop layer. As a method of forming the etch stop layer, the electrical impurities are prepared from the surface of the substrate by, for example, spreading the surface of the substrate by the surface of the substrate. Then, on the surface of the layer, the epitaxial layer is grown. The epitaxial layer may be formed by general conditions, and the conductivity type may be appropriately selected depending on the designed semiconductor element. Then, the trench for dielectric separation of the semiconductor element formed on the surface of the epitaxial layer is formed to have a depth penetrating through the etch stop layer, and then an insulating film is formed inside the trench for separation. At this time, dopant impurities may be diffused from the inner surface of the trench before the formation of the film to form a diffusion layer for extracting the lower electrode. Then, in the trench isolation type process, a semiconductor element is formed on the surface of the epitaxial layer, and then the surface on which the semiconductor element side is formed is bonded to the holding substrate. For the holding substrate to which the holding substrate is bonded, for example, a glass substrate or a quartz substrate can be used. Further, it is preferable to apply an adhesive or a wax to the surface on which the semiconductor element is formed during bonding, and then apply It is attached to the holding substrate. At this time, it is preferred to use an ultraviolet curable adhesive as an adhesive. Further, it is preferable to form a passivation film on the surface on which the semiconductor element is formed before applying the adhesive or wax. Then, 'the opposite side of the surface of the single crystal germanium substrate on which the epitaxial layer is formed, grinding Grind to a specific thickness. The grinding and grinding means at least one of grinding and grinding. Then the money was carved and ground. At this time, the surface of the etch stop layer of the target is etched by applying a potential of 'etching a potential between the substrate and the electrolyte if necessary. 15 201009927 Further, in order to smooth the tip end of the separation groove, it is preferable to perform polishing to a certain extent. Thereafter, an insulating layer is formed on the surface on the side where the etching stopper layer is exposed. Preferably, the insulating layer is formed by a low temperature process such as evaporation or sputtering. For example, it is preferred to form Si〇2 or SiN by sputtering, plasma cVD or evaporation. Regardless of the method used to form the insulating layer, the etch stop surface must remove foreign matter, impurities, and the like before forming the insulating layer. Moreover, even at low temperatures, surface treatment must be applied to ensure adequate adhesion. Therefore, for example, a one-piece washing machine can be used. In addition, in order to improve the adhesion, pulse annealing can be performed after the formation of the insulating layer. In order to ensure the reliability of the components, etc., it is necessary to take measures to ensure cleanliness and damage prevention. After the insulating layer is formed, the metal film is deposited, and the annealing can be performed when necessary. However, the annealing does not deteriorate the bonding agent (ultraviolet curing type) adhering to the holding substrate. In the next process, the supporting substrate When bonding, it is preferable to use a metallic adhesive such as solder in consideration of heat dissipation of the component. Since such a metallic adhesive is used, it is possible to cover the insulating layer with a suitable material such as a metal film which is excellent in wettability of the adhesive. Then, the surface on the side on which the insulating layer is formed is bonded to the support substrate by means of an adhesive. Preferably, the adhesive is excellent in thermal conductivity, such as bismuth tin, but it is necessary to select an appropriate adhesive according to the material of the substrate. 201009927 (also a resin system) Further, the support substrate The thickness may have the necessary mechanical strength, and the material thereof may be (4), but a metal or a resin such as Ming. After pasting the support substrate, it will adhere to the holding base (4) _ on the surface side of the component. At this time, peeling is performed so as not to affect the bonding state of the support substrate on which the element is formed and the back surface of the element (4). As an example thereof, a method of irradiating laser light through a glass holding substrate to peel the glass holding substrate can be mentioned. ® At this stage, the pattern of the component is exposed on the surface of the semiconductor device. Then, cutting is performed using a cutter to form a wafer, thereby obtaining a fully separated power ic wafer. According to this method, even if a complete dielectric separation type 1C is produced, the area of the epitaxial layer in which the element is to be formed is thin, and the desired thickness can be obtained by controlling the thickness ', and thus it is applicable. Moreover, the back grinding is basically the same as the previous back surface finishing, so it is only necessary to add the etching termination process and the bonding of the substrate on the surface side of the component, and the process of the separation process is made. In addition, the latter process has been used for the IC card. Since it has been put into practical use in the production of wafers, it is possible to reduce the cost compared with the process of using a joint separation type using two single crystal germanium wafers in terms of cost. (Embodiment 1) As an embodiment of the present invention, an example in which different methods of etching termination are used will be described. Hereinafter, a description will be given of a complete dielectric surrounded by a trench dielectric separation layer of a BiCMOS type and an insulating film formed on the back surface of a substrate. Electrical component separation 17 201009927 IC and its manufacturing process, as well as dielectric separation structure "〇8 type smart power 1C and its manufacturing process specific examples. m ', Figure 2 is formed with an etch stop layer and an epitaxial layer The substrate of the substrate is under the n-type doped layer 12, which has a high concentration of n+|iib and a low concentration of phosphorus-doped layer 11a. The substrate uses a high-resistance f-type single crystal germanium substrate. 11. Preferably, the single crystal germanium substrate uses one or more impurities having a higher P degree than the epitaxial layer 12.
第3圖係表示將分離用溝槽13形成為略深於高濃度録 層lib、银刻終止層11a’並且於摻雜磷而可發揮没集器 (sinker)的功能後，形成有熱氧化膜之階段的結構者。此 時’於形成分離用溝槽13後’首先於該溝槽内形成例如梦 氧化膜來作為絕緣膜13a®然後’於該溝槽内填充多曰發 13b，藉此能夠將其後形成之半導體元件14實施介電分離。 第4圖係形成有基極14a、射極14b等半導體元件μ 之階段的圖。該階段’基本上沿用一般雙極1C之製造製 程。於該製程中形成CMOS，但於圖中將其省略。 第5圖係實施電極配線15後之階段的概念圖。電極配 線亦可為2層以上之多層配線。電極較好的是金電極。形 成配線電極後，進一步蒸鍍能夠容易地溶於酸、鹼中之锡 等金屬。 第6圖係於形成有半導體元件14之側的表面，利用塗 佈有UV硬化型液體黏接劑之黏接層16來黏貼玻璃製的保 持基板17後之階段的圖。 其後’吸附保持基板17側，利用平面磨削盤將p型單 18 201009927 晶砍基板11的殘餘部分磨削至i 〇 # m以下。該階段之結 構表不於第7圖。 其後’藉由電化學蝕刻將經過平面磨削後的面實施蝕 刻’而利用#刻除去單晶矽基板的殘留部分。此蝕刻係將 基板浸潰於約70°C之ΚΟΗ溶液中，來蝕刻ρ層（ρ型單晶 矽基板的殘留部）。此時’為阻止η層之蝕刻，必須於n-層11a側施加電位。為此，可於形成電極配線後，對基板 的整個面裝設導電性樹脂24，而可對ιΓ層1 la侧施加電 ® 位。第14圖表示實施該蝕刻終止之裝置的概要圖。浸潰於 姓刻溶液25中之基板可藉由上述導電性樹脂24而實施電 性接觸。並且’透過電源電路26及碳電極27施加電壓， 藉此阻止η層之姓刻。 第8圖係表示蝕刻結束時之圖。於該階段中，因為分 離用溝槽13之氧化膜還未露出至表面，所以較好的是研磨 單晶砍基板之殘留部分來使溝槽13露出（第9圖該研 _ 磨亦可為CMP研磨，較好的是使用機械性要素強者。 通過研磨等’在溝槽13的頂端已完全露出的階段中， 利用濺鍍或蒸鍍，以不會使黏接層16劣化劣化的方式，形 成Si〇2層18來作為絕緣層（第1〇圖）。 然後，於下一製程中，當要利用焊錫來黏接支撐基板 的情況，蒸鍍與浑錫之濕潤性良好的銀等，來形成烊錫層 19 (第 11 圖）。 然後，將支撐基板20黏接至焊錫層19側《利用焊錫 黏接具有例如200 /zm左右厚度之鋁基板❶雖然該支撐基 19 201009927 板係金屬時熱傳導率良好故而有利於元件之散熱，但只要 有機械性強度時，則並非必須使用金屬。此後，利用切割 機實施切割’故而能夠考慮凹口、定向平面等來進行黏接 支撐基板。第12圖表不與支揮基板貼合後之階段的圖。 最後’自保持基板1 7侧照射雷射，將保持基板1 7及 黏接層16剝離。然後’較好的是利用氫氟醚 (hydr〇flU〇roether(HFE))等溶劑洗淨半導體裝置。藉此， 完成半導體裝置。 之後’使用通常之製程製成晶片後，進入封裝製程即 可〇 (實施方式2 ) 以下，作為本發明之實施方式2，說明M〇s系智慧型 功率1C之事例。 此時，作為侧終止層，若使用p+層，則製程比較簡 單。於-般MOS製作方面，較好的是蟲晶層係p型者，因 此第15圖表示作為？型之初期階段之基板的概要圖。該基 板係於r型單晶㊉基板31上形成P+層3U，來作為餘刻 終止層’並於其上形成p-層32來作為磊晶層者。 此時，較好的是，通過較高劑量之離子佈植來形成作 為，：止層之，層31a，，但亦可藉由使p 之方式來形成該_終止層。而且，較好岐，餘刻络止 層的口型雜質壤度為5Χ1〜以上者。作 、p 雜質，較好的是硼。 π弋p型 20 201009927 於其後之溝槽33之形成中，形成為若干穿Fig. 3 is a view showing that the separation trench 13 is formed to be slightly deeper than the high-concentration recording layer lib, the silver engraving stop layer 11a', and after being doped with phosphorus to function as a sinker, thermal oxidation is formed. The structure of the stage of the membrane. At this time, 'after forming the separation trenches 13', first, for example, a dream oxide film is formed in the trenches as the insulating film 13a®, and then the plurality of bursts 13b are filled in the trenches, whereby the formation can be formed thereafter. The semiconductor element 14 is subjected to dielectric separation. Fig. 4 is a view showing a stage in which semiconductor elements μ such as the base 14a and the emitter 14b are formed. This stage 'substantially follows the general bipolar 1C manufacturing process. CMOS is formed in this process, but is omitted in the figure. Fig. 5 is a conceptual diagram showing a stage after the electrode wiring 15 is implemented. The electrode wiring may be a multilayer wiring of two or more layers. The electrode is preferably a gold electrode. After the wiring electrode is formed, a metal such as tin which can be easily dissolved in an acid or an alkali can be further vapor-deposited. Fig. 6 is a view showing a state in which the glass-made holding substrate 17 is adhered to the surface on the side on which the semiconductor element 14 is formed, by the adhesive layer 16 coated with the UV-curable liquid adhesive. Thereafter, the side of the adsorption holding substrate 17 was ground, and the residual portion of the p-type single sheet 2010 2010927 crystal-cut substrate 11 was ground to i 〇 # m or less. The structure of this stage is not shown in Figure 7. Thereafter, the surface after the plane grinding was etched by electrochemical etching, and the residual portion of the single crystal germanium substrate was removed by # etching. This etching etches the substrate in a ruthenium solution at about 70 ° C to etch the p layer (the residual portion of the p-type single crystal germanium substrate). At this time, in order to prevent the etching of the n layer, it is necessary to apply a potential to the n-layer 11a side. For this reason, after the electrode wiring is formed, the conductive resin 24 is placed on the entire surface of the substrate, and the electric potential can be applied to the ι layer 1 la side. Fig. 14 is a schematic view showing an apparatus for performing the etching termination. The substrate impregnated in the surname solution 25 can be electrically contacted by the above-mentioned conductive resin 24. And a voltage is applied through the power supply circuit 26 and the carbon electrode 27, thereby preventing the gradation of the η layer. Fig. 8 is a view showing the end of etching. In this stage, since the oxide film of the separation trench 13 is not exposed to the surface, it is preferable to polish the remaining portion of the single-crystal chopped substrate to expose the trench 13 (Fig. 9) In the CMP polishing, it is preferable to use a mechanical element. In the stage where the tip end of the trench 13 is completely exposed by polishing or the like, sputtering or vapor deposition is used so as not to deteriorate the adhesion layer 16 in a deteriorated manner. The Si 〇 2 layer 18 is formed as an insulating layer (Fig. 1). Then, in the next process, when solder is used to bond the support substrate, silver and other wet soldering materials are deposited. To form the tin-tin layer 19 (Fig. 11). Then, the support substrate 20 is adhered to the solder layer 19 side. "Aluminum substrate having a thickness of, for example, about 200 /zm is bonded by soldering, although the support base 19 201009927 is a metal plate. When the thermal conductivity is good, the heat dissipation of the element is facilitated. However, if there is mechanical strength, it is not necessary to use a metal. Thereafter, the cutting is performed by a cutter, so that the support substrate can be bonded in consideration of the notch, the orientation flat, and the like. 12 The figure is not shown in the stage after bonding to the supporting substrate. Finally, the laser is irradiated from the side of the holding substrate 17 to peel off the holding substrate 17 and the adhesive layer 16. Then, it is preferable to use hydrofluoroether (hydr) The semiconductor device is cleaned by a solvent such as 〇flU〇roether (HFE). Thereby, the semiconductor device is completed. Then, after the wafer is formed by a usual process, the package process is completed (Embodiment 2). In the second embodiment, an example of the M〇s-based smart power 1C will be described. In this case, if the p+ layer is used as the side termination layer, the process is relatively simple. In the case of general MOS fabrication, the crystal layer p is preferable. In the figure, Fig. 15 is a schematic view showing a substrate as an initial stage of the pattern. The substrate is formed on the r-type single crystal ten substrate 31 to form a P+ layer 3U as a residual stop layer 'and a p is formed thereon. - Layer 32 is used as the epitaxial layer. At this time, it is preferred that the layer 31a be formed by a higher dose of ion implantation, but may also be formed by means of p. The _ termination layer. Moreover, it is better, the residual impurity of the barrier layer 5Χ1~ degree or more. As, p impurity, preferably boron. After the trench is formed thereon 20201009927 33 of p-type π Yi form several wear
31a’狀。其後之製程基本上按照實 P 16圖)。 “式1之順序（第 於p—層32上形成半導體元件34後’完成表面側的電 極的形成，然後於形成有半導體元件34 P續j 2上形成 黏接層3 6。然後黏接至保持基板3 7。 黏貼保持基板37後，同樣地通過平面磨削之方式，磨 削單晶矽基板31的背面侧，於p +層31a，的下部殘留$私 ® 瓜以下之單晶矽層（第17圖）。然後，使用乙二胺與焦兒 茶盼混合溶液（EDP )、或NaOH水溶液來實施蝕刻，藉此 於P +層3 1 a’停止姓刻。該钮刻中亦可使用k〇h。 此時’如第19圖所示，準備NaOH來作為蝕刻液46， 通過浸潰基板之方式來實施钱刻’因此可批次處理餘刻製 程。蝕刻後利用研磨p+層3 la’將其部分除去。然後較好 的是導入使溝槽33的頂端完全露出之製程，例如機械研磨 等。 然後，與實施方式1相同，於低溫下通過濺鍍或蒸鍍 等方法來形成矽氧化膜等之絕緣層38,將半導體元件34 完全地介電分離（第18圖）。 然後’為了支撐最終元件，將其黏接至支撐基板’然 後除去半導體元件側之保持基板，完成半導體裝置。 然後，使用切割機、雷射切割機等製成晶片，從而能 夠製作出與使用SOI基板之情形相同之元件介電分離型積 體電路。 21 201009927 另夕卜’本發明並非限定 方彳# i, 於逑實施方式者。上述實施 方式僅為例示’凡是具有與 枯俶祕田鉍也 力丹不發明之申清專利範圍所述之 技術性思想實質相同 ^ Π之結構，且發揮同樣的作用效果者， 089 ''可’皆包含於本發明之技術範圍内。 【圖式簡單說明】 賴第刑i圓係本發明之半導雜裝置之-例也就是形成有 慧型功率ic結構之半導體裝置的剖面概要圖。 冰太、土 _係表不本發明之實施方式1之半導體裝置的製 泣方法之中途階段之結構的剖面圖。 第3圖係表示本發明之實施方式i之半導體裝置的製 造方法之中途階段之結構的剖面圖。 ®係表不本發明之實施方式！之半導體裝置的製 法之中途階段之結構的剖面圖。 _係表不本發明之實施方式1之半導體裝置的製 造方法之中途階段之結構的剖面圖。 圖係表不本發明之實施方式1之半導體裝置的製 .法之中途階段之結構的剖面圖。 ®係表不本發明之實施方式1之半導體裝置的製 造万法之中途階段之結構的剖面圖。 谇太、土胃係表不本發明之實施方式1之半導體裝置的製 邊方法之中途階段之結構的剖面圖。 第9圖.係表示本發明^+ t .也古、土 货Θ之實施方式1之半導體裝置的製 这万法之中途階段之結構的剖面圖。 22 20100992731a' shape. Subsequent processes are basically in accordance with the actual P 16 diagram). "The sequence of the formula 1 (after forming the semiconductor element 34 on the p-layer 32) completes the formation of the electrode on the surface side, and then forms the adhesive layer 36 on the semiconductor element 34 P continued to form a bonding layer 36. Then, it is bonded to The substrate 37 is held. After the substrate 37 is adhered, the back side of the single crystal germanium substrate 31 is ground by the same method, and the single crystal layer of the lower layer of the p + layer 31a remains. (Fig. 17.) Then, etching is carried out using ethylene diamine and pyroanthus tea mixture solution (EDP) or aqueous NaOH solution, thereby stopping the surname in the P + layer 3 1 a'. At this time, as shown in Fig. 19, NaOH is prepared as the etching liquid 46, and the etching process is performed by dipping the substrate. Therefore, the batch process can be batch-processed. After etching, the p+ layer 3 is used. La' is partially removed. It is preferably introduced into a process of completely exposing the tip end of the groove 33, for example, mechanical polishing, etc. Then, in the same manner as in the first embodiment, it is formed by sputtering or vapor deposition at a low temperature. An insulating layer 38 such as a tantalum oxide film, the semiconductor element 34 is completely Electrical separation (Fig. 18). Then, in order to support the final element, it is bonded to the support substrate, and then the holding substrate on the side of the semiconductor element is removed to complete the semiconductor device. Then, the wafer is formed using a cutter, a laser cutter, or the like. Therefore, it is possible to manufacture an element dielectric separation type integrated circuit similar to the case of using an SOI substrate. 21 201009927 The present invention is not limited to the embodiment, and the above embodiment is merely an example. 089 '' can be included in the present invention, and has the same technical effect as the technical idea described in the scope of the patent application of the invention. In the technical scope. [Simplified illustration of the drawing] Lai Ding's pentatype is a schematic diagram of a section of a semiconductor device in which a Hui-type power ic structure is formed. A cross-sectional view of a structure in the middle of a weeping method of a semiconductor device according to Embodiment 1 of the present invention. FIG. 3 is a view showing a system of a semiconductor device according to Embodiment 1 of the present invention. A cross-sectional view of a structure in the middle of the method of the present invention. A cross-sectional view showing a structure of a semiconductor device in the middle of the manufacturing process of the present invention. The method of manufacturing the semiconductor device according to the first embodiment of the present invention is not shown. The cross-sectional view of the structure of the semiconductor device according to the first embodiment of the present invention is a cross-sectional view of the structure of the semiconductor device according to the first embodiment of the present invention. A cross-sectional view of the structure of the intermediate stage of the semiconductor device according to the first embodiment of the present invention. Fig. 9 is a cross-sectional view showing the structure of the semiconductor device. + t. A cross-sectional view of the structure of the semiconductor device of the first embodiment of the invention. 22 201009927
第10圖係表示本發明之實施方式工 造方法之中途階段之結構的剖面圖。 第11圖係表示本發明之實施方式工 造方法之中途階段之結構的剖面圖。 第u圖係表示本發明之實施方式ι 迻方法之中途階段之結構的剖面圖。 第13圖係表示本發明之實施方式i 造方法之最終階段之結構的剖面圖。 第14圖係實施本發明之實施方式1 造方法之蝕刻時使用之裝置的概要圖。 第15圖係表示本發明之實施方式2 造方法之中途階段之結構的剖面圖。 第16圖係表示本發明之實施方式2 造方法之中途階段之結構的剖面圓。 第17圖係表示本發明之實施方式2 造方法之中途階段之結構的剖面圊。 第18圖係表示本發明之實施方式2 造方法之中途階段之結構的剖面圖。 之半導體裝置的製 之半導體裝置的製 之半導體裝置的製 之半導體裝置的製 之半導體裝置的製 之半導體裝置的製 之半導體裝置的製 之半導體裝置的製 之半導髏裝置的製 第19圖係表示本發明之實施方式2之半導體裝置的製 造方法之餘刻時所使用之裝置的概要圖。 第20圓係本發明之半導體裝置之另一例也就是具有形 成有縱型IGBT之智慧型功率積髏電路結構之半導體裝置 的剖面概要圖。 23 201009927 【主要元件符號說明】 10 半導體裝置 25 蝕刻溶液 11 早晶破基板 26 電源電路 11a n_層 27 碳電極 lib 高濃度銻層 31 单晶梦基板 12 蠢晶層 31a 钮刻終止層 13 分離用溝槽 31a' P+層 13a 絕緣膜 32 遙晶層 13b 多晶矽 33 分離用溝槽 14 半導體元件 34 半導體元件 14a 基極 36 黏接層 14b 射極 37 保持基板 15 電極配線 38 氧化膜 16 黏接層 46 蝕刻液 17 保持基板 51 IGBT區域 18 Si02 層 52 CMOS區域 19 焊錫層 53 閘極 20 支撐基板 55a η緩衝層 24 導電性樹脂 55b 雜質擴散層 24Fig. 10 is a cross-sectional view showing the structure of a middle stage of the working method of the embodiment of the present invention. Figure 11 is a cross-sectional view showing the structure of the intermediate stage of the working method of the embodiment of the present invention. Figure u is a cross-sectional view showing the structure of the intermediate stage of the embodiment of the present invention. Figure 13 is a cross-sectional view showing the structure of the final stage of the embodiment of the present invention. Fig. 14 is a schematic view showing an apparatus used in the etching of the first embodiment of the present invention. Fig. 15 is a cross-sectional view showing the structure of the middle of the method of the second embodiment of the present invention. Fig. 16 is a cross-sectional view showing the structure of the intermediate stage of the second embodiment of the present invention. Fig. 17 is a cross-sectional view showing the structure of the middle of the method of the second embodiment of the present invention. Figure 18 is a cross-sectional view showing the structure of the middle of the method of the second embodiment of the present invention. Manufactured from a semiconductor device made of a semiconductor device, manufactured by a semiconductor device, manufactured by a semiconductor device, manufactured by a semiconductor device, manufactured by a semiconductor device, manufactured by a semiconductor device, and manufactured as a semiconductor device. It is a schematic view of the apparatus used at the time of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. The 20th circle is another schematic view of a semiconductor device having a smart power accumulation circuit structure in which a vertical IGBT is formed, which is another example of the semiconductor device of the present invention. 23 201009927 [Description of main components] 10 Semiconductor device 25 Etching solution 11 Early crystal breaking substrate 26 Power circuit 11a n_Layer 27 Carbon electrode lib High concentration 锑 layer 31 Single crystal dream substrate 12 Stupid layer 31a Button stop layer 13 Separation The trench 31a' P+ layer 13a The insulating film 32 The crystal layer 13b The polysilicon 33 The trench for separation 14 The semiconductor element 34 The semiconductor element 14a The base 36 The adhesion layer 14b The emitter 37 The substrate 15 The electrode wiring 38 The oxide film 16 The adhesion layer 46 Etching liquid 17 Holding substrate 51 IGBT region 18 SiO 2 layer 52 CMOS region 19 Solder layer 53 Gate 20 Support substrate 55a η Buffer layer 24 Conductive resin 55b Impurity diffusion layer 24
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| JP4631113B2 (en) * | 1999-10-26 | 2011-02-16 | 株式会社デンソー | Manufacturing method of semiconductor device |
| JP2005167090A (en) * | 2003-12-04 | 2005-06-23 | Hamamatsu Photonics Kk | Semiconductor light receiving element and manufacturing method therefor |
| JP2007201220A (en) * | 2006-01-27 | 2007-08-09 | Mitsubishi Electric Corp | Semiconductor device |
-
2008
- 2008-06-18 JP JP2008158887A patent/JP5386862B2/en active Active
-
2009
- 2009-04-20 WO PCT/JP2009/001794 patent/WO2009153909A1/en active Application Filing
- 2009-04-30 TW TW98114437A patent/TW201009927A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010003727A (en) | 2010-01-07 |
| JP5386862B2 (en) | 2014-01-15 |
| WO2009153909A1 (en) | 2009-12-23 |
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