JP2011210770A - Method of manufacturing semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor element, which has small wafer warpage and wafer cracking even when using a wafer which already has a large diameter and is thinned when fed to wafer processes.SOLUTION: The method of manufacturing the semiconductor element includes forming an outer peripheral end 3 by reducing a thickness of an outer periphery of a semiconductor substrate 1, and bonding a metal 4, which has a larger coefficient of thermal expansion than the semiconductor substrate and also has a melting point higher than a maximum temperature applied in a heat treatment process among processes of forming a plurality of semiconductor elements 1, to the outer peripheral end 3 to such a film thickness that the semiconductor elements of the semiconductor substrate 1 do not protrude from both principal surface where the semiconductor elements are formed before a process of forming the plurality of semiconductor elements on the semiconductor substrate 1.

Description

  The present invention relates to a method for manufacturing a semiconductor device using a thin wafer having a large diameter from the time of introduction into a process.

In a power semiconductor device (hereinafter, a semiconductor device is synonymous with a semiconductor element), the direction in which a drift current flows when turned on is the same as the direction in which a depletion layer extends due to a reverse bias voltage when turned off. It is also called a semiconductor device. For example, in the case of a normal planar gate type n-channel vertical MOSFET, the portion of the high-resistance n ⁻ drift layer functions as a region for flowing a drift current in the vertical direction when the MOSFET is in the on state, and is depleted in the off state. To be a region for holding a withstand voltage. The high resistance of the n ^- possible to shorten the current path of the drift layer or high-resistance n ^- thinning the drift layer, since the drift resistance decreases leading to the effect of lowering the substantial on-resistance of the MOSFET. It is known that such a low on-resistance configuration is similarly established not only in the above-described MOSFET but also in vertical semiconductor elements such as IGBTs, bipolar transistors, and diodes. The breakdown voltage of the vertical semiconductor device is related to the thickness of the drift layer. Even in the case of a 1800 V class semiconductor device, the thickness of the finished wafer (semiconductor substrate) is 180 μm, 120 V at 1200 V, and 60 μm at 600 V.

  On the other hand, an FZ crystal is generally used as a wafer in a power semiconductor device that requires a uniform resistance distribution. Wafers using FZ crystals are more difficult to increase in diameter than those using CZ crystals, but are still increasing in diameter to reduce chip costs. However, for example, when a 6-inch or 8-inch diameter FZ crystal wafer, for example, a 120 μm thick wafer is put into the wafer process and subjected to the required processing, the wafer flow is reduced and the process flow is completed. Thus, it is difficult to manufacture a semiconductor device. If there are many wafer cracks, the number of wafers that cannot be completed increases, and the number of completed semiconductor devices tends to decrease greatly. Therefore, conventionally, the wafer is usually thick, for example, by increasing the wafer strength by increasing the thickness of the 6-inch diameter to about 625 μm and the 8-inch diameter to about 725 μm, so that even if the wafer is flowed through the manufacturing process, the wafer A method of reducing cracking is employed. Furthermore, for example, the manufacturing process proceeds only on one side of the wafer in the first half of the manufacturing process, and before moving to the manufacturing process on the back side in the second half of the manufacturing process, the back side is polished and etched to a thickness that is nearly the finished wafer thickness. The wafer has been thinned to Thereafter, a necessary manufacturing process is added to the back side of the thinned wafer, thereby reducing the number of process steps in the thinned wafer state and preventing the wafer from cracking as much as possible. However, this method uses a thick wafer as a finished wafer by scraping more than two thirds of the thickness during the manufacturing process, resulting in wasteful consumption of expensive semiconductor substrate materials. become.

  In this regard, in order to reduce the warpage of the thin wafer, which becomes a problem when the process input is made into a thin wafer, the resin is applied in a ring shape on the outer periphery of the wafer in a flattened state and cured, A processing method for forming a reinforcing portion of a substrate is known. Also known is a processing method in which the thick outer peripheral part becomes a reinforcing part, such as a thinned wafer, in which only the inner peripheral part is cut to a required thickness so as to leave a thick substrate portion in a ring shape on the outer peripheral part of the wafer. (Patent Document 1). In addition, in the case of a bonded wafer that is reinforced by attaching a glass support plate to a thinned wafer, a resin is attached in a ring shape to the outer peripheral edge of the wafer in order to prevent wafer cracking and chemical penetration from the bonding interface at the outer peripheral portion. A processing method is known that cures in a sealed state (Patent Document 2). A document describing a method for increasing the wafer strength and flowing it to the manufacturing process by thickening only the outer peripheral portion of the wafer in a ring shape to be a reinforcing portion and a jig for the same is disclosed (Patent Literature). 3).

JP 2001-257185 A JP 2006-352078 A US Publication No. 2008-64184

  However, in order to prevent the wafer warpage that is likely to occur on a thin wafer, the method of attaching the resin to the outer peripheral edge of the wafer in a ring shape and curing it is difficult for the manufacturing process because the thickness of the ring-shaped cured resin is larger than the thickness of the wafer. In order to flow, a jig for adjusting to a specific transfer device and a process device is required. Furthermore, there is a problem that process conditions are limited by the temperature characteristics of the ring-shaped resin adhered to the outer peripheral edge of the wafer. Further, in a wafer in which a glass support plate is attached to a thinned wafer with an adhesive to increase the strength, the heat resistance temperature of the adhesive is also a problem in the subsequent processes. Furthermore, in the case of a bonded wafer, unless the outer periphery of the wafer is sealed, there is a problem that the processed surface of the wafer deteriorates by penetrating into the bonded wafer due to the nature of the chemical used in the subsequent processes. In any case, if the wafer process can be completed without a wafer crack even if a thin wafer close to the finished wafer thickness after the process is completed is introduced from the beginning of the process, the thick wafer is ground back in the latter half of the process. Obviously, the cost is reduced because the semiconductor crystal material cost for discarding two-thirds of the thickness is reduced.

  The present invention has been made in view of the above points, and provides a method for manufacturing a semiconductor element with less wafer warpage and wafer cracking even when a thin wafer having a large diameter is used from the time of introduction into the process. is there.

  In order to achieve the object of the present invention, before the step of forming a plurality of semiconductor elements on a semiconductor substrate, the outer periphery of the semiconductor substrate is reduced in thickness to form an outer peripheral end, Both main surfaces of the semiconductor substrate on which the semiconductor element is formed are made of a metal having a thermal expansion coefficient larger than that of the semiconductor substrate and having a melting point higher than the highest temperature applied in the heat treatment step in the step of forming the semiconductor element. A method for manufacturing a semiconductor element to be deposited with a film thickness that does not protrude further is provided.

  A plurality of the semiconductor substrates having the same diameter provided with the outer peripheral end portion are stacked, the outer peripheral end portion is exposed and sandwiched by a rotating jig from the main surface direction, and at least a region where the semiconductor element is formed is masked, It is preferable that the stacked semiconductor substrate is rotated about a direction sandwiched between the rotating jigs, and the metal is deposited on the outer peripheral edge by sputtering. Moreover, it is also preferable that the sputtering is sequentially performed from the respective principal surface sides by inclined sputtering at an angle that does not reach the close contact portion of the stacked semiconductor substrates.

  Preferably, the plurality of semiconductor substrates are stacked with a buffer film having heat resistance equal to or higher than the temperature of the semiconductor substrate rising during the sputtering.

  Furthermore, it is desirable that the semiconductor substrate has a thickness that does not require a grinding step for reducing the thickness in the step of forming the semiconductor element. Further, the outer peripheral end of the semiconductor substrate has a shape composed of an inclined portion extending from each of the main surfaces and an end surface perpendicular to the main surfaces, or a shape formed of a curvature portion extending from each of the main surfaces. It is also preferable to adopt a method for manufacturing a processed semiconductor element. The semiconductor element can be an IGBT.

  According to the present invention, it is possible to provide a method for manufacturing a semiconductor element with less wafer warpage and wafer cracking even when a thin wafer having a large diameter is used from the start of the process.

It is sectional drawing of the wafer rotation jig concerning this invention. It is sectional drawing which shows the outer peripheral edge part of the wafer concerning this invention. It is sectional drawing which shows the processing method of the outer peripheral edge part of the wafer concerning this invention. It is sectional drawing which shows IGBT concerning this invention. It is sectional drawing of the different wafer rotation jig concerning this invention. It is a figure which shows the processing method of the outer peripheral edge part of the wafer concerning this invention.

  Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  A manufacturing method of a 1200 V class IGBT will be specifically described as a manufacturing method of the semiconductor element of the present invention. An n-type FZ silicon wafer 1 (hereinafter referred to as wafer 1) having a diameter of 8 inches and a thickness of 120 μm is prepared. In the case of this example, the thickness of the wafer 1 as the input wafer (semiconductor substrate) is almost the thickness when finished. In the manufacturing process, the surface may be polished or etched, but the thickness reduced by polishing or etching is very small (for example, about 5 μm by polishing to expose the silicon layer on the back surface). In other words, in the course of the manufacturing process, there is no need for a grinding step that significantly reduces the thickness of the wafer, so no material is wasted. Note that the thickness of the wafer to be loaded may be determined according to desired characteristics such as the breakdown voltage of the IGBT to be manufactured.

  FIG. 3 is a cross-sectional view showing a method of processing the outer peripheral edge of the wafer 1. As shown in FIG. 3 (a), the outer peripheral edge 3 of the wafer 1 is pushed while rotating the wafer 1 and the mold jig 2 against the mold jig 2 made of a grindstone in which fixed abrasive grains are dispersed in a bonding agent. The inclined portions 3a are formed on the surfaces of the outer peripheral end portions 3 on the both main surface sides of the wafer 1, respectively. Moreover, the outermost peripheral end surface 3c perpendicular to both main surfaces is formed on the outermost side. The outermost peripheral surface 3c may leave the end surface of the wafer 1 before the processing of the outer peripheral end portion, or may be a flat surface by grinding the slightly sharpened end surface with the mold jig 2.

  Alternatively, as shown in FIG. 3 (b), the mold jig 2 is formed with an R shape and chamfered in accordance with this, and the curvature portion 3 b is formed at the outer peripheral end portions 3 on both main surfaces of the wafer 1. It may be formed.

  As described above, the inclined portion 3a, the curved portion 3b, and the outermost peripheral surface 3c are formed on the outer peripheral end portions 3 on the both main surface sides of the wafer 1 because the outermost outer periphery of the wafer 1 is sharpened like a knife. This is to prevent the holder that holds the wafer 1 from being scraped off during the transfer, and to prevent the occurrence of cracks and chips.

  FIG. 6 is a diagram illustrating a method of processing the outer peripheral edge 3 of the wafer 1. After forming the outer peripheral end 3 as described above, as shown in FIG. 6, a polishing cloth 5 impregnated with an abrasive is provided in a cylindrical shape, and the cylindrical polishing cloth 5 is impregnated with an abrasive. , While pressing one wafer 1 while rotating, and relatively moving the polishing cloth 5 and the wafer 1 up and down, the processing damage remaining on the surface processed by the mold jig 2 is removed. It is desirable to do.

  Next, a plurality of wafers 1 having been subjected to the outer edge processing as described above are prepared. A heat-resistant film (not shown) (for example, a heat-resistant elastomer film) is sandwiched between the wafers 1 and stacked. This heat-resistant film has a function of preventing rubbing and scratches due to contact between wafers. If a step of finishing and polishing the surface of the wafer 1 is performed in a later step, the wafers can be stacked without the heat-resistant film.

  FIG. 1 is a cross-sectional view of the wafer rotating jig 30. Here, the wafer 1 is attached to the wafer rotating jig 30 with the heat-resistant film sandwiched therebetween. In the example of FIG. 1, 25 wafers 1 are stacked and attached, but a larger number of wafers 1 may be stacked and processed according to the capability of the sputtering apparatus. The wafer rotating jig 30 is disposed in the sputter deposition tank 50.

  The wafer 1 stacked with the heat-resistant film interposed therebetween is sandwiched between two wafer sandwiching disks 31a-31b.

  One end of the rotating shaft 20b is attached to the center of one wafer sandwiching plate 31a, and the other end of the rotating shaft 20b is held on one wall surface of the sputter deposition tank 50 via a bearing 33a and a bearing mount 34a. One end of a rotating shaft 20c is attached to the center of the other wafer sandwiching plate 31b, and the other end of the rotating shaft 20c is held on the other wall surface of the sputter deposition tank 50 via a bearing 33b and a bearing mount 34b. . The other rotating shaft 20c includes a shaft length adjusting screw 36 and a stopper 35 between the other wafer sandwiching plate 31b and the bearing 33b.

  The stacked wafers 1 are held between the two wafer sandwiching disks 31a-31b by the tightening force of the shaft length adjusting screw 36.

  Here, if the wafer sandwiching disks 31 a and 31 b are too small compared to the wafer 1, the stacked wafers 1 are locally pressed, and unnecessary stress is applied to the wafer 1. Therefore, it is desirable that the wafer sandwiching disks 31a and 31b make the pressing surface of the wafer 1 as large (wide) as possible and press the wafer 1 with the surface.

  Further, if the wafer sandwiching disks 31a and 31b are larger than the wafer 1, an unnecessary metal film can be prevented from being formed in a region other than the outer peripheral edge 3 in a sputtering process described later. In the sputtering process described later, it becomes an obstacle when performing sputtering from an oblique direction. Therefore, the wafer sandwiching disks 31a and 31b have the same size as the area where the wafer 1 is not chamfered (area other than the outer peripheral edge 3), or obstruction of sputtering in an oblique direction in the sputtering process described later. As long as it does not become, it may be slightly larger than the area where the wafer 1 is not chamfered (area other than the outer peripheral edge 3).

  For example, the wafer sandwiching disks 31a and 31b have the same size as the area where the wafer 1 is not chamfered.

  One end of the rotating shaft 20a is connected to a rotation driving motor (not shown) and the like, and a driving force is transmitted to the rotating shaft 20b via a gear 32 attached to the other end.

  When performing the sputter deposition process on the outer peripheral edge 3 of the 25 wafers sandwiched between the wafer rotation jigs 30 installed in the sputter deposition tank 50, the wafer rotation jig 30 shown in FIG. In the state of sandwiching the film, sputtering deposition is not performed on portions other than the outer peripheral edge 3 of the wafer 1 by a shielding plate (not shown).

  FIG. 5 is a cross-sectional view of a wafer rotating jig 40 different from that shown in FIG. The difference from the wafer rotating jig 30 is that the wafer 1 held by the wafer holding jig 31 is elastically held by a spring 38 instead of the adjusting screw 36. By pressing a bearing mount 34 including a bearing 38 with a spring 38, the wafer 1 is sandwiched between the wafer sandwiching disks 31a and 31b. Other parts that are the same as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. Further, in this wafer rotating jig 40, the rotating shaft 20d is directly exposed to the outside of the sputter deposition tank. However, like the wafer rotating jig 30 in FIG. You may let them. In the semiconductor element manufacturing method of the present invention, the wafer may be sandwiched and rotated by a jig having a rotation function, and a refractory metal may be sputter deposited on the outer peripheral edge of the wafer. The wafer rotation jigs in FIGS. 1 and 5 show examples thereof, and are not limited to these methods as long as they do not exceed the gist of the present invention.

  FIG. 2 is a cross-sectional view showing the outer peripheral edge of the wafer. While rotating the 25 wafers 1 attached as shown in FIG. 1, a material having a larger thermal expansion coefficient than that of the semiconductor substrate (wafer) is deposited on the outer peripheral edge 3 of the stacked wafers 1 by sputtering. As shown in FIGS. 2 (a) and 2 (b), the wafer is deposited from both main surface sides of the wafer 1 by oblique sputtering 37.

  The material having a higher thermal expansion coefficient than the wafer material (silicon) is selected as the material to be deposited on the outer peripheral edge 3 of the wafer 1 because a high melting point metal having a high linear expansion coefficient with respect to the wafer has a high tension. This is to show the function of correcting the warpage of the substrate. In a donut-shaped material, a force to spread outward acts at a temperature higher than room temperature as compared to a room temperature state. That is, the inner space expands in the direction of increasing the diameter. In the present invention, since a doughnut-like material having a high linear expansion coefficient is attached to the outer peripheral portion of the wafer, a force is applied to spread the inner wafer at a temperature higher than room temperature. That is, the warpage of the wafer is corrected.

  A material having a higher melting point than that of the wafer (semiconductor substrate) was selected because a subsequent heat treatment process (for example, thermal oxide film formation, impurities such as boron) This is to prevent the semiconductor characteristics from being adversely affected even if the thermal diffusion process exists. That is, even during the high-temperature heat treatment as described above, the refractory metal film deposited in a ring shape on the outer peripheral edge of the wafer does not thermally diffuse into the semiconductor substrate or form an alloy without melting. A material that does not evaporate and does not diffuse deeply into the wafer as an impurity element is desirable.

  Another reason for selecting a material having a higher melting point than that of the wafer (semiconductor substrate) is the portion formed in the deposition of different types of laminated films on wafers and the formation of laminated film patterns on wafers performed in a semiconductor process. This is because stress is accumulated in the silicon wafer due to the removal of the laminated film, and the wafer is deformed or warped. According to the present invention, it is possible to obtain a holding force for maintaining the original flat shape by attaching a high melting point material in advance to the outer peripheral portion of the wafer in a ring shape while the wafer is flat. Because.

  Further, as described above, the oblique sputtering 37 shown in FIGS. 1 and 2 is used at the close contact portion (point a in FIGS. 2A and 2B) on the outer peripheral end 3 side of the stacked wafers 1. This is to prevent the sputtered particles from reaching. As shown in FIG. 2 (c), a refractory metal is deposited on the inclined portion 3 a of each outer peripheral end 3 by the oblique sputtering 37.

  In this example, a titanium / titanium nitride film 4 was deposited. The film thickness ratio of titanium / titanium nitride in the titanium / titanium nitride film 4 is 1/1. Such oblique sputtering 37 can prevent adhesion between the wafers 1 due to metal sputtering. In order to prevent adhesion between the wafers 1 due to metal sputtering, it is further important that the total thickness including the deposited titanium / titanium nitride film 4 and the inclined portion 3 a of the wafer is thinner than the thickness of the wafer 1. If this total thickness is large, the titanium / titanium nitride films 4 deposited on the inclined portion 3a of the outer peripheral edge 3 of the wafer 1 adjacent to each other may be brought into contact with each other during sputtering. If the titanium / titanium nitride films 4 are bonded to each other, there is a possibility that a plurality of wafers cannot be separated, so this must be avoided.

  Even when the wafer 1 does not adhere, if the titanium / titanium nitride film 4 on the outer peripheral edge 3 protrudes from the thickness of the wafer, a special jig is required to flow the wafer 1 to the processing process, which increases costs. It is not preferable. That is, the thickness of the deposited metal (in this example, the titanium / titanium nitride film 4) (arrow T1 in FIG. 2C) does not exceed the thickness of the wafer 1 to be put into the process.

  However, on the other hand, when it is necessary to deposit a thick titanium / titanium nitride film beyond the thickness of the wafer 1, that is, when it is intended to secure a stronger warp reinforcement, In the case of forming a thick film, a film or a plate having a uniform thickness may be sandwiched between the wafer 1 and the wafer 1 in order to prevent adhesion between the wafers 1. If the wafer is heated (250 ° C. or lower) during sputtering or vapor deposition, an elastomer material or the like may be selected. In this case, the thickness of the wafer 1 can be increased so as to exceed the thickness of the wafer 1 within one half or less of the thickness of the film or plate sandwiched between the wafers 1.

  However, if the titanium / titanium nitride film is deposited thickly beyond the thickness of the wafer 1 in this way, the outer periphery of the wafer can be strongly reinforced, but if the wafer thickness needs to be reduced during the semiconductor element process, A special wafer thinning technique that avoids this part and performs back-grinding or etching is required.

  As the aforementioned refractory metal, in addition to titanium / titanium nitride, a single layer of tungsten, titanium, titanium nitride or the like, or a laminate of molybdenum tungsten / titanium, tungsten / molybdenum, or the like can be used. After the process of depositing the titanium / titanium nitride film 4 on the inclined portion 3a of the outer peripheral edge 3 of the wafer 1, the stacked wafers 1 are separated one by one to perform a normal surface process for semiconductor elements. Apply. When the wafer 1 is directly overlapped and the titanium / titanium nitride film 4 is deposited on the outer peripheral edge 3 of the wafer 1 without sandwiching the heat-resistant film, the front and back surfaces of the wafer 1 are placed on both sides before being put into the wafer process. It is desirable to perform final polishing by polishing. Polishing conditions may be a general polishing method. For example, abrasive: colloidal silica (particle size: 20 to 40 nm) pH of about 11 to 12, solvent: NaOH aqueous solution, polishing cloth: non-woven fabric or polyurethane foam type, thickness of about 1 mm, polishing time: about 10 minutes.

The following wafer process according to the present invention will be described by taking, as an example, the IGBT wafer process shown in the cross-sectional view of the main part of FIG. The surface of the IGBT 100 wafer shown in FIG. 4 is the upper side (emitter side) of the drawing, and the back surface of the wafer is the lower side (collector side). After forming an oxide film pattern on the surface of the main part of the wafer having a titanium / titanium nitride film deposited on the inclined part of the outer peripheral edge of the wafer, the p base region 102 and a p-type guard ring (inside the breakdown voltage region) (Not shown). A trench 103 having a depth reaching the n ⁻ base layer 101 (n ⁻ drift layer) from the surface of the p base region is formed. A gate insulating film 104 is formed in the trench 103 and high-concentration polysilicon serving as the gate electrode 105 is formed. After filling, an n ⁺ -type emitter region 106 is formed on the surface of the p base region 102 in contact with the trench 103. In order to improve the latch-up resistance, it is desirable that a high concentration p ⁺ -type region (not shown) is formed in a part of the surface layer of the p-type base region 102.

An interlayer insulating film 107 is coated on the gate electrode 105. Further, the surface of the interlayer insulating film 107 is covered with an emitter electrode 108 made of a metal film such as Al. The emitter electrode 108 is configured to be in conductive contact in common with the surface of the n ⁺ -type emitter region 106 and the surface of the p-type base region 102 through an opening provided in the interlayer insulating film 107. Further, a nitride film, an amorphous silicon film annealed in a nitrogen atmosphere, or a polyimide film is preferably formed on the emitter electrode 108 as a passivation film, but is omitted in FIG.

As a surface structure formed on the back surface side of the wafer (hereinafter referred to as a back surface element structure), an n ⁺ FS layer 109 (field stop layer) and a p ⁺ collector layer 110 are arranged in this order on the surface layer of the n ⁻ base layer 101. Is provided. The collector electrode 111 is in contact with the p ⁺ collector layer 110. An IGBT having such a back element structure is referred to as an FS (field stop) type IGBT. As a result, the ON layer and turn-off loss characteristics can be further improved by making the base layer thinner than the non-punch-through structure while achieving the effects of low injection of minority carriers and high transport efficiency.

One batch of 25 8 inch diameter, 120 μm thick FZ-n silicon wafers were sputter-deposited with the refractory metal as described above, and then a normal IGBT wafer with a withstand voltage of 1200 V class. A plurality of IGBT regions are completed on the silicon wafer by flowing to the wafer process excluding the back grinding step from the process. With respect to the wafer having the plurality of IGBT regions, the wafer warp size (mm) and the number of wafers cracked or chipped were examined. The value of the warp is a warp value for a wafer having no wafer cracks or chips. The warpage is determined by obtaining the horizontal component of the distance between the positions where the wafer is placed vertically, over the entire wafer, and the most protruding positions on the front and back sides, and the value obtained by subtracting the average thickness of the wafer from this value is taken as the warpage value. As a comparative example, 25 wafers having a thickness of 120 μm, which were not sputter-deposited with a refractory metal, were put into an IGBT process, and the wafer after the process was completed was examined. As the refractory metal, titanium / titanium nitride, tungsten, titanium, titanium nitride, molybdenum tungsten / titanium, and tungsten / molybdenum were examined. The melting point and thermal expansion coefficient (linear expansion coefficient) are 3430 ° C. and 0.045 × 10 ⁻⁴ K ^{−1 for} tungsten, 1812 ° C. and 0.084 × 10 ⁻⁴ K ⁻¹ for titanium, and 2930 ° C. for titanium nitride, respectively. 0.094 × 10 ⁻⁴ K ⁻¹ , molybdenum is 2620 ° C. and 0.051 × 10 ⁻⁴ K ⁻¹ , and the linear expansion coefficient of the silicon single crystal is 0.042 × 10 ⁻⁴ K ⁻¹ . The sputter deposit film thickness of each refractory metal was changed to 0.08 μm, 0.01 μm, 0.1 μm, 1.0 μm, and 3.0 μm, and the number of warped wafers and the number of cracked or chipped wafers And display). The results are shown in Table 1. In Table 1, the thickest part indicates the thickness of the thickest part of the sputter deposited film, as indicated by the arrow (T2) in FIG.

  Table 1 shows that when a high melting point metal film is not deposited on the outer peripheral edge of an 8-inch thin wafer, all the wafers of 25 batches are cracked or chipped. When the refractory metal film is deposited on the outer peripheral edge of the wafer, it is desirable to use a titanium / titanium nitride film because if the film thickness is 0.01 μm or more, there will be no cracks / chips on the wafer. Further, the film thickness is 3.0 μm, the warp is 1 mm, and there are no cracks / chips on the wafer, indicating the best results. When the thickness of the titanium / titanium nitride film is 3.0 μm, the warp value is as small as 1 mm. Therefore, the higher the refractory metal thermal expansion coefficient than the thermal expansion coefficient of the silicon wafer, the greater the warpage of the large diameter wafer. It is considered that the correction ability is high.

  In the case of a refractory metal other than the titanium / titanium nitride film, any metal film having a film thickness of 0.01 μm or more can be adopted because there are no wafer cracks / chips.

  The number of cracks / chips is zero when the film thickness of the refractory metal is 0.01 μm or more regardless of the warpage. When the tungsten film is deposited on the outer peripheral edge of the wafer, it indicates that there is no crack or chip even if the warpage is 23 mm. Therefore, the size of the warp itself up to about 20 mm directly affects the crack and chip. Seems to be unrelated. If the film thickness of the refractory metal film is 0.01 μm or more, the metal film reinforces a thin wafer and adheres the metal film even if the warp is large to some extent. This is presumably because there is a deterrent effect by polishing and removing the sharp corners at the outer peripheral edge of the wafer, which tends to cause cracks and chips.

  Even when there is no occurrence of cracking or chipping of the wafer, it can be seen from Table 1 that the warpage is up to about 23 mm to 1 mm, and a certain degree of warpage is inevitable. In addition, a wafer slot pitch of 6.35 mm or the like is generally used as a wafer slot pitch for inserting and holding a wafer cassette used as a kind of wafer transfer jig in an 8-inch wafer process. Since the width of the partition separating the wafer slots is 2.5 mm, a value obtained by subtracting this value becomes a gap for the wafer to enter. Therefore, when the warpage is 6.35 mm−2.5 mm = 3.85 mm or less, a cassette containing 25 sheets can be used. When the warp is more than this, a double pitch cassette with thinned partitions or a triple pitch cassette with thinned every other partition is used. The wafer slot pitch in the case of the double pitch cassette is 12.7 mm, and the wafer slot pitch in the case of the triple pitch cassette is 19.05 mm. Since the number of wafers that can be flowed through is reduced, there is a problem that the processing efficiency of the process deteriorates and the manufacturing cost increases. Therefore, the wafer warpage is desirably 3.85 mm or less from the viewpoint of process efficiency. Looking at Table 1 based on this, when titanium, titanium nitride, tungsten / molybdenum is used as the refractory metal, the film thickness is 3.0 mm or more, and when titanium / titanium nitride, tungsten / titanium is used, the film thickness is 1.0 mm. The above is true. If these refractory metals are used, the wafer warpage can be reduced to 3 mm or less with 0 wafer cracks. Therefore, even when an 8-inch wafer is put into the process, a normal 25 wafer cassette can be used. And process processing efficiency does not deteriorate.

DESCRIPTION OF SYMBOLS 1 Wafer 2 Type jig | tool 3 Outer peripheral edge part 3a Inclined part 3b Curvature part 3c Outermost outer peripheral end surface 4 Titanium / titanium nitride film 5 Polishing cloth 30 Wafer rotation jig 31a, 31b Wafer clamping disk 32 Gear 33, 33a, 33b Bearing 34 , 34a, 34b Bearing mount 35 Stopper 36 Length adjusting screw 37 Oblique sputter 50 Sputter deposition tank 100 IGBT
101 n ⁻ base layer 102 p base region 103 trench 104 gate insulating film 105 gate electrode 106 n ⁺ type emitter region 107 interlayer insulating film 108 emitter electrode 109 n ⁺ FS layer 110 p ⁺ collector layer 111 collector electrode

Claims (7)

Before the step of forming a plurality of semiconductor elements on a semiconductor substrate,
The outer periphery of the semiconductor substrate is reduced in thickness to form an outer peripheral end, and the outer peripheral end has a thermal expansion coefficient larger than that of the semiconductor substrate and is applied in a heat treatment step in the step of forming the semiconductor element. A method of manufacturing a semiconductor element, comprising depositing a metal having a melting point higher than the highest temperature so as not to protrude from both main surfaces of the semiconductor substrate on which the semiconductor element is formed. A plurality of the semiconductor substrates having the same diameter provided with the outer peripheral end portion are stacked, the outer peripheral end portion is exposed, and is sandwiched between rotating jigs from the main surface direction,
Masking at least a region where the semiconductor element is formed;
Rotate the stacked semiconductor substrate around the direction sandwiched between the rotating jigs,
2. The method of manufacturing a semiconductor element according to claim 1, wherein the metal is deposited on the outer peripheral edge by sputtering. 3. The method of manufacturing a semiconductor element according to claim 2, wherein the sputtering is sequentially performed from each main surface side by inclined sputtering at an angle that does not reach a close contact portion of the plurality of stacked semiconductor substrates. 4. The semiconductor substrate according to claim 2, wherein the plurality of semiconductor substrates are stacked with a buffer film having heat resistance equal to or higher than the temperature of the semiconductor substrate rising during the sputtering. The manufacturing method of the semiconductor element of description. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate has a thickness that does not require a grinding step of reducing the thickness in the step of forming the semiconductor device. The outer peripheral end of the semiconductor substrate is processed into a shape consisting of an inclined portion extending from each of the main surfaces and an end surface perpendicular to the main surfaces, or a shape consisting of a curvature portion extending from each of the main surfaces. 2. The method of manufacturing a semiconductor device according to claim 1, wherein: The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an IGBT.

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