JP5266869B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the breakage of a wafer having an outer peripheral end thicker than a center section and also suppress the breakage and jumping of a chip during dicing by an existing device. <P>SOLUTION: An active zone 2 having a device surface structure is formed at the front surface center section of a semiconductor wafer 1. A protective tape 30 is pasted on the front surface of the active zone 2, and the wafer is sucked on a grinding surface plate 20 with the protective tape 30 facing downward. The rear surface center section 3 of the semiconductor wafer 1 is ground using a wheel 12 to which a first grinding wheel 10 is affixed. The thickness of the rear surface outer peripheral end of the semiconductor wafer 1 is equal to that of the semiconductor wafer 1. The outer peripheral end forms a rib section 4. The rear surface of the semiconductor wafer 1 is ground while leaving the rib section 4. In this case, a first transient zone 5 is formed between the center section 3 and the rib section 4 of the semiconductor wafer 1 by the first inclined surface 11 of the first grinding wheel 10. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

This invention relates to the production how the power semiconductor device and a semiconductor device used in such power converter, relates to the particular preparation how the device is thin thin semiconductor device and a semiconductor device.

Conventionally, in an IGBT (Insulated Gate Bipolar Transistor), a punch-through type and a non-punch-through type are used. First, a conventional punch-through IGBT will be described. Note that in this specification, a semiconductor having n or p means that electrons and holes are majority carriers, respectively. Further, “ ⁺ ” or “ ⁻ ” attached to n or p, such as n ⁺ or n ^−, is relatively higher or lower than the impurity concentration of the semiconductor to which they are not attached. Represents that.

FIG. 15 is a cross-sectional view showing the structure of a conventional punch-through IGBT. The punch-through IGBT is intended to reduce the on-voltage when it is on. In the punch-through IGBT, carriers are injected from the collector side to fill the IGBT with a high concentration of carriers. Furthermore, by providing the n ⁺ buffer layer 102 that supports a high voltage, a thin n ⁻ drift layer 103 is realized, and a low on-voltage is realized. Lifetime control is also used to achieve fast turn-off time. The reason is to quickly erase the carrier filled in the IGBT. Thereby, carrier transport efficiency is reduced and a low switching loss is obtained. However, even in the normal on state, there is a problem that the on voltage increases due to the effect of reducing the carrier transport efficiency.

As shown in FIG. 15, in the surface structure formed on the front surface side of the wafer, for example, a p base region 104 is provided in a part of the surface layer of the n ⁻ drift layer 103. An n ⁺ emitter region 105 is provided in a part of the surface layer of the p base region 104. A trench 110 that penetrates the n ⁺ emitter region 105 and reaches the n ⁻ drift layer 103 is provided. A gate electrode 107 is provided inside the trench 110 via a gate oxide film 106. An insulating film 120 is provided on the gate oxide film 106 and the gate electrode 107, and the gate electrode 107 and the emitter electrode 108 are separated by the insulating film 120. The emitter electrode 108 is provided in contact with the p base region 104 and the n ⁺ emitter region 105.

Further, as shown in FIG. 15, in the punch-through type IGBT, a high impurity concentration n-type epitaxial layer is grown on a high impurity concentration p-type silicon substrate to be the p ⁺ collector layer 101 to form an n ⁺ buffer layer. 102 is formed. Then, on the n ⁺ buffer layer 102, is grown n-type epitaxial layer of low impurity concentration, n ^- to form the drift layer 103. The punch-through IGBT is manufactured using the wafer manufactured by the epitaxial growth method as described above.

FIG. 16 is a cross-sectional view showing the structure of a conventional non-punch through type IGBT. The non-punch-through IGBT is based on a design philosophy opposite to the punch-through IGBT that suppresses carrier injection from the collector side and lowers the injection efficiency to increase the transport efficiency. That is, the carrier injection efficiency is controlled by controlling the impurity concentration of the collector (p ⁺ layer) without controlling the lifetime. The non-punch-through IGBT is manufactured using a low-cost wafer such as an n-type FZ (Floating Zone) wafer.

As shown in FIG. 16, in the non-punch through IGBT, after forming a surface structure on the front surface side of the n-type FZ wafer, the n ⁻ drift layer 103 is thinned by grinding from the back surface of the wafer. Next, for example, boron ions are irradiated from the back side of the n-type FZ wafer. A part of the irradiated boron ions is activated, for example, by low temperature annealing of 400 degrees or less. Thereby, the p ⁺ collector layer 101 is formed. Then, collector electrode 109 is formed in contact with p ⁺ collector layer 101.

  In recent years, high performance and low cost have become important issues in IGBTs. For this reason, non-punch-through IGBTs, which can reduce switching loss and improve high-speed switching characteristics, and can reduce costs, are mainly used. In order to further improve the characteristics of the IGBT, a thin IGBT structure using a field stop (FS) layer is used.

FIG. 17 is a cross-sectional view showing the structure of a field stop (FS) IGBT using an FZ wafer. In the FS type IGBT, the n ⁺ buffer layer 102 is used as the field stop layer 102. Similar to the non-punch-through type IGBT shown in FIG. 16, while providing the effects of low carrier injection and high transport efficiency, the ON layer and turn-off loss characteristics are further improved by making the base layer thinner than the non-punch-through structure. It has been improved. As shown in FIG. 17, in the FS type IGBT, after the surface structure of the device is formed on the front surface side of the wafer, the back surface of the n type FZ wafer is shaved and thinned. Then, phosphorus ions are irradiated from the back surface, and then boron ions are irradiated. Further, annealing is performed by irradiating the back surface with laser light while cooling the front surface of the wafer. As a result, the n ⁺ buffer layer 102 and the p ⁺ collector layer 101 are formed by activating phosphorus atoms and boron atoms.

Here, in order to improve the characteristics of the FS-type IGBT as shown in FIG. 17, the n ⁻ drift layer 103 may be thinned according to the breakdown voltage. Specifically, for example, when an IGBT having a breakdown voltage of 1200 V is formed, the desired performance can be sufficiently obtained by setting the thickness of the n ⁻ drift layer 103 to about 120 μm to 130 μm. Further, when forming an IGBT having a breakdown voltage of 600 V, the thickness of the n ⁻ drift layer 103 may be set to about 60 μm to 70 μm.

As described above, when the thickness of the wafer serving as the n ⁻ drift layer 103 is reduced, the warpage of the wafer is increased and the rigidity is remarkably reduced. Therefore, there is a problem that the strength of the wafer cannot be maintained when the wafer is held by, for example, an arm or a jig in the subsequent manufacturing process or transfer process.

  Therefore, a rib wafer in which a rib structure is provided on the back side of the wafer has been proposed. In the rib wafer, the outer peripheral end portion is thicker than the central portion on the back side of the wafer. By using a rib wafer, the warpage of the wafer is greatly reduced, and when the wafer is handled in the transfer process, the strength of the wafer is greatly improved, and cracks and chips on the wafer can be reduced.

  As a method for producing such a rib wafer, a thinning device having a polishing portion having a diameter smaller than the diameter of the wafer is used to grind and thin only the central portion from the back surface side of the wafer, leaving the outer peripheral end portion. Thus, a method of forming a rib portion has been proposed (see, for example, Patent Document 1 below).

  In addition, the center part of the semiconductor wafer is made thinner than the outer peripheral edge part using a grindstone, the rib part is formed, and then the chamfering process is performed on the inner peripheral end part of the surface of the rib part by adjusting the position of the grindstone. A method of forming a curved surface has been proposed (for example, see Patent Document 2 below). According to this method, stress is not concentrated on the inner peripheral end portion of the surface of the rib portion of the semiconductor wafer, and damage from the inner peripheral end portion of the surface of the rib portion can be prevented.

  However, in the technique of Patent Document 1 or 2, by performing grinding, a processing damage layer having a depth similar to the grain size of the grindstone of the grindstone used for grinding is provided on the grinding surface on the back side of the wafer. And the wafer thickness varies. Here, when the wafer is thinned, the particle size of the abrasive grains of the grindstone becomes a size that cannot be ignored with respect to the thickness of the wafer. Therefore, there is a problem that the characteristics of the device deteriorate due to damage caused by the processing damage layer. Further, for example, when an electrode is formed on the back side of the wafer, there is a problem that the contact resistance between the wafer and the electrode increases because there is a processing damage layer on the surface on the back side of the wafer. Further, there is a problem that the wafer is easily broken by a crack in the processing damage layer.

  As a method for solving such a problem, after grinding the back surface side of the wafer to a predetermined thickness that defines the thickness of the rib portion, leaving only the center portion on the back surface side of the wafer, leaving the outer peripheral edge. An etching method has been proposed (see, for example, Patent Document 3 below). According to this method, the processing damage layer by the grindstone on the grinding surface can be removed.

JP-A-5-121384 JP 2007-103582 A JP 2007-208074 A

  However, in the above-described technique, when a dicing tape is attached to the back side of the rib wafer in the dicing process, there is a steep step between the central portion of the wafer and the rib portion, so the rib wafer and the dicing tape are around the step. There will be a gap between them. If there is a gap between the rib wafer and the dicing tape, a chip formed at a position corresponding to the gap cannot be fixed to the stage on which the rib wafer is placed via the dicing tape. For this reason, when performing dicing or subsequent cleaning, there arises a problem such as chip fly in which chips formed on a portion where the dicing tape is not attached are scattered.

  Therefore, dicing on the back side of the wafer by flattening the back side of the wafer by cutting off the rib part before dicing or grinding the rib part to eliminate the step between the wafer outer edge and the center of the wafer. A method of sticking the tape so that there is no gap is conceivable.

  However, it is necessary to introduce a new device for flattening the wafer, which increases the manufacturing cost of the semiconductor device. Further, since a new process is added during the manufacturing process, there is a problem that the production efficiency of the device is lowered.

  Further, in a normal semiconductor device manufacturing method, only the central portion of the wafer is thinned to form a rib portion, and then a photolithography process, a thermal diffusion process, a film forming process, an etching process, and the like are performed. Sometimes. When performing these steps, the step between the central portion of the wafer and the rib portion must be eliminated. For example, the step of the wafer has a convex portion having the same shape as the concave portion of the central portion of the wafer. Corresponding special transfer device and stage are required. For this reason, there exists a problem that production cost will rise.

  Further, when the rising angle from the central portion to the rib portion is steep, that is, when the side surface of the rib portion is substantially perpendicular to the central portion, the thickness change from the central portion toward the rib portion is steep. It is. For this reason, in processes involving heating such as a thermal diffusion process and a film forming process, the difference in volume change per unit area due to thermal expansion between the central part and the rib part is greatly different, and near the boundary between the central part and the rib part. There is a problem that the wafer is destroyed.

In order to eliminate the above-described problems caused by the prior art, the present invention suppresses breakage due to thermal expansion of a wafer whose outer peripheral end is thicker than the central portion, and suppresses chip breakage and chip fly in dicing using an existing apparatus. and to provide a manufacturing how a semiconductor device and a semiconductor device capable.

To solve the above problems and achieve an object, a semiconductor device according to this invention, in a semiconductor wafer provided with thicker ribs than the central portion to the outer edge, between the central portion and the rib portion In between, the thickness is gradually reduced from the thickness of the rib portion to the thickness of the intermediate region, and the intermediate region having a plane that is thinner than the rib portion and thicker than the central portion and parallel to the central portion. A first transition region that decreases, and a second transition region that gradually decreases in thickness from the thickness of the intermediate region to the thickness of the central portion, the first transition region and the second transition region Each transition region has an inclined surface whose rising angle from the intermediate region and the central portion is 15 ° or more and 45 ° or less.

A method of manufacturing a semiconductor device according to this invention, a surface structure forming step of forming a surface structure of the element in the center portion of the front surface side of the semiconductor wafer, the lower surface of the grinding surface is a back surface of the semiconductor wafer A rib portion is formed along the outer peripheral edge of the semiconductor wafer by grinding the central portion on the back surface side of the semiconductor wafer with a first grindstone that is parallel and has an inclined surface from the lower surface toward the side surface. And a first back surface grinding step for forming a first transition region that gradually decreases in thickness from the thickness of the rib portion, and the lower surface of the grinding surface is parallel to the central portion on the back surface side of the semiconductor wafer, A region surrounded by the first transition region on the back surface side of the semiconductor wafer is further ground by a second grindstone having an inclined surface from the lower surface toward the side surface, and the thickness of the rib portion is thicker than the thickness of the central portion. Thinner than that A second back grinding step of forming an intermediate region parallel to the central portion and forming a second transition region in which the thickness gradually decreases from the thickness of the intermediate region to the thickness of the central portion; , Including.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the in the first back grinding step, by grinding by the inclined surface of the first grinding wheel, and the said rib portion intermediate region In the meantime, a first inclined surface having an angle of rising from the intermediate region of 15 ° to 45 ° is formed, and the region having the first inclined surface becomes the first transition region, and in the second back grinding step Forming a second inclined surface having a rising angle from the central portion of 15 ° to 45 ° between the central portion and the intermediate region by grinding with the inclined surface of the second grindstone. The region having the second inclined surface is the second transition region.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the in the second back surface grinding step, the as the width of the intermediate region is 0.2mm or more 3mm or less, the first back grinding Grinding is performed with a diameter smaller than that of the process.

A method of manufacturing a semiconductor device according to this invention is the invention described above, in the second back surface grinding step, and carrying out fine grinding at a slower rate than the first rear surface grinding step.

A method of manufacturing a semiconductor device according to this invention is the invention described above, after the second back surface grinding step, the back surface side of the front surface of the semiconductor wafer, and characterized in that it comprises an etching step of etching by mixed acid To do.

In the above-described invention, for example, a mixture of nitric acid, hydrofluoric acid, sulfuric acid, and phosphoric acid may be used as the mixed acid. The weight ratio of nitric acid: hydrofluoric acid: sulfuric acid: phosphoric acid: water may be selected in the range of 20-40: 3-10: 10-30: 5-15: balance.

According to inventions described above, in Ribuweha formed of thicker ribs than the central portion to the outer edge, between the central portion and the rib portion, gradually from the thickness of the rib portions of the central portion to the thickness A transition region with a reduced thickness is formed. For this reason, when the rib wafer is attracted to a normal flat stage during dicing, the vicinity of the transition region is deformed and the warpage of the rib wafer is corrected. As a result, the entire back surface of the area where the chip is formed in the central portion of the rib wafer is attracted to the flat stage. In addition, since the thickness gradually changes in the transition region, for example, in the process of applying heat, the difference in volume change due to thermal expansion does not become steep, so that the rib wafer can be prevented from being destroyed.

Further, according to the above-described invention, the grinding surface having the inclined surface gradually decreases in thickness from the thickness of the rib portion to the thickness of the central portion between the central portion and the rib portion of the rib wafer. An inclined surface can be formed.

In the above-described invention, when the rib portion is formed by grinding the central portion while leaving the outer peripheral end portion of the semiconductor wafer, the thickness between the rib portion and the center is increased between the central portion and the rib portion. A transition region that gradually decreases in thickness to the thickness of the portion can be formed. For this reason, when the rib wafer is attracted to a normal flat stage during dicing, the vicinity of the transition region is deformed and the warpage of the rib wafer is corrected. As a result, the entire back surface of the area where the chip is formed in the central portion of the rib wafer is attracted to the flat stage. For this reason, dicing can be performed in the same manner as a normal flat wafer. In addition, since the thickness gradually changes in the transition region, for example, in the process of applying heat, the difference in volume change due to thermal expansion does not become steep, so that the rib wafer can be prevented from being destroyed.

According to the manufacturing how a semiconductor device and a semiconductor device according to the present invention, the outer peripheral edge portion is suppressed breakage due to thermal expansion of the thicker wafer than the center portion, and chip fly damage or chip in the dicing with existing equipment There is an effect that it can be suppressed.

With reference to the accompanying drawings, illustrating a preferred embodiment of the manufacturing how a semiconductor device and a semiconductor device according to the present invention in detail. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a diagram illustrating the structure of the semiconductor device according to the first embodiment. In FIG. 1, the upper figure is a plan view showing the structure of the semiconductor device according to the first embodiment, and the lower figure is a sectional view showing a sectional structure taken along the cutting line AA ′ in the upper figure. . As shown in FIG. 1, in the semiconductor device according to the first embodiment, the thickness of the rib portion 4 is gradually increased between the central portion 3 and the rib portion 4 of the semiconductor wafer 1 such as a silicon wafer. A first transition region 5 in which the thickness transitions to the thickness of the central portion 3 is formed. In the first transition region 5, for example, an inclined surface that rises at an angle θ <b> 1 from the central portion 3 toward the surface of the rib portion 4 is formed.

  Here, the rising angle θ1 from the central portion 3 of the inclined surface is preferably 15 ° or more and 45 ° or less, for example. The reason is that when the rising angle θ1 is less than 15 °, the width of the first transition region 5 in the semiconductor wafer 1 is widened, and the area of the central portion 3 serving as an element formation region is small. This is because the number of chips produced from the wafer 1 is reduced. Further, when the rising angle is larger than 45 °, the rigidity of silicon in the first transition region 5 is strong, and the first transition region 5 is sufficiently deformed when the back surface side of the semiconductor wafer 1 is attracted to a flat suction device. do not do. For this reason, the warp of the semiconductor wafer 1 is not sufficiently corrected, and for example, a region near the boundary between the central portion 3 and the first transition region 5 is not adsorbed by the adsorbing device, so that processing such as dicing cannot be performed. is there. Furthermore, if the area near the boundary between the central portion 3 and the first transition area 5 is forcibly adsorbed by the adsorption device, the semiconductor wafer 1 is broken.

  Next, the structure of the semiconductor device manufacturing apparatus according to the first embodiment will be described. FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor device manufacturing apparatus according to the first embodiment. In FIG. 2, the upper right diagram is a front view of the semiconductor device manufacturing apparatus according to the first embodiment, and the upper left diagram is a side view of the semiconductor device manufacturing apparatus according to the first embodiment. FIG. 3 is a bottom view of the semiconductor device manufacturing apparatus according to the first exemplary embodiment; As shown in FIG. 2, the semiconductor device manufacturing apparatus according to the first embodiment is a grinding wheel used to grind only the central portion while manufacturing the rib wafer, leaving the outer peripheral end portion of the semiconductor wafer. It is.

  The first grindstone 10 according to the first embodiment has a height of (a + b), a width of (d + e), a corner of one side of the lower surface of the rectangular parallelepiped having a depth of c, and a first inclined surface. 11 is provided. The upper surface side of the 1st grindstone 10 is a side attached to the wheel with which a grinding device is provided.

  When the first grindstone 10 is attached to the wheel, the width of the lower surface of the first grindstone 10 that contacts the semiconductor wafer horizontally (the width of the lower surface) is e, and this region is in contact with the back side of the semiconductor wafer. . The width e of the lower surface is preferably at least 1 mm. Further, the first inclined surface 11 rises at an angle θ2 from a region that is in horizontal contact with the semiconductor wafer. The first inclined surface 11 is in contact with the vicinity of the boundary between the central portion and the rib portion of the semiconductor wafer, so that a transition region is formed in the semiconductor wafer. Therefore, in the semiconductor wafer, the rising angle θ1 of the transition region rising from the central portion is θ1 = 180 ° −θ2. Further, the first inclined surface 11 is not formed on the side surface of the first grindstone 10 in the region from the top surface to the height a, and is perpendicular to the central portion on the back surface side of the semiconductor wafer.

  Therefore, when the semiconductor wafer is ground by the first grindstone 10, the inclined surface having an inclination width of d or less, an inclination height of b or less, and a rising angle of θ1 is a central portion and a rib portion on the back surface side of the semiconductor wafer. Formed between. The region of the inclined surface becomes a transition region. Further, the rising angle θ2 in the first grindstone 10 is preferably, for example, 135 ° or more and 165 ° or less. The grindstone is, for example, a diamond grindstone using # 3000 vitrified as a binder.

  Below, the 1st grindstone 10 demonstrates an example attached to the wheel with which a grinding apparatus is provided. FIG. 3 is a diagram illustrating an example in which the semiconductor device manufacturing apparatus according to the first embodiment is attached to a wheel included in the grinding apparatus. As shown in FIG. 3, a plurality of first grindstones 10 are attached along the outer periphery of a wheel 12 in which the shape of the attachment portion to which the first grindstone 10 is attached has a circular shape. At this time, the first inclined surface 11 of the first grindstone 10 is arranged on the outer peripheral direction side of the wheel 12. Also, let R be the diameter of the grinding surface to be ground in the first grindstone 10 attached to the wheel 12.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 4 to 6 are sectional views sequentially showing the method for manufacturing the semiconductor device according to the first embodiment. First, as shown in FIG. 4, the surface structure of the device is formed in the central portion 3 on the front surface side of the semiconductor wafer 1. The region where the surface structure of this device is formed is the active region 2.

  Next, as shown in FIG. 5, a protective tape 30 is attached to the surface of the active region 2 of the semiconductor wafer 1. Then, the semiconductor wafer 1 is attracted to the grinding surface plate 20 with the protective tape 30 facing down. By affixing the protective tape 30 to the surface of the active region 2 of the semiconductor wafer 1, the active region 2 can be protected from impact and vibration during grinding when the back surface side of the semiconductor wafer 1 is ground. Thereby, the characteristic of the device produced using this semiconductor wafer 1 can be maintained. In addition, when the influence of the impact and vibration at the time of grinding is small, it is not necessary to stick the protective tape 30.

  Next, the central portion 3 on the back surface side of the semiconductor wafer 1 is ground using the wheel 12 to which the first grindstone 10 is attached. For example, a motor (not shown) is connected to the wheel 12, and the wheel 12 is rotated at a speed of, for example, about 4500 rpm by driving the motor, and the first grindstone 10 is also rotated. Further, grinding may be performed while the grinding surface plate 20 on which the semiconductor wafer 1 is adsorbed is rotated at a speed of about 300 rpm, for example. The grinding speed is, for example, about 0.7 μm per second.

  At this time, the outer peripheral end portion on the back surface side of the semiconductor wafer 1 is left with the original thickness of the semiconductor wafer 1. This outer peripheral end portion becomes the rib portion 4. Then, the back surface side of the semiconductor wafer 1 is ground so as to leave the rib portion 4. Further, at this time, the first transition region 5 is formed between the central portion 3 and the rib portion 4 of the semiconductor wafer 1 by the first inclined surface 11 of the first grindstone 10.

  Here, when the semiconductor wafer 1 is ground using a grindstone, the region where the grindstone is in contact with the semiconductor wafer 1, that is, the central portion 3 on the back side of the semiconductor wafer 1, the first transition region 5, and the side walls of the rib portion 4, A processing damage layer is generated. The thickness of the processing damage layer is almost the same as the average particle diameter of the abrasive grains of the grindstone used for grinding.

  Further, grinding is performed so that the thickness of the central portion 3 is equal to or greater than a thickness required for performing a manufacturing process on at least the back surface side (hereinafter referred to as a target thickness) plus an etching allowance. Here, the etching allowance is a depth at which etching is performed in a later etching step, and is set to be equal to or greater than the depth of the processing damage layer. Specifically, when the average grain size of the abrasive grains of the first grindstone 10 is about 5 μm, the etching allowance is preferably 20 μm or more. The upper limit of the depth at which etching is performed is not particularly set, but if it exceeds 100 μm, the error in the etching depth cannot be ignored with respect to the thickness of the central portion 3 of the semiconductor wafer 1. This is not preferable because the thickness of the film may not be uniform. Next, when the protective tape 30 is attached to the front surface side of the semiconductor wafer 1, the protective tape 30 is peeled off.

  Next, as shown in FIG. 6, the entire back surface of the semiconductor wafer 1 is etched using, for example, a mixed acid. That is, the central portion 3 on the back surface side of the semiconductor wafer 1, the first transition region 5, and the rib portion 4 are etched simultaneously. In the etching, the type of the etchant 23 is not particularly limited. For example, at room temperature, a mixed acid of nitric acid: hydrofluoric acid: sulfuric acid: phosphoric acid: water at 30: 5: 20: 15: 30 is used as a nozzle. 22 is dropped onto the semiconductor wafer 1 at a flow rate of 1 liter per minute, for example. Here, the mixed acid may be, for example, such that the weight percentage of nitric acid: hydrofluoric acid: sulfuric acid: phosphoric acid: water ranges from 20 to 40: 3 to 10:10 to 30: 5 to 15: balance. At this time, the semiconductor wafer 1 is placed on the spin chuck 21 with its front side down, and rotated at a speed of, for example, 700 rpm, and the etching solution 23 is dropped from the nozzle 22 onto the back side of the semiconductor wafer 1. May be.

  As another etching method, after forming a protective film on the surface of the active region 2, the semiconductor wafer 1 may be immersed in a chemical bath containing a mixed acid for a predetermined time. In this case, the surface where the protective film is not formed is uniformly etched.

  In this way, the processing damage layer on the back surface side of the semiconductor wafer 1 is removed. Furthermore, the thickness of the central portion 3 of the semiconductor wafer 1 may be adjusted to the target thickness by this etching. In this case, for example, by monitoring the thickness of the central portion 3 of the semiconductor wafer 1 with a thickness sensor using infrared rays, the etching depth is adjusted, and the thickness of the central portion 3 of the semiconductor wafer 1 is set to the target thickness. It may be. Next, the substrate may be cleaned with a cleaning liquid such as pure water, and may be dried such as spin drying.

  Next, dicing of the semiconductor wafer 1 is performed by a normal method using a flat suction device. For example, using a pressure-sensitive dicing tape, the semiconductor wafer 1 is attached to a ring frame and is adsorbed by a flat adsorbing device. Then, blade dicing is performed by a dicing blade from the front surface side of the semiconductor wafer 1. In dicing, for example, a nickel electrolytic casting blade of diamond grindstone # 3000 is used as a dicing blade. For example, the feeding speed is set to 30 mm per second and the rotation of the spindle is set to 30000 rpm.

  According to the first embodiment, when the back surface side of the semiconductor wafer 1 is placed on a flat suction device and suction is performed, the vicinity of the first transition region 5 in the semiconductor wafer 1 is deformed, and the warp of the semiconductor wafer 1 is performed. Is sufficiently corrected, the entire back side of the active region 2 is adsorbed by the adsorption device. In this state, by performing dicing from the front surface side of the semiconductor wafer 1, it is possible to prevent chip breakage and chip jumping.

  Further, since the first transition region 5 is formed between the central portion 3 and the rib portion 4, the rise from the central portion 3 to the rib portion 4 is not steep. That is, the thickness gradually increases from the central portion 3 to the rib portion 4. Therefore, since the volume change per unit area due to the thermal expansion of the first transition region 5 gradually increases from the central part 3 side to the rib part 4 side, it is possible to prevent the wafer from being broken due to a steep volume change difference. Can do.

(Embodiment 2)
Next, a semiconductor device according to the second embodiment will be described. FIG. 7 is a diagram for explaining the structure of the semiconductor device according to the second embodiment. In FIG. 7, the upper diagram is a plan view showing the structure of the semiconductor device according to the second embodiment, and the lower diagram is a sectional view showing a sectional structure along the cutting line BB ′ in the upper diagram. . As shown in FIG. 7, in the semiconductor device according to the second embodiment, for example, an intermediate region 7 parallel to the central portion 3 between the central portion 3 and the rib portion 4 of the semiconductor wafer 1 such as a silicon wafer. Is formed. The middle region 7 is thicker than the central portion 3 and thinner than the rib portion 4. Further, a second transition region 6 that gradually transitions from the thickness of the rib portion 4 to the thickness of the intermediate region 7, and a third transition region 8 that gradually transitions from the thickness of the intermediate region 7 to the thickness of the central portion 3. Are formed.

  In the second transition region 6, an inclined surface that rises at an angle from the surface of the intermediate region 7 toward the surface of the rib portion 4 is formed. The third transition region 8 is formed with an inclined surface that rises at an angle from the central portion 3 toward the surface of the intermediate region 7. In the second transition region 6, the rising angle θ3 from the intermediate region 7 of the inclined surface is preferably, for example, 15 ° or more and 45 ° or less. In the third transition region 8, the rising angle θ4 from the central portion 3 of the inclined surface is preferably 15 ° or more and 45 ° or less, for example.

  Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. 8 to 10 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the second embodiment. In the method of manufacturing a semiconductor device according to the second embodiment, the transition region between the central portion and the rib portion is formed in two stages using the second grindstone and the third grindstone. The second grindstone and the third grindstone are grindstones having the same conditions as the first grindstone according to the first embodiment. The first grindstone, the second grindstone, and the third grindstone may be the same or different within a predetermined range.

  First, as shown in FIG. 8, after the active region 2 is formed in the central portion 3 on the front surface side of the semiconductor wafer, the protective tape is applied to the surface of the active region 2 of the semiconductor wafer 1 as in the first embodiment. Affix 30. Then, the semiconductor wafer 1 is attracted to the grinding surface plate 20 with the protective tape 30 facing down. In addition, when the influence of the impact and vibration at the time of grinding is small, it is not necessary to stick the protective tape 30.

  Next, first grinding is performed on the central portion 3 on the back surface side of the semiconductor wafer 1 using the wheel 15 to which the second grindstone 13 is attached. For example, a motor (not shown) is connected to the wheel 15, and the wheel 15 is rotated at a speed of, for example, about 4500 rpm by the driving of the motor, and the second grindstone 13 is also rotated. Alternatively, the grinding surface plate 20 on which the semiconductor wafer 1 is adsorbed may be ground while being rotated at a speed of about 300 rpm, for example. The grinding speed is, for example, about 3 μm per second.

  At this time, the outer peripheral end portion on the back surface side of the semiconductor wafer 1 is left with the original thickness of the semiconductor wafer 1. This outer peripheral end portion later becomes the rib portion 4. Then, the back surface side of the semiconductor wafer 1 is ground so as to leave the rib portion 4. At this time, the rising angle of the second grindstone 13 from the central portion 3 in this state is θ3 (for example, 15 ° to 45 °) due to the inclined surface having a rising angle of θ5 (for example, 135 ° to 165 °). An inclined surface that is less than or equal to ° is formed. That is, the second transition region 6 is formed between the central portion 3 and the rib portion 4 of the semiconductor wafer 1 by the inclined surface 14 of the second grindstone 13.

  Further, in this state, the thickness of the central portion 3 is at least a thickness for performing a manufacturing process on the back surface side (hereinafter referred to as a target thickness), and a thickness ground with a third grindstone described later and etching removal. Grind to a thickness greater than the total thickness. Here, the etching allowance is preferably 20 μm or more when the average grain size of the abrasive grains of the third grindstone described later is about 5 μm.

  Next, second grinding is performed on the grinding surface ground by the second grindstone 13 using the wheel 18 to which the third grindstone 16 is attached. In the second grinding, a region having a diameter smaller than the diameter of the ground surface by the first grinding is ground. The region remaining due to the difference between the diameter ground by the first grinding and the diameter ground by the second grinding becomes the intermediate region 7. For example, a motor (not shown) is connected to the wheel 18, and the wheel 18 is rotated at a speed of, for example, about 5000 rpm by driving the motor, and the third grindstone 16 is also rotated. Further, the grinding may be performed while rotating the grinding surface plate 20 on which the semiconductor wafer 1 is adsorbed, for example, at a speed of about 200 rpm. The grinding speed is, for example, about 0.7 μm per second.

  At this time, the rising angle of the third grindstone 16 is θ6 (for example, 135 ° to 165 °), and the rising angle from the central portion 3 is θ4 (for example, 15 ° to 45 °). A surface is formed. That is, the third transition region 8 is formed between the central portion 3 of the semiconductor wafer 1 and the intermediate region 7 by the inclined surface 17 of the third grindstone 16.

  Here, the difference between the diameter ground by the second grindstone 13 and the diameter ground by the third grindstone 16, that is, the width of the intermediate region 7 is preferably 0.2 mm or more and 3 mm or less. The reason for this is that if the difference in diameter to be ground is smaller than 0.2 mm, the position accuracy of the grinding apparatus including the wheels 15 and 18 to which the second grindstone 13 or the third grindstone 16 is fixed is insufficient, and the third grindstone 16 This is because the side surface reaches the second transition region 6 formed by the second grindstone 13 and the intermediate region 7 is not formed. Further, if the difference in diameter to be ground is larger than 3 mm, the area of the intermediate region 7 increases and the area of the central portion 3 decreases. Accordingly, the active region for forming an element decreases accordingly, and a chip that can be taken from one wafer This is because the number decreases.

  Next, when the protective tape 30 is affixed to the front surface side of the semiconductor wafer 1, the protective tape 30 is peeled off. Next, as shown in FIG. 10, the processing damage layer is etched as in the first embodiment. Then, dicing is performed after washing and drying.

  According to the second embodiment, the same effect as in the first embodiment can be obtained. In addition, when performing grinding in two stages, rough grinding is performed at a high speed in the first grinding, and even if a large processing damage layer is generated on the grinding surface, fine grinding is performed in the second grinding. The damage of the processing damage layer can be reduced to such an extent that it can be removed by subsequent etching. For this reason, the throughput at the time of grinding the back surface side of a semiconductor wafer improves.

Example 1
In accordance with the first embodiment described above, IGBTs were respectively produced on 100 wafers. The wafer used was silicon and the diameter was 8 inches. Further, when grinding the back side of the wafer, a protective tape was attached to the front side of all 100 wafers. Further, in grinding, 25 samples were prepared for each of the conditions of the grindstone used.

  FIG. 11 is a diagram illustrating conditions of the grindstone used in the first embodiment. As shown in FIG. 11, in Example 1, grinding was performed using grindstones A to D having different shapes. Each of the grindstones A to C has a lower surface width e of 3 mm, a depth c of 10 mm, a height a perpendicular to the upper surface of 4 mm, an inclined height b of 1 mm, and an inclined width d of 1 mm, 1. 7 mm, 3.7 mm, and rising angle θ2 are 135 °, 150 °, and 165 ° (refer to FIG. 2 for a, b, c, d, e, and θ2). Further, the grindstone D is a conventional rectangular parallelepiped grindstone (a grindstone without an inclined surface). The width e of the lower surface is 3 mm, the depth c is 10 mm, and the height (that is, the height of the entire grindstone) a is perpendicular to the upper surface. 5 mm. In each case, the distance between the grindstones when attached to the wheel is about 1 mm, and the diameter R of the grinding surface by the plurality of grindstones attached to the wheel is 196 mm. Then, the wheel to which the grindstone was attached was rotated at a speed of 4500 rpm, the grinding platen on which the wafer was adsorbed was rotated at a speed of 300 rpm, and grinding was performed at a grinding speed of 0.7 μm per minute.

  Then, while rotating the wafer at a speed of 700 rpm, a mixed acid of 30: 5: 20: 15: 30, for example, nitric acid: hydrofluoric acid: sulfuric acid: phosphoric acid: water by weight is 1 liter per minute on the wafer. Etching was carried out by dropping at a flow rate of. Further, it was washed with pure water and spin-dried.

  Next, the wafer was attached to a ring frame for dicing using a pressure-sensitive dicing tape by a normal method and adsorbed on a flat adsorption device. Then, dicing was performed from the front surface side of the wafer by rotating the spindle at a speed of 30000 rpm at a feeding speed of 30 mm per second using a dicing blade of a nickel electrolytic casting blade of diamond grindstone # 3000.

  Next, after dicing, it was examined whether or not chip breakage or chip jump occurred on each wafer. The results are summarized in FIG. 12 for each condition of the grindstone used for grinding. FIG. 12 is a diagram illustrating the number of wafers on which chip breakage or chip fly occurs when dicing is performed on the semiconductor device according to the first embodiment.

  According to the first embodiment, as shown in FIG. 12, in the wafers ground by the grindstone A to the grindstone C, the number of wafers in which chip breakage or chip jump occurs is reduced to 0 or 1 out of 25. I was able to. However, in the wafers ground with the conventional grindstone D, chip breakage or chip jump occurred in 25 out of 25 wafers. Therefore, when the dicing is performed by setting the rising angle θ2 of the grindstone to 135 ° or more and 165 ° or less, that is, setting the rising angle θ1 from the center of the transition region of the wafer to 15 ° or more and 45 ° or less. It was found that chip breakage and chip jumping can be prevented.

(Example 2)
Next, according to the second embodiment described above, IGBTs were fabricated on 400 wafers. Using the grindstone A to grindstone D shown in Example 1, 100 pieces of each were subjected to the first grinding. In the first grinding, the wheel to which the grindstone was attached was rotated at a speed of 4500 rpm, the grinding platen on which the wafer was adsorbed was rotated at a speed of 300 rpm, and rough grinding was performed at a grinding speed of 3 μm / min. .

  Then, after the first grinding, each of the wafers ground by 100 for each grindstone was further subjected to the second grinding using the grindstones E to H, and 25 samples each were produced. FIG. 13 is a diagram illustrating conditions of a grindstone used in the second grinding in the second embodiment. The shapes and dimensions of the grindstones E to H are the same as those of the grindstones A to D, respectively, but when mounted on the wheel, the diameter R of the grinding surface is smaller than the grindstones A to D (196 mm), and is mounted to 194 mm. It was. In the second grinding, the wheel to which the grindstone is attached is rotated at a speed of 5000 rpm, the grinding platen on which the wafer is adsorbed is rotated at a speed of 200 rpm, and fine grinding is performed at a grinding speed of 0.7 μm per minute. went. Since other processes are the same as those in the first embodiment, description thereof is omitted.

  FIG. 14 is a diagram illustrating the number of wafers on which chip breakage or chip fly occurs when dicing is performed on the semiconductor device according to the second embodiment. According to the second embodiment, as shown in FIG. 14, dicing is performed on a wafer that has been ground using a conventional grindstone D or grindstone H for at least one of the first grinding and the second grinding. At that time, 25 of 25 wafers, chip breakage or chip jumping occurred on all the wafers. On the other hand, in a wafer that has been ground by combining the grindstones A to C and the grindstones E to G, the number of wafers in which chip breakage or chip jump has occurred is suppressed to 0, 1 or 2 out of 25 sheets. I was able to.

As described above, manufacturing how a semiconductor device and a semiconductor device according to the present invention is useful for producing thin semiconductor device and a semiconductor device of the device thickness, in particular, the power to be used, for example, the power converter It is suitable for manufacturing a semiconductor device and the semiconductor device.

1 is a diagram illustrating a structure of a semiconductor device according to a first embodiment; 1 is a cross-sectional view showing a structure of a semiconductor device manufacturing apparatus according to a first embodiment; It is a figure which shows an example with which the manufacturing apparatus of the semiconductor device concerning Embodiment 1 was attached to the wheel with which a grinding device is provided. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a structure of a semiconductor device according to a second embodiment; FIG. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; It is a figure which shows the conditions of the grindstone used in Example 1. FIG. FIG. 3 is a diagram showing the number of wafers on which chip breakage or chip jumping occurs when dicing is performed on the semiconductor device according to Example 1; It is a figure which shows the conditions of the grindstone used in the 2nd grinding in Example 2. FIG. FIG. 10 is a diagram showing the number of wafers on which chip breakage or chip fly occurs when dicing is performed on a semiconductor device according to Example 2; It is sectional drawing shown about the structure of the conventional punch through type IGBT. It is sectional drawing shown about the structure of the conventional non-punch through type IGBT. It is sectional drawing shown about the structure of a field stop (FS) type IGBT using an FZ wafer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Active area | region 3 Center part 4 Rib part 5 1st transition area 10 1st whetstone 11 1st inclined surface 12 Wheel 20 Grinding surface plate 30 Protective tape

Claims (6)

In the semiconductor wafer in which the rib part thicker than the center part is provided at the outer peripheral end part,
Between the rib part and the central part, an intermediate region having a plane that is thinner than the rib part and thicker than the central part and parallel to the central part,
A first transition region in which the thickness gradually decreases from the thickness of the rib portion to the thickness of the intermediate region;
A second transition region in which the thickness gradually decreases from the thickness of the intermediate region to the thickness of the central portion;
With
The semiconductor device according to claim 1, wherein the first transition region and the second transition region have inclined surfaces whose rising angles from the intermediate region and the central portion are 15 ° to 45 °, respectively. A surface structure forming step of forming the surface structure of the element in the center of the front side of the semiconductor wafer;
The semiconductor wafer is ground by grinding the central portion on the back surface side of the semiconductor wafer with a first grindstone having a lower surface of the grinding surface parallel to the back surface of the semiconductor wafer and having an inclined surface from the lower surface toward the side surface. Forming a rib portion along the outer peripheral edge of the first and back grinding step of forming a first transition region that gradually decreases in thickness from the thickness of the rib portion;
The first transition region on the back surface side of the semiconductor wafer is further provided by a second grindstone having a lower surface of the grinding surface parallel to the central portion on the back surface side of the semiconductor wafer and having an inclined surface from the lower surface toward the side surface. A region surrounded by is formed to form an intermediate region that is thicker than the thickness of the central portion and thinner than the rib portion and parallel to the central portion, and from the thickness of the intermediate region to the thickness of the central portion A second back grinding step for forming a second transition region where the thickness is gradually reduced to the thickness;
A method for manufacturing a semiconductor device, comprising: In the first back grinding step, a rising angle from the intermediate region is 15 ° or more and 45 ° or less between the rib portion and the intermediate region by grinding with the inclined surface of the first grindstone. Forming a first inclined surface, and a region having the first inclined surface becomes the first transition region;
In the second back grinding step, the rising angle from the central portion is 15 ° or more and 45 ° or less between the central portion and the intermediate region by grinding with the inclined surface of the second grindstone. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the second inclined surface is formed, and the region having the second inclined surface is a second transition region. In the said 2nd back surface grinding process, it grinds with a diameter smaller than a said 1st back surface grinding process so that the width | variety of the said intermediate area may be 0.2 mm or more and 3 mm or less. The manufacturing method of the semiconductor device as described in 2. above. 5. The method of manufacturing a semiconductor device according to claim 2, wherein in the second back grinding step, fine grinding is performed at a slower speed than in the first back grinding step. After the second back grinding step,
6. The method of manufacturing a semiconductor device according to claim 2, further comprising an etching step of etching the entire rear surface of the semiconductor wafer with a mixed acid.

Images