JP2004296817A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device which can reduce the occurrence of failure in crack and external appearance and can also improve productivity. <P>SOLUTION: A wafer 5 is set on a support base 1c provided at the circumferential part of a holder 1, an external circumferential part clamping ring 2 is placed thereon, and the wafer 5 and the external circumferential part clamping ring are pressed with a cover. Since the height L of the support base 1c is set as high as 6 mm if the wafer 5 is warped, the wafer 5 does not contact with the bottom surface 1d of the holder 1 and crack is not caused on the wafer 5. Moreover, since the circumferential part of the wafer 1 is uniformly clamped with the external circumferential part clamping ring, the amount of the warp of the wafer 5 can be reduced and the occurrence of failure in external appearance due to the occurrence of crack and damage can be prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device in which a metal electrode film is deposited on a back surface of a semiconductor wafer as an electrode film of a semiconductor device such as an insulated gate bipolar transistor (hereinafter, referred to as IGBT). The present invention relates to a method for manufacturing a thin semiconductor device manufactured by grinding and polishing.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a large number of transistors, resistors, and the like are connected and used for wiring in important parts of computers and communication devices, and integrated circuits (hereinafter, simply referred to as ICs) integrated on semiconductor chips (hereinafter, simply referred to as chips). Is also heavily used. A device obtained by further integrating a power semiconductor element on such an IC is called a power IC.
An IGBT (Insulated Gate Bipolar Transistor) is a power semiconductor device having both high-speed switching characteristics and voltage driving characteristics of a MOSFET and low on-voltage characteristics of a bipolar transistor. For this reason, IGBTs have been applied to not only industrial equipment fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS) and switching power supplies, but also consumer electronics fields such as microwave ovens, rice cookers and strobes. Furthermore, development to the next-generation device is also progressing, and a device having a lower on-voltage is developed by a new device structure, and a reduction in loss and a higher efficiency of an applied device are being achieved.
[0003]
The structure of the IGBT includes a punch-through type, a non-punch-through type, and a field stop type. Most of the currently mass-produced IGBTs have an n-channel vertical double diffusion structure except for a part of a p-channel type for an audio power amplifier. IGBT will be described.
The punch-through type has a structure in which an n ⁺ layer (buffer layer) is provided between a p ⁺ epitaxial substrate and an n ⁻ layer (active layer), and a depletion layer in the active layer reaches a buffer layer that is the n ⁺ layer. , IGBTs are the mainstream basic structure. For example, for a 600-V withstand voltage system, the thickness of the active layer, which is an n ⁻ layer, of about 70 μm is sufficient, but the total thickness including the p ⁺ substrate portion is 200 to 300 μm. Therefore, non-punch-through type IGBTs and field stop type IGBTs employing a low dose shallow p ⁺ collector layer for cost reduction of a chip using an FZ substrate instead of an epitaxial substrate have been developed. I have.
[0004]
FIG. 3 is a cross-sectional view of a main part of a non-punch-through IGBT employing a low dose shallow p ⁺ collector layer. The figure shows a 1/2 cell.
The non-punch-through type employing the low dose shallow p ⁺ collector layer 58 (low implantation p ⁺ collector) does not use a p ⁺ epitaxial substrate, so the total substrate thickness is significantly thinner than the punch-through type. In this structure, since the hole injection rate can be controlled, high-speed switching is possible without performing lifetime control. However, since the on-voltage depends on the thickness and the specific resistance of the n ⁻ layer 51 as the active layer, Somewhat high value. However, since the FZ substrate is used instead of the p ⁺ epitaxial substrate as described above, the cost of the chip can be reduced.
[0005]
In the figure, 52 is a p base layer, 53 is an n emitter layer, 54 is a gate insulating film, 55 is a gate electrode, 56 is an emitter electrode, 57 is an interlayer insulating film, and 59 is a collector electrode.
FIG. 4 is a sectional view of a main part of the field stop type IGBT. The figure shows a 1/2 cell.
The basic structure is the same as that of the punch-through type IGBT, except that the total thickness of the substrate is 100 μm to 200 μm by using an FZ (floating zone) substrate without using a p ⁺ epitaxial substrate. N which is also active layer and the punch-through type ^- thickness of the layer 51 is Yes in the order of 70μm in the case of breakdown voltage of 600V, for depleted whole area is obtained by applying the rated voltage, it is under the active layer n ⁺ layer 60 (n buffer layer) is provided. On the collector side, a shallow p ⁺ diffusion layer having a low dose is formed as the collector layer 58 and used as a low-implantation collector. This eliminates the need for lifetime control as in the non-punch-through type. (To further reduce the on-voltage, a trench IGBT having a narrow and deep groove formed on the chip surface and a gate electrode formed on a side surface of the groove with a gate insulating film interposed therebetween is referred to as a field stop type IGBT (FS-IGBT). There is also a structure combined with). Further, reduction of the total thickness has been promoted by optimizing the design and the like.
[0006]
However, in order to realize a thin IGBT of about 70 μm, back back grinding, ion implantation from the back surface, back surface heat treatment, and the like are required. However, the thinning of the wafer causes a large warpage of the wafer, which affects the manufacturing process. There are many technical issues such as giving.
FIGS. 5A to 5E are views for explaining a manufacturing process after the formation of the surface structure of the FS-IGBT. FIGS. 5A to 5E are cross-sectional views in the order of steps. First, a manufacturing process of the surface structure 61 will be described with reference to a cross-sectional view of a main part of the FS-IGBT of FIG.
(1) A gate insulating film 54 (here, SiO ₂ ) is formed on the front side of an n-type semiconductor wafer (hereinafter simply referred to as a wafer 50) which is an FZ-N substrate (an n-type substrate manufactured by a floating zone method). ), A gate electrode 55 made of polycrystalline silicon (here, Poly-Si) is deposited and processed, and an interlayer insulating film 57 (here, BPSG) is deposited and processed on the surface to form an insulated gate structure. Can be
(2) A p base layer 52 (p ⁺ ) is formed on the wafer 50, and then an n emitter layer 53 (n ⁺ ) is formed in the p base layer 52.
(3) A surface electrode (emitter electrode 56) made of an aluminum / silicon film is formed so as to be in contact with the n emitter layer 53. The aluminum / silicon film is thereafter heat-treated at a low temperature of about 400 to 500 ° C. in order to realize stable bonding and low-resistance wiring. Further, although not shown, an insulating protective film made of a polyimide film is formed so as to cover the surface. This is the process of forming the surface structure 61 (FIG. 5A).
[0007]
Next, the process on the back side will be described. The process on the back side is performed after the process on the front side is completed. Therefore, in FIG. 5, the details of the surface structure 61 on the front surface side shown in FIG. 4 are omitted.
(4) From the back side, the wafer 50 is thinned to a desired thickness using back grinding or etching (FIG. 9B).
(5) Next, in order to form the n ⁺ layer 60 as a buffer layer and the high concentration p collector layer 58 (p ⁺ layer), ion implantation is performed from the back surface. In this example, the n ⁺ layer 60 is implanted with phosphorus, and the p collector layer 58 is implanted with boron. Thereafter, heat treatment (annealing) is performed in an electric furnace. The heat treatment temperature is a low temperature of 350 ° C. to 500 ° C. (FIG. 3C).
(6) Next, on the high-concentration p collector layer 58 (p ⁺ layer), a metal serving as a back electrode (collector electrode 59) is formed by combining metal films such as an aluminum layer, a titanium layer, a nickel layer, and a gold layer. An electrode film is formed by vapor deposition using a semiconductor wafer holding jig (FIG. 4D).
(8) Next, the wafer is diced into chips (FIG. 9E).
[0008]
Finally, although not shown, an aluminum wire is fixed to the surface of the emitter electrode 56 having a surface structure by ultrasonic wire bonding, and the collector electrode 59 on the back surface is fixed to a fixing member via a solder layer.
Here, the semiconductor wafer holding jig used in the vapor deposition step (6) and a state in which the wafer is set in the jig will be described.
FIG. 6 is a view for explaining a conventional semiconductor wafer holding jig and a state in which a wafer is set in the jig. FIG. 6A is a plan view of a main part of the jig, and FIG. FIG. 3D is a cross-sectional view of a main part taken along line XX in FIG.
[0009]
The conventional semiconductor wafer holding jig 70 has a plate-shaped jig main body 71 with which the front end of the wafer 50 contacts, and an elastic return force of a spring 72 or the like, and is provided at four locations outward toward the center of the wafer 50. And four pins 73 for holding the wafer 50 therebetween. Further, a projection 75 of about 0.5 mm is provided so that the wafer 50 and the contact plate 74 do not come into direct contact with each other.
In addition to FIG. 6, various methods of holding a wafer when a thin film such as a metal electrode film of a semiconductor element such as an IGBT is formed on a wafer or when a diced wafer is formed into chips are described.
[0010]
For example, a wafer is placed in a concave portion of a tray, the peripheral portion of the wafer is pressed by a pressing tool, a gas for pressurization is introduced into the space of the concave portion, the wafer is fixed, and a thin film is formed on the exposed wafer surface (see Patent Document 1). ).
There is also known a method in which a wafer is placed on a substrate table in close contact with the wafer, and a peripheral portion of the wafer is pressed by a spring with a ring-shaped pressing plate to form a thin film on the exposed wafer surface (see Patent Document 2).
In addition, as a method for taking out chips from the wafer, an IC wafer is attached to an adhesive sheet, the adhesive sheet is stretched on a wafer ring, and a predetermined chip size is cut in advance by dicing. A method is known in which the space between the IC chips is widened to form a chip by widening the outside (Patent Document 3).
[0011]
Also, there is a method of holding the wafer by partially pressing the peripheral edge of the wafer in order to prevent adhesion of a wafer pressing portion generated when the wafer pressed and fixed to the clamp is removed from the clamp and to suppress a decrease in product yield. It is known (see Patent Document 4).
Further, in order to prevent cracks or chipping of the orientation flat portion of the wafer, there is a method of holding the wafer by pressing the entire orientation flat portion of the wafer and partially pressing the peripheral portion of the wafer at other locations (see Patent Document 5). ).
Further, after grinding the back surface of the semiconductor wafer, a method for forming a metal electrode film on the back surface without applying horizontal stress to the semiconductor wafer and holding the peripheral portion of the semiconductor wafer has been filed. Application 2002-233913).
[0012]
[Patent Document 1]
JP, 2002-43404, A
[Patent Document 2]
JP-A-7-130824 FIG.
[Patent Document 3]
Japanese Patent Application Laid-Open No. H11-214487
[Patent Document 4]
JP, 2002-299422, A
[Patent Document 5]
JP 2000-124295 A FIG.
[0013]
[Problems to be solved by the invention]
In the method of vapor deposition using the semiconductor wafer holding jig of FIG. 6, as described above, the wafer 50 is pinned from the four outside positions toward the center of the wafer 50 by using the elastic return force of the spring 72 or the like. It is deposited so as to be sandwiched.
In this method, when the wafer is as thick as several hundreds of μm, the warpage of the wafer is small, which is not a problem. However, when the thickness of the wafer 50 after back grinding the back surface is reduced to about 70 μm, the wafer 50 is often broken. This is because the metal film to be deposited has a tensile stress on the wafer 50, and as shown in FIG. 7, the amount of warpage caused by the stress increases as the thickness of the wafer 50 decreases. Therefore, as shown in FIG. 8, as the thickness of the wafer is reduced, the rate of occurrence of cracks is increased, and the productivity is significantly deteriorated. As a factor for increasing the crack generation rate, the method of holding the wafer at the time of vapor deposition has a great influence.
[0014]
In the jig for holding a semiconductor wafer as shown in FIG. 6A, the outer periphery of the wafer is suppressed by the pins 73 using the return force of the spring 72. Therefore, when the wafer 50 is thin, it is pushed by the pins 73. It bends and breaks. Further, since only a part of the wafer 50 is pressed, as shown in FIG. 6D, the warpage of the wafer 50 is large, and the wafer 50 comes into contact with the cover plate 74 to be scratched, resulting in poor appearance or cracking. Or
In order to solve this problem, when a method of pressing the peripheral portion of the wafer is used as described in Japanese Patent Application No. 2002-233913, there is a great effect in preventing the wafer from being cracked. Since the semiconductor wafer holding jig comes into contact with the wafer and the wafer is scratched, it is difficult to prevent poor appearance.
[0015]
An object of the present invention is to provide a method of manufacturing a semiconductor device which solves the above-mentioned problems, reduces cracking defects and appearance defects, and improves productivity.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a semiconductor device in which a back surface of a semiconductor wafer is ground and then a metal electrode film is formed on the back surface using a semiconductor wafer holding jig. In a state where substantially the entire back surface is exposed, the semiconductor wafer is held by sandwiching the peripheral edge of the semiconductor wafer from a direction perpendicular to the semiconductor wafer rear surface, and a region other than the peripheral edge of the semiconductor wafer is the semiconductor. The method is a method of depositing a metal electrode film on the back surface without contacting the wafer holding jig.
Further, a jig main body abutting on a peripheral portion of the front surface of the semiconductor wafer, and a support for pressing the peripheral portion of the semiconductor wafer from the back surface side of the semiconductor wafer in a state where substantially the entire back surface of the semiconductor wafer is exposed. A metal electrode film is deposited on the back surface of the semiconductor wafer by using a semiconductor wafer holding jig having a body.
[0017]
Further, it is preferable that a distance between a surface other than the peripheral portion of the semiconductor wafer and a bottom surface of the jig body opposed thereto is wider than a warpage of the semiconductor wafer in a process of depositing a metal electrode film.
Further, a method for manufacturing a semiconductor device, comprising: holding a semiconductor wafer having a backside ground on a semiconductor wafer holding jig such that the backside is exposed, and depositing a metal electrode film on the backside of the semiconductor wafer, The semiconductor wafer is brought into contact with the body jig side wall of the semiconductor wafer holding jig, and a ring-shaped contact table whose surface is arranged at a predetermined height from the bottom surface of the body jig such that the peripheral edge of the semiconductor wafer surface comes into contact with the ring-shaped contact table. Arranging, and arranging a ring-shaped pressing plate of the semiconductor wafer holding jig so as to be in contact with a peripheral portion of the back surface of the semiconductor wafer; and a ring-shaped lid and a body jig of the semiconductor wafer holding jig. A manufacturing method includes a step of pressing the semiconductor wafer and the ring-shaped holding plate sandwiched therebetween, and a step of depositing a metal electrode film on an exposed back surface of the semiconductor wafer.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
1A and 1B are views for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 1A is a perspective view of a semiconductor wafer holding jig, and FIGS. It is a process sectional view shown in order of a process. FIGS. 7B to 7D are views corresponding to the cross-sectional view taken along line XX of FIG. 8A, and show a method of setting a wafer on a semiconductor wafer holding jig in a vapor deposition process. FIG.
First, the semiconductor wafer holding jig will be described. The semiconductor wafer holding jig includes a holder 1 (main body jig), a lid 3 and an outer peripheral holding ring 2. The holder 1 is in contact with the inner side wall 1 a larger than the outer periphery of the wafer and the side wall 1 a. And a concave bottom surface 1d of the holder 1 in contact with the peripheral edge of the holder 1, and the height L of the support table in contact with the wafer 5 is set to be about 6 mm higher than the concave bottom. The width W1 of the support is set to 5 to 7 mm. The width W2 of the outer peripheral holding ring is 5 to 7 mm, and the thickness is 0.5 to 1 mm. A leaf spring 3 a is attached to the lid 3, and a handle 2 a is provided on the outer peripheral holding ring 2. The handle 2 a is made to fit into the notch 1 b of the side wall 1 a of the holder 1. The lid and the holder are provided with a hinge (not shown) that hinges at the part B. (Figure (a)).
[0019]
Next, a process of attaching a thin wafer of about 70 μm to 100 μm to a semiconductor wafer holding jig will be described with reference to FIGS.
First, the wafer 5 is placed so as to be in contact with the support 1c of the holder 1 of the semiconductor wafer holding jig attached to the dome of a vapor deposition device (not shown). Since the height L (height from the concave bottom surface 1d) of the support is about 6 mm, even if the wafer 5 warps due to the difference in thermal expansion coefficient when a metal electrode film is deposited on the wafer 5, The wafer 5 does not come into contact with the bottom surface 1d of the holder 1 and the wafer 5 is not scratched (FIG. 2B).
[0020]
Next, the handle portion 2a of the outer peripheral holding ring 2 is fitted with a notch 1b formed on the side wall 1a of the holder 1 with tweezers or the like sandwiched therebetween, and is mounted on the wafer 5. (FIG. (C)).
Next, the lid 3 is put on the holder 1, and the holder 1 and the lid 3 are sandwiched by the stoppers 4. A leaf spring 3a is attached to the lid 3. The leaf spring 3a uniformly presses the peripheral edge of the wafer 5 via the plate-shaped outer peripheral holding ring 2, so that the amount of warpage of the wafer 5 is reduced. In addition, since a strong pressure is not locally applied to the wafer 5, the rate of occurrence of cracks can be reduced (FIG. 4D).
[0021]
Next, the bell jar of a vacuum evaporation apparatus (not shown) is evacuated to start evaporation.
In this embodiment, the height L of the support 1c is set to about 6 mm, but the height L is set at the bottom of the wafer 5 when the wafer 5 is bent in the holder 1 and during the vapor deposition. What is necessary is just to design in the height which does not contact 1d. When the diameter of the wafer 5 is large or when the thickness of the wafer 5 is small, the height may be increased.
The pressing force of the leaf spring 3a is adjusted to a strength that does not break the wafer 5. Further, a notch (not shown) may be formed in a portion C on the side of the holder 1 so that the mounting and removing of the wafer 5 with tweezers or the like can be easily performed.
[0022]
By depositing a metal electrode film on the thin wafer surface using the semiconductor wafer support jig, the occurrence of scratches on the wafer 5 is prevented as described above, and the rate of occurrence of cracks is reduced as shown in FIG. It can be greatly reduced. In particular, even in the case of a wafer as thin as about 70 μm to 100 μm, the crack occurrence rate can be reduced to several percent. As a result, the productivity of the thin semiconductor device can be significantly improved. Further, appearance defects can be reduced by preventing the occurrence of scratches, and good electrical characteristics can be obtained.
The above is summarized as follows. As described above, by changing from the pin type to the holder type, cracks during wafer setting can be reduced. Further, by sandwiching the outer peripheral portion of the wafer between the support base 1c and the outer peripheral portion holding ring 2, it is possible to forcibly suppress the warpage of the wafer 5 at the time of forming the deposited film. By providing a gap larger than the amount of warpage between the bottom surface 1d of the holder 1 and the wafer 5, the contact between the wafer 5 and the bottom surface 1d is eliminated, and scratches and cracks can be reduced. Further, since the cover 3 of the holder 1 has the leaf spring 3a, when the cover 3 is closed, the outer peripheral portion of the wafer 5 can be softly pressed without applying a vertical stress, thereby reducing cracking. be able to.
[0023]
【The invention's effect】
In the present invention, by vapor-depositing a thin film wafer using the above-described jig for holding a semiconductor wafer, appearance defects due to scratches and the rate of occurrence of cracks can be significantly reduced, and the productivity of thin semiconductor devices can be increased.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a perspective view of a jig for holding a semiconductor wafer, and FIGS. FIG. 2 is a diagram showing a relationship between a wafer thickness and a crack occurrence rate. FIG. 3 is a cross-sectional view of a main part of a non-punch-through IGBT employing a low dose shallow p ⁺ collector layer. FIG. 4 is a field stop type. FIG. 5 is a view for explaining a manufacturing process after a surface structure of the FS-IGBT is formed. FIGS. 5A to 5E are process cross-sectional views shown in the order of processes. It is a figure explaining the state where the semiconductor wafer holding jig and the wafer were set in the jig, (a) is a main part plan view of the jig, and (b) to (d) are XX lines of (a). FIG. 7 is a cross-sectional view of a main part cut away. FIG. 7 is a view showing the relationship between the thickness of a wafer and the amount of warpage. Diagram showing the relationship between thickness and crack occurrence rate [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Holder 1a Side wall 1b Notch 1c Support 1d Bottom 2 Outer peripheral holding ring 2a Handle 3 Cover 3a Leaf spring 4 Clamp 5 Wafer W1 Width of supporting base W2 Width of outer holding ring L Height of supporting base

Claims (4)

After grinding the back surface of the semiconductor wafer, using a semiconductor wafer holding jig, a method of manufacturing a semiconductor device for forming a metal electrode film on the back surface,
With the substantially entire back surface of the semiconductor wafer exposed, the semiconductor wafer is held by sandwiching the peripheral edge of the semiconductor wafer from a direction perpendicular to the back surface of the semiconductor wafer, and the semiconductor wafer other than the peripheral edge of the semiconductor wafer is held. A method of manufacturing a semiconductor device, comprising: depositing a metal electrode film on the back surface in a state where a region does not contact the semiconductor wafer holding jig. A jig body that abuts a peripheral portion of the front surface of the semiconductor wafer, and a support that presses the peripheral portion of the semiconductor wafer from the back surface side of the semiconductor wafer while substantially the entire back surface of the semiconductor wafer is exposed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a metal electrode film is deposited on the back surface of the semiconductor wafer using a semiconductor wafer holding jig having the following. 3. The semiconductor wafer according to claim 1, wherein an interval between a surface other than a peripheral portion of the semiconductor wafer and a bottom surface of the jig body opposed thereto is larger than a warpage of the semiconductor wafer in a process of depositing a metal electrode film. 13. The method for manufacturing a semiconductor device according to item 5. A method of manufacturing a semiconductor device, comprising: holding a semiconductor wafer having a backside ground on a semiconductor wafer holding jig so that the backside is exposed, and depositing a metal electrode film on the backside of the semiconductor wafer. The semiconductor wafer is arranged in contact with a side wall of the main body jig of the holding jig and on a ring-shaped contact table whose surface is arranged at a predetermined height from the bottom surface of the main body jig such that a peripheral portion of the semiconductor wafer surface is in contact with the ring-shaped contact table. A step of arranging a ring-shaped holding plate of the semiconductor wafer holding jig so as to be in contact with a peripheral portion of the back surface of the semiconductor wafer, and a step of arranging the ring-shaped lid of the semiconductor wafer holding jig and the main body jig. A method for manufacturing a semiconductor device, comprising: a step of pressing the sandwiched semiconductor wafer and the ring-shaped pressing plate; and a step of depositing a metal electrode film on an exposed back surface of the semiconductor wafer.

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