CN115621302A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115621302A CN115621302A CN202211347019.4A CN202211347019A CN115621302A CN 115621302 A CN115621302 A CN 115621302A CN 202211347019 A CN202211347019 A CN 202211347019A CN 115621302 A CN115621302 A CN 115621302A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 17
- 239000000463 material Substances 0.000 claims abstract description 78
- 238000005520 cutting process Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 14
- 230000003014 reinforcing effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The device comprises a plurality of chip functional areas and a plurality of cutting road areas which are arranged around the peripheries of the chip functional areas in a one-to-one correspondence manner; each cutting channel area is internally provided with a groove structure, each groove structure comprises a groove arranged in the substrate of the cutting channel area and a filling material filled in the groove, and each groove at least comprises a first groove extending along a first direction and a second groove extending perpendicular to the first direction and communicated with the first groove; wherein the filling material comprises a material with hardness greater than that of a substrate of the semiconductor device, and the groove structures in the plurality of cutting channel regions jointly form a frame structure. Therefore, during preparation, a reticular reinforcing structure can be formed on the whole wafer of the semiconductor device, and the problem that the wafer is warped in the manufacturing process due to the arrangement of the deep groove on the semiconductor device can be effectively solved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Power semiconductor devices, also known as power electronics devices, are mainly used in power conversion and control circuits of power equipment. The existing semiconductor power device comprises a trench type semiconductor power device, wherein a trench is formed in an epitaxial layer through a deep trench process, and then a dielectric layer and a polysilicon shielding gate are filled in the trench to form a structure for reducing a surface electric field in a vertical direction, so that the performances of the semiconductor power device, such as breakdown voltage, on-resistance and the like, are improved. Common trench type semiconductor power devices mainly include shielded gate power devices, super junction devices, insulated gate bipolar transistors and the like.
The whole chip of the trench type semiconductor power device is composed of repeated deep trench structures, so that the wafer warping phenomenon inevitably occurs in the wafer manufacturing process. In order to solve the above problems, the main solution at present is to use a TAIKO grinding process, i.e. a margin is left on the periphery of the wafer, and only the inside of the wafer is ground and thinned, so as to improve the strength of the wafer. However, the existing method for solving the wafer warpage still has the problem of poor strength, and the wafer is still warped to a certain extent by adopting the method, so that the growing high demand of users is difficult to meet.
Disclosure of Invention
The invention provides a semiconductor device and a preparation method thereof, which can effectively solve the problem that a semiconductor wafer warps in the manufacturing process.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention provides a semiconductor device, which comprises a plurality of chip functional areas and a plurality of cutting path areas which are arranged around the peripheries of the chip functional areas in a one-to-one correspondence manner; each cutting path area is internally provided with a groove structure, each groove structure comprises a groove arranged in the substrate of the cutting path area and filling materials filled in the groove, and each groove at least comprises a first groove extending along a first direction and a second groove extending along a direction perpendicular to the first direction and communicated with the first groove; wherein the filling material comprises a material with hardness greater than that of a substrate of the semiconductor device, and the groove structures in the plurality of cutting channel regions jointly form a frame structure. According to the invention, the groove structure is arranged in each cutting channel area, and the groove structures of the plurality of cutting channel areas form the frame structure together, so that a reticular reinforcing structure can be formed on the whole wafer of the semiconductor device during preparation, and the problem of warping of the wafer in the manufacturing process caused by the arrangement of the deep grooves in the semiconductor device can be effectively solved.
In one possible embodiment, the fill material includes silicon nitride and a buffer material, the buffer material being located between the silicon nitride and the recess. Through setting up the filler material into silicon nitride and buffer material, like this, the stress problem between silicon nitride and the substrate can be alleviated to buffer material, avoids filler material and substrate bonding degree not good.
In one possible embodiment, the buffer material is an oxide.
In one possible embodiment, the thickness of the buffer material is between 300A and 500A.
In a possible embodiment, the grooves further include a third groove and a fourth groove, and the first groove, the second groove, the third groove and the fourth groove are enclosed to form an annular structure. Thus, the groove structure can surround the periphery of the chip functional region, so that the strength of the frame structure can be enhanced.
In a possible embodiment, the ring structures include a plurality of ring structures, the plurality of ring structures sequentially surround the periphery of the chip functional region, and two adjacent ring structures are communicated with each other. In this way, the strength of the frame structure can be further enhanced compared to the case where a ring structure is provided around the chip functional region.
In a possible embodiment, the groove further comprises a connecting groove provided between two adjacent ring structures. Through setting up the spread groove, can conveniently realize being connected between two adjacent ring structures.
In a possible embodiment, the connection groove between two adjacent ring structures includes a plurality of connection grooves, and any one of the ring structures is staggered with the connection groove between the ring structures on one side and the connection groove between the ring structures on the other side. The connecting strength between two adjacent annular structures can be improved by arranging the connecting grooves, and the strength of the frame structure can be effectively improved by the staggered arrangement.
In one possible embodiment, the filling material includes a first portion located within the recess, and a second portion of the substrate extending outwardly from the first portion and covering the scribe line region. Therefore, the filling material can be filled in the groove and can also cover the upper surface of the cutting road area, and the structural strength of the frame structure can be further improved.
The present invention also provides a method for manufacturing a semiconductor device, the semiconductor device comprising: providing a semiconductor device, wherein the semiconductor device comprises a plurality of chip functional areas and a plurality of cutting channel areas which are arranged around the peripheries of the chip functional areas in a one-to-one correspondence manner; forming grooves in each cutting path region through a photoetching process, wherein the grooves at least comprise first grooves extending along a first direction and second grooves extending perpendicular to the first direction and communicated with the first grooves; and forming a filling material in the groove, wherein the filling material comprises a material with hardness greater than that of a substrate of the semiconductor device, the filling material in each cutting path area and the groove together form a groove structure, and the groove structures in the cutting path areas together form a frame structure. According to the semiconductor device prepared by the preparation method of the semiconductor device, each cutting channel area of the device is provided with the groove structure, and the plurality of groove structures form the frame structure together, so that the strength of the semiconductor device can be effectively enhanced, the problem that the semiconductor wafer is warped and deformed due to the arrangement of the deep grooves in the semiconductor wafer is effectively solved in the preparation process of the semiconductor, and the reliability of the semiconductor device is improved.
The semiconductor device structure provided by the invention has the beneficial effects that:
the invention provides a semiconductor device, which comprises a plurality of chip functional areas and a plurality of cutting path areas which are arranged around the peripheries of the chip functional areas in a one-to-one correspondence manner; each cutting path area is internally provided with a groove structure, each groove structure comprises a groove arranged in the substrate of the cutting path area and filling materials filled in the groove, and each groove at least comprises a first groove extending along a first direction and a second groove extending along a direction perpendicular to the first direction and communicated with the first groove; wherein the filling material comprises a material with hardness greater than that of the substrate of the semiconductor device, and the groove structures in the plurality of cutting path areas jointly form a frame structure. According to the invention, the groove structure is arranged in each cutting channel region of the semiconductor device, and the groove structures of the plurality of cutting channel regions form the frame structure located in the cutting channel region of the semiconductor device together, so that during preparation, a reticular reinforcing structure can be formed on the whole wafer of the semiconductor device, and the problem of warping of the wafer in the manufacturing process caused by the arrangement of the deep groove in the semiconductor device can be effectively solved.
Drawings
The invention is further described with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of a semiconductor device according to the present invention;
FIG. 2 is a second schematic structural diagram of a semiconductor device according to the present invention;
fig. 3 is a third schematic structural diagram of a semiconductor device according to the present invention;
FIG. 4 isbase:Sub>A cross-sectional view taken along line A-A of FIG. 2;
FIG. 5 isbase:Sub>A second cross-sectional view taken along line A-A of FIG. 2;
fig. 6 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present invention.
Reference numerals: 10-chip functional area; 20-cutting track area; 30-a trench structure; 31-a groove; 311-a first groove; 312-a second groove; 313-a third groove; 314-a fourth groove; 315-connecting trough; 32-a filler material; 321-silicon nitride; 322-a buffer material; 323-first part; 324-a second portion; 40-substrate.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The invention provides a semiconductor device and a preparation method thereof, wherein each cutting channel region 20 (each chip functional region 10 corresponds to one cutting channel region 20) of the semiconductor device is correspondingly provided with a groove structure 30, so that the groove structures 30 of all the cutting channel regions 20 can form a frame structure on the semiconductor device, and the frame structure is spread over the whole semiconductor device, and thus, compared with the prior art, the semiconductor device can effectively solve the problem that a semiconductor wafer is warped in the preparation process due to the arrangement of deep grooves. The details of the semiconductor device and the method for manufacturing the same provided in the present application will be explained and explained below.
The first implementation mode comprises the following steps:
as shown in fig. 1 and fig. 2, the semiconductor device provided by the present application includes a plurality of chip functional regions 10 and a plurality of scribe line regions 20 surrounding the peripheries of the plurality of chip functional regions 10 in a one-to-one correspondence; each cutting channel area 20 is internally provided with a groove structure 30, each groove structure 30 comprises a groove 31 arranged in the substrate 40 of the cutting channel area 20 and a filling material 32 filled in the groove 31, and each groove 31 at least comprises a first groove 311 arranged in a extending mode along a first direction and a second groove 312 which extends in a direction perpendicular to the first direction and is communicated with the first groove 311; wherein the filling material 32 comprises a material having a hardness greater than that of the substrate 40 of the semiconductor device, and the trench structures 30 in the plurality of scribe line regions 20 collectively form a frame structure.
The semiconductor device includes a plurality of chip functional regions 10 and a plurality of scribe line regions 20, wherein the periphery of each chip functional region 10 is surrounded by a corresponding scribe line region 20, and all the scribe line regions 20 are combined to form a total scribe line region 20. Exemplarily, as shown in fig. 1, fig. 1 illustrates that the semiconductor device includes nine chip functional regions 10, and in this case, the nine chip functional regions 10 correspond to one scribe line region 20 one by one, respectively. Of course, in other embodiments, it may also be considered that there are a plurality of chip functional regions 10, there is only one dicing lane region, and the dicing lane region includes a plurality of sub-dicing lane regions 20, and each sub-dicing lane region 20 is surrounded on the periphery of each chip functional region 10 in a one-to-one correspondence. It should be understood that the above two ways are merely descriptive differences, which are the same in nature, and should not be considered as limitations of the scribe line region 20 and the chip functional region 10.
Each scribe line region 20 is provided with a trench structure 30, and the trench structure 30 includes a groove 31 provided in the substrate 40 of the scribe line region 20 and a filling material 32 filled in the groove 31. Here, the substrate 40 is a substrate 40 of a semiconductor device, and may be a single base or may include a base and an epitaxial layer. When including a substrate and an epitaxial layer, the trench structure 30 is formed in the epitaxial layer of the scribe line region 20.
In addition, the groove 31 is at least provided with the first groove 311 extending in the first direction and the second groove 312 extending in the direction perpendicular to the first direction, so that each groove structure 30 can be ensured to have a transverse structure and a longitudinal structure, and the structural strength of the groove structure 30 can be effectively improved.
In addition, this application is with first recess 311 and second recess 312 intercommunication each other, like this, can make the filling material 32 of filling in first recess 311 and second recess 312 be the continuity, so, can effectively promote the structural stability and the uniformity of trench structure 30, avoid trench structure 30 dispersion to reduce overall structure intensity.
In a possible embodiment, as shown in fig. 2, the first recess 311 may be disposed on one side of the functional region 10, and the second recess 312 is disposed on the other side of the functional region 10. The number of the first grooves 311 and the second grooves 312 is not limited.
In another possible embodiment, as shown in fig. 3, the first recess 311 and the second recess 312 may be disposed on the same side of the chip functional region 10, and the first recess 311 and the second recess 312 are disposed orthogonally. It should be noted that, when the first recess 311 and the second recess 312 are orthogonally disposed, the number of the first recess 311 and the second recess 312 can be determined by those skilled in the art, and the present application is not limited thereto. In addition, assuming that the first recess 311 and the second recess 312 are orthogonal to form an orthogonal group, the orthogonal group located at one side of the chip functional region 10 and the orthogonal group located at the other side of the chip functional region 10 may or may not be connected to each other. Fig. 3 is a diagram illustrating an example in which the orthogonal set on one side of the functional region 10 of the chip and the orthogonal set on the other side of the functional region 10 of the chip are connected to each other.
In the two possible embodiments, a person skilled in the art may select any one of the setting manners as needed, and the application is not limited.
The filling material 32 includes at least one material having a hardness greater than that of the substrate 40 of the semiconductor device, so that a frame structure having sufficient strength can be formed in the scribe line region 20 of the semiconductor device, thereby effectively increasing the overall hardness of the semiconductor device as compared to the prior art.
It should be noted that the groove structures 30 in any two adjacent scribe line regions 20 may or may not be connected to each other. Preferably, the trench structures 30 in any two adjacent dicing street regions 20 are interconnected. Therefore, the groove structures 30 in the two adjacent cutting path regions 20 are connected, so that the preparation of the groove structures 30 is more convenient, and the preparation method is more convenient and easier to realize; secondly, all the trench structures 30 can be integrated to obtain a large frame structure, and the frame structure is uniformly distributed on the whole semiconductor device, so that the structural strength of the semiconductor device is improved as a whole, and the semiconductor wafer is prevented from warping in the preparation process.
In one possible embodiment, referring to fig. 4, the filling material 32 includes silicon nitride 321 (silicon nitride 321 is a material with hardness greater than that of the substrate 40 of the semiconductor device mentioned above) and a buffer material 322, and the buffer material 322 is located between the silicon nitride 321 and the recess 31 (i.e., the buffer material 322 and the silicon nitride 321 are sequentially filled in the recess 31, such that the buffer material 322 is located between the silicon nitride 321 and the substrate 40).
According to the application, the filling material 32 is set to be the silicon nitride 321 and the buffer material 322, and the buffer material 322 is set between the silicon nitride 321 and the substrate 40, so that the buffer material 322 can relieve the stress problem between the silicon nitride 321 and the substrate 40, and poor bonding degree between the filling material 32 and the substrate 40 is avoided.
The specific material type of the buffer material 322 can be determined by those skilled in the art, as long as the selection of the buffer material 322 can be satisfied to alleviate the stress problem between the silicon nitride 321 and the substrate 40, and improve the bonding degree. Illustratively, in one possible embodiment, the buffer material 322 may be an oxide.
Optionally, the thickness of the above-described buffer material 322 may be between 300A and 500A. For example, the thickness of the buffer material 322 may be 300A, 400A, or 500A, etc., which are not listed in this application.
In summary, the present invention provides a semiconductor device, which includes a plurality of chip functional regions 10 and a plurality of scribe line regions 20 surrounding the periphery of the chip functional regions 10 in a one-to-one correspondence; each cutting channel area 20 is internally provided with a groove structure 30, each groove structure 30 comprises a groove 31 arranged in the substrate 40 of the cutting channel area 20 and a filling material 32 filled in the groove 31, and each groove 31 at least comprises a first groove 311 arranged in a extending mode along a first direction and a second groove 312 which extends in a direction perpendicular to the first direction and is communicated with the first groove 311; wherein the filling material 32 comprises a material having a hardness greater than that of the substrate 40 of the semiconductor device, and the trench structures 30 in the plurality of scribe line regions 20 collectively form a frame structure. According to the invention, the groove structure 30 is arranged in each dicing channel area 20 of the semiconductor device, so that a plurality of groove structures 30 can jointly form a frame structure positioned in the dicing channel area 20 of the semiconductor device, and on one hand, a reticular reinforcing structure can be formed on the whole wafer of the semiconductor device during preparation, and the problem of warping of the wafer caused by arrangement of deep grooves in the semiconductor device in the manufacturing process can be effectively solved. In addition, in the present application, the filling material 32 is configured as the silicon nitride 321 and the oxide, and the oxide is disposed between the silicon nitride 321 and the substrate 40, so that the oxide can play a role of buffering, and the stress problem between the silicon nitride 321 and the substrate 40 is improved, thereby improving the bonding strength of the two, and thus further improving the overall strength of the semiconductor device.
Second embodiment
In this embodiment, the trench structure 30 provided in this embodiment may be a ring structure as compared to the first embodiment.
In this embodiment, referring to fig. 2, the groove 31 further includes a third groove 313 and a fourth groove 314, and the first groove 311, the second groove 312, the third groove 313 and the fourth groove 314 form an annular structure in an enclosing manner. In this way, the groove structure 30 can surround the periphery of the chip functional region 10, so that the strength of the frame structure can be further enhanced.
It should be noted that the specific length-width ratio of the ring structure may depend on the sizes of the chip functional region 10 and the scribe line region 20, and the application is not limited thereto.
In a possible embodiment, the ring structure includes a plurality of ring structures, the plurality of ring structures sequentially surround the periphery of the chip functional region 10, and two adjacent ring structures are communicated with each other. In this way, the strength of the frame structure can be further enhanced compared to the case where a ring structure is provided around the outer periphery of the chip functional region 10.
In short, the ring-shaped structures may include a plurality of ring-shaped structures, and in order to be sequentially arranged around the periphery of the chip functional region 10, a gap is formed between two adjacent ring-shaped structures, and the two adjacent ring-shaped structures can be communicated with each other.
It should be noted that, in the first embodiment, the specific number of the ring structures is not limited, and may include 3, 4, 5, and the like. Of course, it may be 1 or 2. The specific number of cyclic structures can be determined by one skilled in the art as a function of the circumstances.
Secondly, the groove 31 further includes a connecting groove 315 disposed between two adjacent ring structures (since the connecting groove 315 is a part of the groove 31, the connecting groove 315 should be filled with the filling material 32). Thus, the present embodiment can conveniently realize the connection between two adjacent ring structures by providing the connection groove 315. It should be understood that the arrangement of the connecting grooves 315 and the corresponding filling of the filling material 32 in the connecting grooves 315 to realize the connection of two adjacent ring structures are only an example given in the present application, and are not a limitation to the present application. In other embodiments, a person skilled in the art can select other ways to connect two adjacent ring structures.
Third, in a possible embodiment, the connection groove 315 between two adjacent ring structures may also include a plurality of connection grooves, and any one of the ring structures is staggered with the connection groove 315 between the ring structures on one side and the connection groove 315 between the ring structures on the other side, as shown in fig. 2. The connection strength between two adjacent annular structures can be improved by arranging the plurality of connection grooves 315, and the strength of the frame structure can be effectively improved by the staggered arrangement.
It should be noted that, taking the ring structures including three, any one of the above ring structures refers to the second layer ring structure as an example, the above staggered arrangement means that all the connection slots 315 between the second layer ring structure and the first layer ring structure are respectively offset from all the connection slots 315 between the second layer ring structure and the third layer ring structure.
Specifically, the connecting groove 315 and the first, second, third and fourth grooves 311, 312, 313 and 314 may be prepared by the same process, and besides connecting the two adjacent ring structures to form the frame, the connecting groove 315 is vertically connected to the ring structures, so that an orthogonal layout may be formed, and the overall strength of the frame structure is enhanced.
It should be understood that, in the present embodiment, other parts that are not described are all used in common relative to the first embodiment, and therefore, in order to avoid repeated description, no further description is provided in the present embodiment.
Third embodiment
Here, it should be noted that the present embodiment may be coexistent with the first embodiment alone, or may be coexistent with the first and second embodiments, and the present application is not limited thereto. In this embodiment, the same portions as those in the first and second embodiments will not be described repeatedly, and only different portions will be described in this embodiment.
Referring to fig. 5, in this embodiment, compared to the first and second embodiments, the filling material 32 includes a first portion 323 located in the groove 31, and a second portion 324 extending outward from the first portion 323 and covering the substrate 40 of the scribe line region 20.
In this way, the filling material 32 may not only fill the groove 31, but also cover the upper surface of the scribe line region 20 (i.e., the upper surface of the substrate 40), so that the structural strength of the frame structure may be further improved compared to filling the filling material 32 only in the groove 31.
Example IV
The present invention further provides a method for manufacturing a semiconductor device, referring to fig. 6, the semiconductor device includes the following steps:
s100, providing a semiconductor device, wherein the semiconductor device comprises a plurality of chip functional areas 10 and a plurality of cutting track areas 20 which are arranged around the peripheries of the chip functional areas 10 in a one-to-one correspondence mode.
It should be noted that the chip functional region 10 and the scribe lane region 20 have already been described in detail in the first embodiment, and please refer to the foregoing description, and the description of this embodiment is not repeated.
S200, forming a groove 31 in each scribe line region 20 by a photolithography process, wherein the groove 31 at least includes a first groove 311 extending along a first direction and a second groove 312 extending perpendicular to the first direction and communicating with the first groove 311.
Since the photolithography process is well known to those skilled in the art, the process will not be described in detail in this embodiment.
Here, the specific shape of the cross section of the groove 31 is not limited in the present application, and may be, for example, a square, a circle, a polygon, or the like.
And S300, forming a filling material 32 in the groove 31, wherein the filling material 32 comprises a material with hardness greater than that of the substrate 40 of the semiconductor device, the filling material 32 of each dicing lane area 20 and the groove 31 jointly form a groove structure 30, and the groove structures 30 in the dicing lane areas 20 jointly form a frame structure.
It should be noted that the type of the filling material 32, the shape and the arrangement of the trench structure 30, and the like in the present embodiment have been described in detail in the foregoing embodiments, so that the description of this part is omitted here, and the same contents as those in the foregoing embodiments can be referred to in the foregoing.
In summary, in the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the embodiment, each scribe line region 20 of the device has the trench structure 30, and the plurality of trench structures 30 form a frame structure together, so that the strength of the semiconductor device can be effectively enhanced, the problem of warpage deformation of the semiconductor wafer caused by the arrangement of the deep trench in the semiconductor manufacturing process can be effectively solved, and the reliability of the semiconductor device can be improved.
While the invention has been described with reference to several particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. The semiconductor device is characterized by comprising a plurality of chip functional areas and a plurality of cutting channel areas which are arranged around the peripheries of the chip functional areas in a one-to-one correspondence manner; each cutting channel area is internally provided with a groove structure, each groove structure comprises a groove arranged in a substrate of the cutting channel area and a filling material filled in the groove, and each groove at least comprises a first groove extending along a first direction and a second groove extending perpendicular to the first direction and communicated with the first groove; wherein the filling material comprises a material with hardness greater than that of a substrate of the semiconductor device, and the groove structures in the cutting path areas jointly form a frame structure.
2. The semiconductor device of claim 1, wherein the fill material comprises silicon nitride and a buffer material, the buffer material being located between the silicon nitride and the recess.
3. The semiconductor device according to claim 2, wherein the buffer material is an oxide.
4. The semiconductor device of claim 2, wherein the buffer material has a thickness between 300A and 500A.
5. The semiconductor device according to any one of claims 1 to 4, wherein the grooves further comprise a third groove and a fourth groove, and the first groove, the second groove, the third groove and the fourth groove enclose a ring-shaped structure.
6. The semiconductor device according to claim 5, wherein the ring-shaped structures include a plurality of ring-shaped structures, the plurality of ring-shaped structures are sequentially arranged around the periphery of the chip functional region, and two adjacent ring-shaped structures are communicated with each other.
7. The semiconductor device according to claim 6, wherein the groove further comprises a connection groove provided between two adjacent ring structures.
8. The semiconductor device according to claim 7, wherein the connection groove between two adjacent ring structures comprises a plurality of connection grooves, and any one of the ring structures is staggered with the connection groove between the ring structures on one side and the connection groove between the ring structures on the other side.
9. The semiconductor device of claim 5, wherein the fill material comprises a first portion located within the recess, a second portion of the substrate extending outward from the first portion and covering the scribe line region.
10. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor device, wherein the semiconductor device comprises a plurality of chip functional areas and a plurality of cutting channel areas which are arranged around the peripheries of the chip functional areas in a one-to-one correspondence manner;
forming grooves in each dicing channel area through a photoetching process, wherein the grooves at least comprise first grooves extending along a first direction and second grooves extending perpendicular to the first direction and communicated with the first grooves;
and forming a filling material in the groove, wherein the filling material comprises a material with hardness greater than that of a substrate of a semiconductor device, the filling material and the groove of each cutting channel region jointly form a groove structure, and the groove structures in the cutting channel regions jointly form a frame structure.
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| CN115621302B (en) | 2023-08-11 |
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Denomination of invention: Semiconductor devices and their preparation methods Effective date of registration: 20231228 Granted publication date: 20230811 Pledgee: Wuding Road Sub branch of Bank of Shanghai Co.,Ltd. Pledgor: Shanghai Gongcheng Semiconductor Technology Co.,Ltd. Registration number: Y2023980075345 |