CN115223990A - Semiconductor structure and method for forming semiconductor structure - Google Patents
Semiconductor structure and method for forming semiconductor structure Download PDFInfo
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- CN115223990A CN115223990A CN202110432166.0A CN202110432166A CN115223990A CN 115223990 A CN115223990 A CN 115223990A CN 202110432166 A CN202110432166 A CN 202110432166A CN 115223990 A CN115223990 A CN 115223990A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 303
- 239000002184 metal Substances 0.000 claims abstract description 303
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 238000005520 cutting process Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 239000007788 liquid Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000007789 sealing Methods 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 239000012466 permeate Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor structure and method of forming the same, the structure comprising: a substrate including a chip region, the chip region including a device region and a scribe line region surrounding the device region; a guard ring structure located on the scribe line region, the guard ring structure surrounding the device region, the guard ring structure comprising: the second metal structure at least comprises a second metal layer, the second metal layer is positioned between two adjacent first metal layers, any one of the second metal layers is mutually separated, and the central lines of two adjacent second metal layers are not overlapped. The performance of the semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Since the silicon material is brittle, when the wafer is cut, the cutting method of the cutting knife generates a certain mechanical stress on the front and back surfaces of the wafer, which may cause edge chipping at the edge of the chip. Edge chipping can reduce the mechanical strength of the chip, and the initial chip edge crack can further propagate in the subsequent packaging process or during the use of the chip product, possibly causing chip fracture and thus causing electrical failure of the chip. In order to protect the internal circuit of the chip, prevent the dicing damage and improve the chip reliability, a Seal Ring (SR) structure is usually designed at the periphery of the chip.
When the wafer cutting process is performed along the scribe lines, the chip seal ring structure can prevent unnecessary stress from the scribe lines to the chip from spreading and cracking due to the wafer cutting process. And the chip sealing ring structure also has the capability of resisting gas-liquid erosion and can prevent the permeation and damage of water vapor or other chemical pollution sources.
In the current semiconductor technology, the shrinking size of the semiconductor device puts higher demands on the crack blocking capability and the gas-liquid shielding capability of the chip sealing ring.
Therefore, how to enhance the gas-liquid barrier capability and the fracture barrier capability of the chip seal ring structure is a problem to be solved urgently.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, aiming at enhancing the performance of a chip sealing ring structure.
In order to solve the above technical problem, a technical solution of the present invention provides a semiconductor structure, including: a substrate including a chip region, the chip region including a device region and a scribe line region surrounding the device region; a guard ring structure located on the scribe line region, the guard ring structure surrounding the device region, the guard ring structure comprising: the second metal structure at least comprises a second metal layer, the second metal layer is positioned between two adjacent first metal layers, any one of the second metal layers is mutually separated, and the central lines of two adjacent second metal layers are not overlapped.
Optionally, the second metal structure includes a plurality of second metal layers, and the plurality of second metal layers are concentrically distributed around the device region in a direction parallel to the substrate surface.
Optionally, the number of the first metal layers is multiple, in a direction parallel to the substrate surface, the multiple first metal layers are concentrically distributed with the device region as a center, and the first metal layers and the second metal layers are arranged in an overlapping manner in a direction perpendicular to the substrate surface.
Optionally, the number of the guard ring structures is multiple, and the multiple guard ring structures are concentrically distributed with the device region as a center.
Optionally, a projection pattern of the first metal layer on the substrate is a closed ring shape, and the closed ring shape has a first width; the projection pattern of the second metal layer on the substrate forms an interrupted ring shape, and the interrupted ring shape has a second width.
Optionally, the first width is greater than the second width, or the first width is smaller than the second width.
Optionally, the protection ring structure further includes: the metal layer structure comprises a plurality of third metal layers and a plurality of fourth metal layers, wherein the third metal layers and the fourth metal layers are alternately arranged in a direction vertical to the surface of the substrate, the projection pattern of the third metal layers on the substrate is in a closed ring shape, and the projection pattern of the fourth metal layers on the substrate is in a closed ring shape.
Optionally, the guard ring structure further includes: the metal layer structure comprises a plurality of fifth metal layers and a plurality of sixth metal layers which are alternately arranged in the direction perpendicular to the surface of the substrate, wherein the fifth metal layers are mutually separated, the sixth metal layers are mutually separated, the center lines of two adjacent fifth metal layers are not overlapped, and the center lines of two adjacent sixth metal layers are not overlapped.
Optionally, a projection pattern of the fifth metal layer on the substrate forms a discontinuous ring shape, and a projection pattern of the sixth metal layer on the substrate forms a discontinuous ring shape.
Optionally, the method further includes: a dielectric structure on a substrate, the guard ring structure being located within the dielectric structure.
Optionally, the material of the first metal layer includes a metal or a metal nitride; the material of the second metal layer comprises a metal or a metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a chip area, and the chip area comprises a device area and a cutting channel area surrounding the device area; forming a guard ring structure in the scribe line region, the guard ring structure surrounding the device region, the guard ring structure comprising: the second metal structure at least comprises a second metal layer, the second metal layer is positioned between two adjacent first metal layers, any one of the second metal layers is mutually separated, and the central lines of two adjacent second metal layers are not overlapped.
Optionally, the second metal structure includes a plurality of second metal layers, and the plurality of second metal layers are concentrically distributed with the device region as a center in a direction parallel to the substrate surface.
Optionally, the number of the first metal layers is multiple, in a direction parallel to the substrate surface, the multiple first metal layers are concentrically distributed with the device region as a center, and the first metal layers and the second metal layers are arranged in an overlapping manner in a direction perpendicular to the substrate surface.
Optionally, the number of the guard ring structures is multiple, and the multiple guard ring structures are concentrically distributed with the device region as a center.
Optionally, a projection pattern of the first metal layer on the substrate is a closed ring shape, and the closed ring shape has a first width; the projection pattern of the second metal layer on the substrate forms an interrupted ring shape, and the interrupted ring shape has a second width.
Optionally, the first width is greater than the second width, or the first width is smaller than the second width.
Optionally, the protection ring structure further includes: the metal layer structure comprises a plurality of third metal layers and a plurality of fourth metal layers, wherein the third metal layers and the fourth metal layers are alternately arranged in a direction vertical to the surface of the substrate, the projection pattern of the third metal layers on the substrate is in a closed ring shape, and the projection pattern of the fourth metal layers on the substrate is in a closed ring shape.
Optionally, the protection ring structure further includes: the metal layer structure comprises a plurality of fifth metal layers and a plurality of sixth metal layers, wherein the fifth metal layers are alternately arranged in the direction perpendicular to the surface of the substrate, the sixth metal layers are positioned on the fifth metal layers, any one of the fifth metal layers is mutually separated, any one of the sixth metal layers is mutually separated, the central lines of two adjacent layers of the fifth metal layers are not overlapped, and the central lines of two adjacent layers of the sixth metal layers are not overlapped.
Optionally, the first metal layer and the third metal layer are formed simultaneously; the second metal layer and the fourth metal layer are formed simultaneously.
Optionally, the method further includes: a dielectric structure is formed on a substrate, the guard ring structure being located within the dielectric structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure of the technical scheme of the present invention, the scribe line region has a guard ring structure, the guard ring structure surrounds the device region, and the guard ring structure includes: the second metal structure comprises a plurality of layers of second metal layers, the second metal layers are positioned between two adjacent layers of first metal layers, any layer of the second metal layers are mutually separated, and the central lines of two adjacent layers of the second metal layers are not overlapped. Therefore, the stress of the second metal layers is small, the buffering capacity of the protective ring structure is enhanced, when cracks are expanded when the substrate is cut, the protective ring structure can weaken crack expansion force, the situation that the cracks are expanded to a device area is reduced, and the performance of the chip is improved.
Further, the projection pattern of the first metal layer on the substrate is a closed ring shape, so that the protective ring structure has certain gas-liquid blocking capacity.
Further, the guard ring structure further comprises: the metal layer structure comprises a plurality of third metal layers and a plurality of fourth metal layers, wherein the third metal layers and the fourth metal layers are alternately arranged in a direction perpendicular to the surface of the substrate, the projection pattern of the third metal layers on the substrate is a closed ring, and the projection pattern of the fourth metal layers on the substrate is a closed ring. Therefore, the protective ring structure has better gas-liquid blocking capacity, and the condition that gas and liquid easily permeate from the net structure of the second metal layer when the second metal layer is in the net structure is made up.
Further, the guard ring structure further comprises: the metal layer structure comprises a plurality of fifth metal layers and a plurality of sixth metal layers which are alternately arranged in the direction perpendicular to the surface of the substrate, wherein any one of the fifth metal layers is mutually separated, any one of the sixth metal layers is mutually separated, the central lines of two adjacent layers of the fifth metal layers are not overlapped, and the central lines of two adjacent layers of the sixth metal layers are not overlapped. The fifth metal layer and the sixth metal layer can act together with the second metal layer to weaken crack expansion force, reduce the crack expansion to a device area and improve the performance of the chip.
Drawings
Fig. 1 to 6 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Detailed Description
As described in the background art, the gas-liquid barrier capability and the crack barrier capability of the existing chip seal ring structure have yet to be enhanced.
Specifically, along with semiconductor structure's size is littleer and smaller, the cutting passageway that corresponds is also more and more narrow, and consequently the cutting knife is along cutting the passageway when cutting the wafer, and the distance of cutting knife and chip is also littleer and smaller, and if sealing ring structure fracture barrier capacity around the chip is not enough, the crack that the cutting knife cutting wafer produced is very easy to be diffused to the chip to lead to the electrical property of chip to become invalid.
In order to solve the above problems, the present invention further provides a semiconductor structure and a method for forming the semiconductor structure, where a guard ring structure is provided on a scribe line region, the guard ring structure surrounds the device region, and the guard ring structure includes: the second metal structure comprises a plurality of layers of second metal layers, the second metal layers are positioned between two adjacent layers of first metal layers, any layer of the second metal layers are mutually separated, and the central lines of two adjacent layers of the second metal layers are not overlapped. Therefore, the stress of the second metal layers is small, the buffering capacity of the protective ring structure is enhanced, when cracks are expanded when the substrate is cut, the protective ring structure can weaken crack expansion force, the situation that the cracks are expanded to a device area is reduced, and the performance of the chip is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 5 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 1, a substrate is provided, the substrate including a chip region, the chip region including a device region 200 and a scribe line region 201 surrounding the device region 200.
The device region 200 is used for forming a semiconductor device; the scribe line region 201 is used to divide the device region 200 along the scribe line region 201.
In this embodiment, the substrate is made of silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the multicomponent semiconductor material of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
Referring to fig. 2 to 4, fig. 2 is a top view of fig. 3 and 4, fig. 3 is a schematic cross-sectional view of fig. 2 along a section line BB1 without a dielectric structure 209, fig. 4 is a schematic structural view of fig. 2 along a section line CC1 without the dielectric structure 209, a guard ring structure is formed in a scribe line region 201, the guard ring structure surrounds the device region 200, and the guard ring structure includes: the plurality of layers of first metal layers 202 and second metal structures are overlapped in the direction perpendicular to the substrate surface, the second metal structure at least comprises one layer of second metal layer 203, the second metal layer 203 is positioned between two adjacent layers of first metal layers 202, any one layer of second metal layer 203 is mutually separated, and the central lines of two adjacent layers of second metal layers 203 are not overlapped.
Therefore, the stress of the second metal layers 203 is small, so that the buffering capacity of the protective ring structure is enhanced, when cracks expand during substrate cutting, the protective ring structure can weaken crack expansion force, reduce the situation that the cracks expand to the device region 200, and improve the performance of the chip.
In this embodiment, the second metal structure includes a plurality of second metal layers 203, and the plurality of second metal layers 203 are concentrically distributed around the device region 200 in a direction parallel to the substrate surface.
The number of the first metal layers 202 is multiple, in a direction parallel to the substrate surface, the multiple first metal layers 202 are concentrically distributed with the device region as a center, and the first metal layers 202 and the second metal layers 203 are arranged in an overlapping manner in a direction perpendicular to the substrate surface. In the present embodiment, a first metal layer 202 is schematically shown.
The number of the guard ring structures is plural, and the plurality of guard ring structures are concentrically distributed with the device region 200 as a center.
In this embodiment, a projection pattern of the first metal layer 202 on the substrate is a closed ring shape, and the closed ring shape has a first width. The projection pattern of the first metal layer 203 on the substrate is a closed ring shape, so that the protective ring structure has certain gas-liquid blocking capability.
In this embodiment, the projected pattern of the second metal layer 203 on the substrate forms an interrupted ring shape, and the interrupted ring shape has a second width.
In this embodiment, the first width is greater than the second width.
In another embodiment, the first width is less than the second width.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of fig. 2 along a section line DD1 without the dielectric structure 209.
In this embodiment, the guard ring structure further includes: the metal layer structure comprises a plurality of third metal layers 204 and a plurality of fourth metal layers 205, wherein the third metal layers 204 and the fourth metal layers 205 are alternately arranged in a direction perpendicular to the surface of the substrate, the projection pattern of the third metal layers 204 on the substrate is a closed ring, and the projection pattern of the fourth metal layers 205 on the substrate is a closed ring.
Therefore, the protective ring structure has a good gas-liquid blocking capability, so as to make up for the situation that the gas and liquid easily permeate from the mesh structure of the second metal layer 203 when the second metal layer 203 is in the mesh structure.
The number of the third metal layer 204 and the fourth metal layer 205 may be multiple, and the multiple third metal layers 204 and the multiple fourth metal layers 205 are concentrically distributed around the device region 200.
In other embodiments, the third and fourth metal layers may not be formed.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of fig. 2 with the dielectric structure 209 omitted along the section line EE 1.
In this embodiment, the guard ring structure further includes: a plurality of fifth metal layers 206 and a plurality of sixth metal layers 207 that are located on fifth metal layer 206 of alternate arrangement on the surface direction of perpendicular to substrate, arbitrary layer mutually discrete between the fifth metal layer 205, arbitrary layer mutually discrete between the sixth metal layer 207, the central line of two adjacent fifth metal layers 205 is misaligned, and the central line of two adjacent sixth metal layers 207 is misaligned.
The fifth metal layer 206 and the sixth metal layer 207 can act together with the second metal layer 203 to weaken crack propagation force, reduce the crack propagation to the device region 200, and improve chip performance.
The number of the fifth metal layer 206 and the sixth metal layer 207 may be multiple, and the fifth metal layer 206 and the sixth metal layer 207 are concentrically distributed with the device region 200 as a center.
In other embodiments, the fifth and sixth metal layers may not be formed.
In this embodiment, the first metal layer 202, the third metal layer 204 and the fifth metal layer 206 are formed at the same time; the second metal layer 203, the fourth metal layer 205, and the sixth metal layer 207 are formed simultaneously.
The forming method of the protective ring structure comprises the following steps: forming a dielectric structure 209 on the substrate; a first metal layer 202 and a second metal layer are formed in the dielectric structure 209 in an overlapping manner, a third metal layer 204 and a fourth metal layer 205 are formed in the dielectric structure 209 in an overlapping manner, and a fifth metal layer 206 and a sixth metal layer 207 are formed in the dielectric structure 209 in an overlapping manner.
The materials of the first metal layer 202, the third metal layer 204 and the fifth metal layer 206 comprise metals or metal nitrides; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
The materials of the second metal layer 203, the fourth metal layer 205 and the sixth metal layer 207 comprise metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
The material of the dielectric structure 209 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, with reference to fig. 1 to 6, including:
a substrate including a chip region including a device region 200 and a scribe lane region 201 surrounding the device region 200; a guard ring structure located on the scribe line region 201, the guard ring structure surrounding the device region 200, the guard ring structure comprising: the structure comprises a plurality of first metal layers 202 and a plurality of second metal structures which are overlapped in the direction vertical to the surface of the substrate, wherein the second metal structures at least comprise a second metal layer 203, the second metal layers 203 are positioned between two adjacent first metal layers 202, the second metal layers 203 of any layer are mutually separated, and the central lines of the two adjacent second metal layers 203 are not overlapped.
In this embodiment, the second metal structure includes a plurality of second metal layers 203, and the plurality of second metal layers 203 are concentrically distributed around the device region 200.
In this embodiment, the number of the first metal layers 202 is plural, the plural first metal layers 202 are concentrically distributed with the device region as a center in a direction parallel to the substrate surface, and the first metal layers 202 and the second metal layers 203 are arranged in an overlapping manner in a direction perpendicular to the substrate surface.
In this embodiment, the number of the guard ring structures is multiple, and the guard ring structures are concentrically distributed around the device region 200.
In this embodiment, a projection pattern of the first metal layer 203 on the substrate is a closed ring shape, and the closed ring shape has a first width; the projection pattern of the second metal layer 203 on the substrate forms an interrupted ring shape having a second width.
In this embodiment, the first width is greater than the second width, or the first width is smaller than the second width.
In this embodiment, the guard ring structure further includes: the metal layer structure comprises a plurality of third metal layers 204 and a plurality of fourth metal layers 205, wherein the third metal layers 204 and the fourth metal layers 205 are alternately arranged in a direction perpendicular to the surface of the substrate, the projection pattern of the third metal layers 204 on the substrate is a closed ring shape, and the projection pattern of the fourth metal layers 205 on the substrate is a closed ring shape.
In this embodiment, the guard ring structure further includes: a plurality of layers of fifth metal layer 206 and a plurality of layers of sixth metal layer 207 of alternate arrangement on the surface direction of perpendicular to substrate, arbitrary layer mutually discrete between the fifth metal layer 206, arbitrary layer mutually discrete between the sixth metal layer 207, the central line of two adjacent layers of fifth metal layer 206 is misaligned, and the central line of two adjacent layers of sixth metal layer 207 is misaligned.
In this embodiment, the projection pattern of the fifth metal layer 206 on the substrate forms a discontinuous ring shape, and the projection pattern of the sixth metal layer 207 on the substrate forms a discontinuous ring shape.
In this embodiment, the method further includes: a dielectric structure 209 located on the substrate, the guard ring structure being located within the dielectric structure 209.
In this embodiment, the material of the first metal layer 202 includes a metal or a metal nitride; the material of the second metal layer 203 comprises metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (21)
1. A semiconductor structure, comprising:
a substrate including a chip region, the chip region including a device region and a scribe line region surrounding the device region;
a guard ring structure located on the scribe line region, the guard ring structure surrounding the device region, the guard ring structure comprising: the second metal structure at least comprises a second metal layer, the second metal layer is positioned between two adjacent first metal layers, any one of the second metal layers is mutually separated, and the central lines of two adjacent second metal layers are not overlapped.
2. The semiconductor structure of claim 1, wherein the second metal structure comprises a plurality of second metal layers concentrically arranged about the device region in a direction parallel to a surface of the substrate.
3. The semiconductor structure of claim 2, wherein the number of the first metal layers is plural, the plural first metal layers are concentrically distributed with the device region as a center in a direction parallel to a surface of the substrate, and the first metal layers and the second metal layers are arranged to overlap in a direction perpendicular to the surface of the substrate.
4. The semiconductor structure of claim 1, wherein the number of guard ring structures is multiple, and the multiple guard ring structures are concentrically distributed around the device region.
5. The semiconductor structure of claim 1, wherein a projected pattern of the first metal layer on the substrate is a closed loop shape, the closed loop shape having a first width; the projection pattern of the second metal layer on the substrate forms an interrupted ring shape, and the interrupted ring shape has a second width.
6. The semiconductor structure of claim 5, wherein the first width is greater than the second width or the first width is less than the second width.
7. The semiconductor structure of claim 1, wherein the guard ring structure further comprises: the metal layer structure comprises a plurality of third metal layers and a plurality of fourth metal layers, wherein the third metal layers and the fourth metal layers are alternately arranged in a direction perpendicular to the surface of the substrate, the projection pattern of the third metal layers on the substrate is a closed ring, and the projection pattern of the fourth metal layers on the substrate is a closed ring.
8. The semiconductor structure of claim 1, wherein the guard ring structure further comprises: the metal layer structure comprises a plurality of fifth metal layers and a plurality of sixth metal layers which are alternately arranged in the direction perpendicular to the surface of the substrate, wherein the fifth metal layers are mutually separated, the sixth metal layers are mutually separated, the central lines of two adjacent layers of the fifth metal layers are not overlapped, and the central lines of two adjacent layers of the sixth metal layers are not overlapped.
9. The semiconductor structure of claim 8, wherein a projected pattern of the fifth metal layer on the substrate forms an interrupted ring shape, and a projected pattern of the sixth metal layer on the substrate forms an interrupted ring shape.
10. The semiconductor structure of claim 1, further comprising: a dielectric structure on the substrate, the guard ring structure being located within the dielectric structure.
11. The semiconductor structure of claim 1, wherein a material of the first metal layer comprises a metal or a metal nitride; the material of the second metal layer comprises metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
12. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a chip area, and the chip area comprises a device area and a cutting path area surrounding the device area;
forming a guard ring structure in the scribe line region, the guard ring structure surrounding the device region, the guard ring structure comprising: the second metal structure at least comprises a second metal layer, the second metal layer is positioned between two adjacent first metal layers, any one of the second metal layers is mutually separated, and the central lines of two adjacent second metal layers are not overlapped.
13. The method of forming a semiconductor structure of claim 12, wherein the second metal structure comprises a plurality of second metal layers concentrically arranged about the device region in a direction parallel to a surface of the substrate.
14. The method according to claim 13, wherein the number of the first metal layers is plural, the plural first metal layers are concentrically distributed around the device region in a direction parallel to a surface of the substrate, and the first metal layers and the second metal layers are arranged to overlap in a direction perpendicular to the surface of the substrate.
15. The method of claim 12, wherein the number of guard ring structures is multiple, and the multiple guard ring structures are concentrically distributed around the device region.
16. The method of forming a semiconductor structure of claim 12, wherein a projected pattern of the first metal layer on the substrate is a closed loop shape, the closed loop shape having a first width; the projection pattern of the second metal layer on the substrate forms an interrupted ring shape, and the interrupted ring shape has a second width.
17. The method of forming a semiconductor structure of claim 16, wherein the first width is greater than the second width or the first width is less than the second width.
18. The method of forming a semiconductor structure of claim 12, wherein the guard ring structure further comprises: the metal layer structure comprises a plurality of third metal layers and a plurality of fourth metal layers, wherein the third metal layers and the fourth metal layers are alternately arranged in a direction perpendicular to the surface of the substrate, the projection pattern of the third metal layers on the substrate is a closed ring, and the projection pattern of the fourth metal layers on the substrate is a closed ring.
19. The method of forming a semiconductor structure of claim 12, wherein the guard ring structure further comprises: the metal layer structure comprises a plurality of fifth metal layers and a plurality of sixth metal layers, wherein the fifth metal layers are alternately arranged in the direction perpendicular to the surface of the substrate, the sixth metal layers are positioned on the fifth metal layers, any one of the fifth metal layers is mutually separated, any one of the sixth metal layers is mutually separated, the central lines of two adjacent layers of the fifth metal layers are not overlapped, and the central lines of two adjacent layers of the sixth metal layers are not overlapped.
20. The method of forming a semiconductor structure of claim 18, wherein the first metal layer and the third metal layer are formed simultaneously; the second metal layer and the fourth metal layer are formed simultaneously.
21. The method of forming a semiconductor structure of claim 12, further comprising: and forming a dielectric structure on the substrate, wherein the protective ring structure is positioned in the dielectric structure.
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