CN116581108A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN116581108A CN116581108A CN202310844510.6A CN202310844510A CN116581108A CN 116581108 A CN116581108 A CN 116581108A CN 202310844510 A CN202310844510 A CN 202310844510A CN 116581108 A CN116581108 A CN 116581108A
- Authority
- CN
- China
- Prior art keywords
- groove
- sub
- grooves
- trench
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title description 14
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000004020 conductor Substances 0.000 claims abstract description 31
- 238000005452 bending Methods 0.000 claims description 33
- 238000000059 patterning Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 33
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a chip area and a scribing area arranged around the chip area, the semiconductor device comprises a wafer substrate, a gate wiring and a conductive material, the wafer substrate is positioned on the chip area and the scribing area, the gate wiring is arranged on the wafer substrate positioned on the chip area and extends along a first direction, the wafer substrate is provided with a first groove and a second groove which are positioned on the chip area and filled with the conductive material, and two ends of the first groove and the second groove are connected with adjacent gate wirings and are alternately arranged along the first direction; the first groove and the second groove comprise a first sub-groove and a second sub-groove connected with the first sub-groove, the first sub-groove extends along a second direction, the second direction is perpendicular to the first direction, the second sub-groove of the first groove protrudes towards one face deviating from the second groove, and the second sub-groove of the second groove protrudes towards one face deviating from the second groove. By the arrangement, the warping degree of the wafer can be reduced.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In the semiconductor manufacturing process, the directions of device grooves adopted by semiconductor chips of semiconductor devices are in the same direction, when the area of the chips is large and the grooves reach a certain depth, larger stress is generated between filling materials in the grooves and a wafer substrate, and further stress concentrated in one direction can be brought to the surface of the wafer, so that the wafer is warped, the accurate positions of device contact holes can be directly influenced, and therefore the chip performance and the yield are reduced.
Disclosure of Invention
In view of the above, the present application provides a semiconductor device and a method for manufacturing the same, which can reduce the warpage of a wafer.
The application provides a semiconductor device, which comprises a chip area and a scribing area arranged around the chip area, wherein the semiconductor device comprises a wafer substrate, a gate wire and a conductive material, the wafer substrate is positioned on the chip area and the scribing area, the gate wire is arranged on the wafer substrate in a spacing manner and extends along a first direction, the wafer substrate is provided with a first groove and a second groove which are arranged at intervals, the first groove and the second groove are positioned in the chip area and are filled with the conductive material, two ends of the first groove and the second groove are connected with the adjacent gate wire, and the first groove and the second groove are alternately arranged along the first direction;
the first grooves and the second grooves comprise first sub-grooves and second sub-grooves connected with the first sub-grooves, the first sub-grooves extend along a second direction, the second direction is perpendicular to the first direction, the second sub-grooves of the first grooves face towards the first sub-grooves of the first grooves and face away from the second grooves in a protruding mode, and the second sub-grooves of the second grooves face towards the second grooves and face away from the first grooves in a protruding mode.
In some embodiments, the second sub-slot is connected to the gate trace through the first sub-slot.
In some embodiments, the second sub-groove of the first groove is disposed corresponding to the second sub-groove of the second groove, and the first sub-groove of the first groove is disposed corresponding to the first sub-groove of the second groove.
In some embodiments, the second sub-groove includes a middle groove and bending grooves connected to both ends of the middle groove, and an inclination angle of 45 ° is formed between the middle groove and the bending grooves.
In some embodiments, the second sub-groove comprises a long groove and a short groove, the short groove is connected with the long groove through the first sub-groove, and the length of the long groove is larger than that of the short groove.
In some embodiments, the long groove and the short groove each comprise a middle groove and bending grooves connected with two ends of the middle groove, a 90-degree inclined angle is formed between the middle groove and the bending grooves, and the length of the bending grooves of the long groove is larger than that of the bending grooves of the short groove.
In some embodiments, the first sub-groove and the second sub-groove have a 45 ° inclination therebetween.
In some embodiments, the first groove and the second groove further comprise a third sub-groove connected with the first sub-groove, the third sub-groove is located on one side of the first sub-groove away from the second sub-groove, and the third sub-groove of the first groove is disposed between the third sub-grooves adjacent to the second groove.
In some embodiments, the first sub-groove and the third sub-groove have a 45 ° inclination therebetween.
The application also provides a preparation method of the semiconductor device, which is used for preparing the semiconductor device, wherein the semiconductor device comprises a chip area and a scribing area arranged around the chip area;
providing a wafer substrate, wherein the wafer substrate is positioned in the chip area and the scribing area;
patterning the wafer substrate, namely, carving first grooves and second grooves which are positioned in the chip area and are alternately arranged along a first direction, wherein the first grooves and the second grooves comprise first sub-grooves and second sub-grooves connected with the first sub-grooves, the first sub-grooves extend along a second direction, the second direction is perpendicular to the first direction, the second sub-grooves of the first grooves are arranged in a protruding mode towards one surface of the first sub-grooves of the first grooves, which is away from the second grooves, and the second sub-grooves of the second grooves are arranged in a protruding mode towards one surface of the first sub-grooves of the second grooves, which is away from the first grooves;
filling conductive materials in the first groove and the second groove;
and forming a gate wire positioned in the chip area on the wafer substrate, wherein the gate wire extends along the first direction, and two ends of the first groove and the second groove are connected with the adjacent gate wire.
The application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a chip area and a scribing area arranged around the chip area, the semiconductor device comprises a wafer substrate, a gate wiring and a conductive material, the wafer substrate is positioned on the chip area and the scribing area, the gate wiring is arranged on the wafer substrate positioned on the chip area and extends along a first direction, the wafer substrate is provided with a first groove and a second groove which are positioned on the chip area and filled with the conductive material, and two ends of the first groove and the second groove are connected with adjacent gate wirings and are alternately arranged along the first direction; the first groove and the second groove comprise a first sub-groove and a second sub-groove connected with the first sub-groove, the first sub-groove extends along a second direction, the second direction is perpendicular to the first direction, the second sub-groove of the first groove protrudes towards one face deviating from the second groove, and the second sub-groove of the second groove protrudes towards one face deviating from the second groove. By the arrangement, the warping degree of the wafer can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a first structure of a semiconductor device provided by the present application;
FIG. 2 is an enlarged schematic view of the structure of FIG. 1 at A;
fig. 3 is a schematic cross-sectional structure of the semiconductor device in fig. 1 along BC;
fig. 4 is a schematic view of a second structure of the semiconductor device provided by the present application;
fig. 5 is a schematic view of a third structure of the semiconductor device provided by the present application;
FIG. 6 is an enlarged schematic view of the structure of FIG. 5 at D;
fig. 7 is a schematic view of a fourth structure of the semiconductor device provided by the present application;
FIG. 8 is an enlarged schematic view of the structure of FIG. 7 at E;
fig. 9 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present application;
fig. 10 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present application.
Reference numerals:
10. a semiconductor device; 11. a chip region; 12. a dicing area; 100. a wafer substrate; 110. a first trench; 111. a first sub-tank; 112. a second sub-tank; 113. a middle groove; 114. a bending groove; 115. a long groove; 116. a short groove; 120. a second trench; 130. an inactive trench; 131. a first inactive slot; 132. a second inactive slot; 133. a first subslot; 134. a second subslot; 135. a third sub-slot; 140. a third sub-tank; 150. a P-type doped region; 200. a gate trace; 300. a conductive material; 310. a first layering; 320. a second layering; 400. a first oxide layer; 500. a second oxide layer; 600. an emitter metal.
Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.
The application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a chip area and a scribing area arranged around the chip area, the semiconductor device comprises a wafer substrate, a gate wiring and a conductive material, the wafer substrate is positioned on the chip area and the scribing area, the gate wiring is arranged on the wafer substrate positioned on the chip area and extends along a first direction, the wafer substrate is provided with a first groove and a second groove which are positioned on the chip area and filled with the conductive material, and two ends of the first groove and the second groove are connected with adjacent gate wirings and are alternately arranged along the first direction; the first groove and the second groove comprise a first sub-groove and a second sub-groove connected with the first sub-groove, the first sub-groove extends along a second direction, the second direction is perpendicular to the first direction, the second sub-groove of the first groove protrudes towards one surface of the first sub-groove of the first groove, which faces away from the second groove, and the second sub-groove of the second groove protrudes towards one surface of the first sub-groove of the second groove, which faces away from the second groove.
In the application, the first groove and the second groove are at least formed by grooves extending along two different directions, so that the stress generated by the conductive material in the groove has at least two different extending directions, and the tensile stress and the compressive stress can be simultaneously provided in at least two directions, and the stress generated in the groove can be counteracted, thereby reducing the warping degree of the wafer.
Referring to fig. 1-3, fig. 1 is a schematic view of a first structure of a semiconductor device according to the present application; FIG. 2 is an enlarged schematic view of the structure of FIG. 1 at A; fig. 3 is a schematic cross-sectional structure of the semiconductor device in fig. 1 along BC. The present application provides a semiconductor device 10. The semiconductor device 10 includes a wafer substrate 100, a gate trace 200, a conductive material 300, a first oxide layer 400, a second oxide layer 500, and an emitter metal 600. The semiconductor device 10 includes a chip region 11 and a scribe region 12 disposed around the chip region 11. Specifically, the chip area 11 and the scribe area 12 of the semiconductor device 10 have a plurality, each scribe area 12 is disposed around a chip area 11, the chip area 11 includes an active area and a termination area disposed around the active area, the scribe area 12 is disposed around the termination area, the structure on the scribe area 12 is not conductive, and the wafer is cut at the scribe area 12 when cut.
The wafer substrate 100 is located in the chip area 11 and the scribe area 12, the wafer substrate 100 may be a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate, etc., the wafer substrate 100 has a first trench 110 and a second trench 120 that are disposed at intervals, the first trench 110 and the second trench 120 are located in the chip area 11, the first trench 110 and the second trench 120 are alternately arranged along a first direction y, each of the first trench 110 and the second trench 120 includes a first sub-trench 111 and a second sub-trench 112 connected to the first sub-trench 111, the first sub-trench 111 extends along a second direction x, and the second direction x is perpendicular to the first direction y, that is, the first sub-trench 111 is disposed perpendicular to the gate trace 200. The second sub-groove 112 of the first groove 110 is arranged to protrude towards the first sub-groove 111 of the first groove 110 facing away from the second groove 120, and the second sub-groove 112 of the second groove 120 is arranged to protrude towards the first sub-groove 111 of the second groove 120 facing away from the first groove 110, i.e. a certain included angle is formed between the first sub-groove 111 and the second sub-groove 112. The second sub-grooves 112 of the first groove 110 are disposed corresponding to the second sub-grooves 112 of the second groove 120, the first sub-grooves 111 of the first groove 110 are disposed corresponding to the first sub-grooves 111 of the second groove 120, and the first sub-grooves 111 and the second sub-grooves 112 are alternately disposed along the second direction x. Further, the second sub-groove 112 includes a middle groove 113 and bending grooves 114 connected to both ends of the middle groove 113, and an inclination angle of 45 ° is formed between the middle groove 113 and the bending grooves 114. Specifically, the middle groove 113 extends along the first direction y and is parallel to the first sub groove 111, the extending direction of one bending groove 114 connected with the middle groove 113 is located at one side of the first direction y, the extending direction of the other bending groove 114 connected with the middle groove 113 is located at the other side of the first direction y, that is, the extending directions of two bending grooves 114 connected with the middle groove 113 are different, the included angle α between the middle groove 113 and the bending groove 114 and between the bending groove 114 and the first sub groove 111 is 45 °, that is, the second sub groove 112 is formed by grooves extending along three different directions, that is, the first groove 110 and the second groove 120 are formed by grooves extending along three different directions; in the direction from the gate trace 200 toward the wafer substrate 100, the first sub-groove 111 and the second sub-groove 112 are formed as a positive-negative zigzag groove. The first and second sub-grooves 111 and 112 of the first groove 110 are identical to the first and second sub-grooves 111 and 112 of the second groove 120 in width, length, and height. The second sub-groove 112 is connected to the gate wire 200 through the first sub-groove 111, i.e., the second sub-groove 112 is not directly connected to the gate wire 200. Alternatively, the second sub-groove 112 may be directly connected to the gate wire 200. The wafer substrate 100 has an undoped region, a P-doped region 150 and a plurality of N-doped regions, the P-doped region 150 and the N-doped region are located on one surface of the wafer substrate 100 where the first trench 110 and the second trench 120 are located, the first trench 110 and the second trench 120 penetrate the P-doped region 150 and extend to the undoped region, and the N-doped regions are located on two sides of the first trench 110 and the second trench 120. The first trench 110 and the second trench 120 are effective trenches of the semiconductor device 10.
In another embodiment, the second sub-grooves 112 of the first groove 110 and the second sub-grooves 112 of the second groove 120 are staggered, and the first sub-grooves 111 of the first groove 110 and the first sub-grooves 111 of the second groove 120 are staggered, so that the residual stress of the adjacent first groove 110 or second groove 120 can be further offset, the warpage degree of the wafer is reduced, the accurate position of the device contact hole is prevented from being influenced, and the chip performance and the yield are ensured. .
The conductive material 300 is filled in the first trench 110 and the second trench 120, a first oxide layer 400 is disposed between the conductive material 300 and the walls of the first trench 110 and the second trench 120, the conductive material 300 is composed of a first layer 310 and a second layer 320, a through hole is disposed in the first layer 310, the through hole exposes the first oxide layer 400, the second layer 320 is filled in the through hole, and the conductive material 300 may be polysilicon or other conductive materials 300. The second oxide layer 500 covers the wafer substrate 100, the conductive material 300, and the insulating layer. The reflective electrode is disposed on the second oxide layer 500.
The gate wires 200 are disposed on the wafer substrate 100 at intervals and extend along the first direction y, the gate wires 200 are located in the chip region 11, and two ends of the first trench 110 and the second trench 120 are connected to adjacent gate wires 200. Specifically, the gate wire 200 is located on the second oxide layer 500 and is spaced from the emitter metal 600; the projection of the gate trace 200 does not overlap with the projections of the first trench 110 and the second trench 120 in the direction of the emitter metal 600 toward the wafer substrate 100.
In the prior art, the directions of the device grooves adopted by the semiconductor chips of the semiconductor devices are in the same direction, when the areas of the chips are large and the grooves reach a certain depth, larger stress is generated between the filling materials in the grooves and the wafer substrate, and then the stress concentrated in one direction can be brought to the surface of the wafer, so that the wafer warpage is caused, the accurate positions of the device contact holes can be directly influenced, and therefore, the chip performance and the yield are reduced. In the present application, the extending directions of the first sub-groove 111 and the second sub-groove 112 are set to be inconsistent, that is, a certain angle is formed between the first sub-groove 111 and the second sub-groove 112, so that the stress generated by the conductive material 300 in the groove has two different extending directions, and the two directions can provide tensile stress and compressive stress at the same time, so that the stress generated in the groove can offset each other, thereby reducing the warpage degree of the wafer, and meanwhile, the process cost does not need to be increased.
In the present application, the second sub-groove 112 is configured by grooves extending along three different directions, that is, the first groove 110 and the second groove 120 are configured by grooves extending along three different directions, so that the stress generated by the conductive material 300 in the groove has three different extending directions, and the three directions can provide tensile stress and compressive stress at the same time, so that the stress generated in the groove can offset each other, thereby reducing the warpage degree of the wafer, and meanwhile, without increasing the process cost.
In the present application, by providing the first trenches 110 and the second trenches 120 alternately arranged in the chip area 11, after the stress generated in the first trenches 110 and the second trenches 120 is offset once by the own first sub-trenches 111 and the third direction offset stress in the second sub-trenches 112, the adjacent first trenches 110 or second trenches 120 are also formed by three trenches with different extending directions, so that the stress generated in the adjacent first trenches 110 or second trenches 120 can be offset twice, thereby further offset the residual stress, further reducing the warpage degree of the wafer, further avoiding affecting the accurate position of the device contact hole, and further ensuring the chip performance and yield.
In the application, the included angle alpha between the middle groove 113 and the bending groove 114 is 45 degrees, so that the stress generated in the groove can be counteracted, and the warping degree of the wafer is reduced.
In the present application, the first sub-groove 111 and the second sub-groove 112 of the first trench 110 are correspondingly arranged with the second sub-groove 112 of the second trench 120, and the first sub-groove 111 of the first trench 110 is correspondingly arranged with the first sub-groove 111 of the second trench 120, so that the adjacent first trench 110 or second trench 120 can further offset the residual stress, thereby reducing the warpage degree of the wafer, avoiding affecting the accurate position of the device contact hole, and further ensuring the chip performance and yield.
In the present application, the widths, lengths and heights of the first sub-groove 111 and the second sub-groove 112 of the first trench 110 and the first sub-groove 111 and the second sub-groove 112 of the second trench 120 are set to be the same, so that the stress generated in the first trench 110 is equal to the stress generated in the second trench 120, thereby further improving the effect of stress offset, further reducing the warpage degree of the wafer, further avoiding influencing the accurate position of the device contact hole, and further ensuring the chip performance and yield.
It should be noted that, part of the structure in the present application may be removed as needed.
Referring to fig. 4, fig. 4 is a schematic diagram of a second structure of the semiconductor device according to the present application. It should be noted that the second structure is different from the first structure in that:
the semiconductor device 10 further includes an inactive trench 130 filled with a conductive material 300, the inactive trench 130 being disposed between the first trench 110 and the second trench 120, and the inactive trench 130 being unconnected to the gate trace 200, i.e., the inactive trench 130 being non-conductive. The inactive groove 130 includes a first inactive groove 131 and a second inactive groove 132 connected thereto, the first inactive groove 131 extending in the second direction x; the second ineffective slot 132 comprises a first sub-slot 133, a second sub-slot 134 and a third sub-slot 135, wherein two ends of the second sub-slot 134 are connected with the first sub-slot 133, and the second sub-slot 134 extends along the second direction x and is arranged in parallel with the middle slot 113, namely, the second sub-slot 134 is arranged corresponding to the middle slot 113; one end of the first sub-groove 133 facing away from the second sub-groove 134 is connected with the third sub-groove 135, and the extending direction of the first sub-groove 133 is the same as the extending direction of the bending groove 114 and is parallel to the bending groove 114, i.e. the first sub-groove 133 is correspondingly arranged with the bending groove 114; one end of the third sub-groove 135 facing away from the first sub-groove 133 is connected with the first ineffective groove 131, and the extending direction of the third sub-groove 135 is perpendicular to the extending direction of the first sub-groove 111; i.e., from the direction of the gate trace 200 toward the wafer substrate 100, the second trench 120 is located within the area surrounded by the second sub-trench 112. The ratio of the inactive trench 130 to the active trench is 1:1. By arranging the ineffective trench 130 which is not connected with the gate wire 200 in the chip area 11, the film layer in the ineffective trench 130 is not conductive, only the film layer in the effective trench is conductive, so that the current density of the chip can be reduced, and the circuit capacity of the device can be improved.
In addition, for the sake of clarity, the structures of the second oxide layer 500 and the emitter metal 600 are not shown in fig. 4, but are not meant to be omitted, and the other structures, such as the first structure, are not described herein.
Referring to fig. 5 and 6, fig. 5 is a schematic view of a third structure of the semiconductor device according to the present application; fig. 6 is an enlarged schematic view of the structure at D in fig. 5. The third structure is different from the first structure in that:
the second sub-groove 112 includes a long groove 115 and a short groove 116, the short groove 116 is connected with the long groove 115 through the first sub-groove 111, the length H of the long groove 115 is greater than the length H of the short groove 116, and the length H of the long groove 115 and the length H of the short groove 116 are respectively regarded as an integral comparison. Further, each of the long groove 115 and the short groove 116 includes a middle groove 113 and bending grooves 114 connected to both ends of the middle groove 113, an angle α between the middle groove 113 and the bending grooves 114 is 90 °, the middle groove 113 extends along the second direction x, the bending grooves 114 extend along the first direction y, and a length R of the bending grooves 114 of the long groove 115 is greater than a length R of the bending grooves 114 of the short groove 116.
In the present application, the extension directions of the middle groove 113 and the bending groove 114 are not set in the same direction, and the length R of the bending groove 114 of the long groove 115 is set to be greater than the length R of the bending groove 114 of the short groove 116, so that the stress generated in the bending groove 114 extending along the first direction y is not on the same horizontal line, thereby the stress is not concentrated, and the warping degree of the wafer is reduced.
In one embodiment, a first trench 110 and a second trench 120 form a repeating trench unit, and the long groove 115 of one repeating trench unit is disposed corresponding to the short groove 116 of an adjacent repeating trench unit, so that the stresses generated in the trenches can be further offset, and the warpage of the wafer is reduced.
In addition, for the sake of clarity, the structures of the second oxide layer 500 and the emitter metal 600 are not shown in fig. 5, but are not meant to be omitted, and the other structures, such as the first structure, are not described herein.
Referring to fig. 7 and 8, fig. 7 is a schematic view of a fourth structure of a semiconductor device according to the present application; fig. 8 is an enlarged schematic view of the structure at E in fig. 7. The fourth structure is different from the first structure in that:
the first groove 110 and the second groove 120 further comprise a third sub-groove 140 connected with the first sub-groove 111, the third sub-groove 140 is located at one side of the first sub-groove 111 away from the second sub-groove 112, and the third sub-groove 140 of the first groove 110 is disposed between the adjacent third sub-grooves 140 of the second groove 120. The angle α between the first sub-groove 111 and the third sub-groove 140 and between the first sub-groove 111 and the second sub-groove 112 is 45 °. The third sub-groove 140 and the second sub-groove 112 are symmetrically disposed with respect to the first sub-groove 111, and the planar shapes of the first trench 110 and the second trench 120 are fishbone-shaped in the direction from the gate trace 200 toward the wafer substrate 100.
In addition, for the sake of clarity, the structures of the second oxide layer 500 and the emitter metal 600 are not shown in fig. 7, but are not meant to be omitted, and the other structures, such as the first structure, are not described herein.
In the present application, the first groove 110 and the second groove 120 are formed by the first sub-groove 111, the second sub-groove 112 and the third sub-groove 140, and the third sub-groove 140 of the first groove 110 is disposed between the adjacent third sub-grooves 140 of the second groove 120, and the included angle α between the first sub-groove 111 and the third sub-groove 140 and between the first sub-groove 111 and the second sub-groove 112 is set to be 45 ° so that the stresses generated in the first sub-groove 111, the second sub-groove 112 and the third sub-groove 140 are in three different directions, thereby enabling the stresses not to be concentrated and further reducing the warpage degree of the wafer.
Referring to fig. 1, 3, 9 and 10, fig. 9 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present application; fig. 10 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present application. The application also provides a preparation method of the semiconductor device 10, which is used for preparing the semiconductor device 10 provided by the application, wherein the semiconductor device 10 comprises a chip region 11 and a scribing region 12 arranged around the chip region 11.
S11, providing a wafer substrate, wherein the wafer substrate is positioned in the chip area and the scribing area.
S12, carrying out patterning treatment on the wafer substrate, and etching first grooves and second grooves which are positioned in the chip area and are alternately arranged along a first direction, wherein the first grooves and the second grooves comprise first sub-grooves and second sub-grooves connected with the first sub-grooves, the first sub-grooves extend along a second direction, the second direction is perpendicular to the first direction, the second sub-grooves of the first grooves are arranged in a protruding mode towards one surface of the first sub-grooves of the first grooves, which is away from the second grooves, and the second sub-grooves of the second grooves are arranged in a protruding mode towards one surface of the first sub-grooves of the second grooves, which is away from the first grooves.
Specifically, field oxide is grown on the wafer substrate 100; then, setting photoresist on the field oxide, and exposing and developing by adopting a photoetching plate to enable the field oxide and the photoresist to form a photoetching pattern, wherein the photoetching pattern is positioned in the chip area 11, and the scribing area 12 is used for limiting the edge of each chip area 11; then, dry etching is performed using the photoresist as a mask plate to form the wafer substrate 100, wherein the reaction gas passes through the pattern in the photolithography pattern to contact the wafer substrate 100 to form the first trench 110 and the second trench 120.
In one embodiment, after step S12, the method further includes:
a first oxide layer 400 is grown in the first trench 110 and the second trench 120 by dry oxygen growth, and covers the inner walls of the first trench 110 and the second trench 120 to perform an insulating function.
And S13, filling conductive materials in the first groove and the second groove.
Specifically, the first trenches 110 and the second trenches 120 are filled with the first layered layer 310, and the back etching is completed, wherein the thickness d of the first layered layer 310 is smaller than 1/2 of the widths w of the first trenches 110 and the second trenches 120, so that the first trenches 110 and the second trenches 120 are incompletely filled, and the first layered layer 310 has a through hole exposing the first oxide layer 400. This has the advantage that the conductive material 300 on both sides of the first trench 110 and the second trench 120 do not interact during the back etching process after the first layer 310 is filled, and the film stress of the first layer 310 can be released.
After the first trenches 110 and the second trenches 120 have deposited the first layer 310, a second layer 320 is deposited over the first layer 310 in the first trenches 110 and the second trenches 120, the second layer 320 is filled into the via holes and contacts the first layer 310 until the via holes are completely filled, and the first layer 310 and the second layer 320 form the conductive material 300. This has the advantage that the gaps left in the first trenches 110 and the second trenches 120 are small, i.e. the aperture of the through holes is small, when the second conductive material 300 is deposited, so that the second conductive material 300 is less filled into the first trenches 110 and the second trenches 120, the interlayer stress is small, and the tensile force of the conductive material 300 on the trenches is small in the subsequent other thermal processes, so as to reduce the warpage of the wafer without increasing the cost.
S14, forming a gate wire located in the chip area on the wafer substrate, wherein the gate wire extends along a first direction, and two ends of the first groove and the second groove are connected with adjacent gate wires.
The application provides a semiconductor device 10 and a method for manufacturing the same, wherein the first groove 110 and the second groove 120 are formed by grooves extending along at least two different directions, so that the stress generated by the conductive material 300 in the groove has at least two different extending directions, and at least two directions can provide tensile stress and compressive stress at the same time, so that the stress generated in the groove can offset each other, thereby reducing the warping degree of a wafer, and meanwhile, the process cost is not increased.
The foregoing embodiments of the present application are not limited to the above embodiments, but are intended to be included within the scope of the present application as defined by the appended claims and their equivalents.
Claims (10)
1. The semiconductor device is characterized by comprising a chip area and a scribing area arranged around the chip area, wherein the semiconductor device comprises a wafer substrate, a gate wire and a conductive material, the wafer substrate is positioned on the chip area and the scribing area, the gate wire is arranged on the wafer substrate in a spacing mode and extends along a first direction, the wafer substrate is provided with a first groove and a second groove which are arranged at intervals, the first groove and the second groove are positioned in the chip area and are filled with the conductive material, two ends of the first groove and the second groove are connected with the adjacent gate wire, and the first groove and the second groove are alternately arranged along the first direction;
the first grooves and the second grooves comprise first sub-grooves and second sub-grooves connected with the first sub-grooves, the first sub-grooves extend along a second direction, the second direction is perpendicular to the first direction, the second sub-grooves of the first grooves face towards the first sub-grooves of the first grooves and face away from the second grooves in a protruding mode, and the second sub-grooves of the second grooves face towards the second grooves and face away from the first grooves in a protruding mode.
2. The semiconductor device according to claim 1, wherein the second sub-groove is connected to the gate wiring through the first sub-groove.
3. The semiconductor device according to claim 1, wherein the second sub-groove of the first trench is provided corresponding to the second sub-groove of the second trench, and wherein the first sub-groove of the first trench is provided corresponding to the first sub-groove of the second trench.
4. A semiconductor device according to any one of claims 1 to 3, wherein the second sub-groove includes a middle groove and bending grooves connected to both ends of the middle groove, the middle groove having an inclination angle of 45 ° with the bending grooves.
5. A semiconductor device according to any one of claims 1 to 3, wherein the second sub-groove includes a long groove and a short groove, the short groove and the long groove are connected by the first sub-groove, and a length of the long groove is larger than a length of the short groove.
6. The semiconductor device according to claim 5, wherein the long groove and the short groove each include a middle groove and bending grooves connected to both ends of the middle groove, the middle groove and the bending grooves have an inclination angle of 90 degrees therebetween, and a length of the bending grooves of the long groove is greater than a length of the bending grooves of the short groove.
7. The semiconductor device of claim 1, wherein the first sub-groove and the second sub-groove have a 45 ° inclination therebetween.
8. The semiconductor device of claim 7, wherein the first trench and the second trench further comprise a third sub-trench connected to the first sub-trench, the third sub-trench being located on a side of the first sub-trench facing away from the second sub-trench, the third sub-trench of the first trench being disposed between the third sub-trenches adjacent to the second trench.
9. The semiconductor device of claim 8, wherein the first sub-groove and the third sub-groove have a 45 ° inclination therebetween.
10. A method of manufacturing a semiconductor device, characterized in that it is used for manufacturing the semiconductor device according to any one of claims 1 to 9, the semiconductor device comprising a chip region and a scribe region provided around the chip region;
providing a wafer substrate, wherein the wafer substrate is positioned in the chip area and the scribing area;
patterning the wafer substrate, namely, carving first grooves and second grooves which are positioned in the chip area and are alternately arranged along a first direction, wherein the first grooves and the second grooves comprise first sub-grooves and second sub-grooves connected with the first sub-grooves, the first sub-grooves extend along a second direction, the second direction is perpendicular to the first direction, the second sub-grooves of the first grooves are arranged in a protruding mode towards one surface of the first sub-grooves of the first grooves, which faces away from the second grooves, and the second sub-grooves of the second grooves are arranged in a protruding mode towards one surface of the first sub-grooves of the second grooves, which faces away from the first grooves;
filling conductive materials in the first groove and the second groove;
and forming a gate wire positioned in the chip area on the wafer substrate, wherein the gate wire extends along the first direction, and two ends of the first groove and the second groove are connected with the adjacent gate wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310844510.6A CN116581108B (en) | 2023-07-11 | 2023-07-11 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310844510.6A CN116581108B (en) | 2023-07-11 | 2023-07-11 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116581108A true CN116581108A (en) | 2023-08-11 |
| CN116581108B CN116581108B (en) | 2024-01-09 |
Family
ID=87536284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310844510.6A Active CN116581108B (en) | 2023-07-11 | 2023-07-11 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116581108B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332270A (en) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| US20070040213A1 (en) * | 2003-11-12 | 2007-02-22 | Koji Hotta | Trench gate field effect devices |
| CN105762147A (en) * | 2016-04-14 | 2016-07-13 | 株洲中车时代电气股份有限公司 | Semiconductor power device layout |
| CN115621302A (en) * | 2022-10-31 | 2023-01-17 | 上海功成半导体科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN115954380A (en) * | 2022-12-07 | 2023-04-11 | 上海积塔半导体有限公司 | Cell structure of insulated gate bipolar transistor and insulated gate bipolar transistor |
-
2023
- 2023-07-11 CN CN202310844510.6A patent/CN116581108B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332270A (en) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| US20070040213A1 (en) * | 2003-11-12 | 2007-02-22 | Koji Hotta | Trench gate field effect devices |
| CN105762147A (en) * | 2016-04-14 | 2016-07-13 | 株洲中车时代电气股份有限公司 | Semiconductor power device layout |
| CN115621302A (en) * | 2022-10-31 | 2023-01-17 | 上海功成半导体科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN115954380A (en) * | 2022-12-07 | 2023-04-11 | 上海积塔半导体有限公司 | Cell structure of insulated gate bipolar transistor and insulated gate bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116581108B (en) | 2024-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100545863B1 (en) | Semiconductor device having a fin structure and method of manufacturing the same | |
| KR100792384B1 (en) | Five channel fin transistor device and method of manufacturing the same | |
| KR20130004673A (en) | Dram device and method of manufacturing the same | |
| KR101353343B1 (en) | Semiconductor Devices Having Storage Nodes Respectively Spaced away To Different Distances From One Side Of Bit Line Pattern On Active and Methods Of Forming The Same | |
| KR20020017041A (en) | Method of forming a contact structure in semiconductor device | |
| CN116581108B (en) | Semiconductor device and method for manufacturing the same | |
| KR100819559B1 (en) | Semiconductor integrated circuit devices having gate pattern suitable for physically spacing electrical nodes from each other on semiconductor substrate with the gate pattern diposed between the electrical nodes and methods of forming the same | |
| KR101543430B1 (en) | Method for fabricating semiconductor devices | |
| KR100790571B1 (en) | Transistor and the method for manufacturing the same | |
| KR20130004680A (en) | Method of manufacturing a dram device | |
| JPS59113669A (en) | Semiconductor element | |
| CN116581107B (en) | Semiconductor device and method for manufacturing the same | |
| KR100468699B1 (en) | Overlay Keys for Overlap Measurement in Semiconductor Manufacturing Processes | |
| KR100344835B1 (en) | Semiconductor Device and Method for the Same | |
| KR101196462B1 (en) | Semiconductor device and method for fabricating the same | |
| JP2017028056A (en) | Semiconductor device manufacturing method | |
| KR100590201B1 (en) | Method of fabricating self-aligned contact | |
| US20140036565A1 (en) | Memory device and method of manufacturing memory structure | |
| CN111435680B (en) | Stepped element and method for manufacturing the same | |
| US20230395684A1 (en) | Semiconductor device | |
| KR101001152B1 (en) | Method for fabrication of semiconductor device | |
| JP2003258049A (en) | Method for manufacturing semiconductor device | |
| KR100691131B1 (en) | Semiconductor device and manufacturing method thereof | |
| US20220262731A1 (en) | Semiconductor devices | |
| KR20070107336A (en) | Method of fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |