KR100590201B1 - Method of fabricating self-aligned contact - Google Patents

Method of fabricating self-aligned contact Download PDF

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KR100590201B1
KR100590201B1 KR1019990003397A KR19990003397A KR100590201B1 KR 100590201 B1 KR100590201 B1 KR 100590201B1 KR 1019990003397 A KR1019990003397 A KR 1019990003397A KR 19990003397 A KR19990003397 A KR 19990003397A KR 100590201 B1 KR100590201 B1 KR 100590201B1
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semiconductor substrate
pad
contact
region
contact holes
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KR20000054995A (en
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전광열
김동현
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 자기정렬 콘택 패드(self-aligned contact pad)의 제조 방법에 관한 것으로, 게이트 구조물(gate structure)이 형성된 반도체 기판 전면에 층간절연막이 증착 된다. 인접한 게이트 구조물 사이의 영역의 층간절연막 및 층간절연막 하부의 반도체 기판의 일부 두께가 식각 되어 패드 콘택홀(pad contact hole)이 형성된다. 이와 같이, 패드 콘택홀의 하부가 반도체 기판의 상부 표면에 대해 리세스(recess) 되도록 형성함으로써, 콘택 패드와 접합 영역(junction region)의 접촉 면적(contact area)을 증가시킬 수 있고, 따라서 콘택 패드의 계면 저항을 줄일 수 있다. 이때, 실리콘 RF 표면 처리(surface treatment)를 통해 리세스된 부위의 반도체 기판의 손상(damage)을 제거할 수 있고, 이온주입 공정을 통해 패드 콘택홀의 하부에 단계적인 접합 영역(gradual junction region)을 형성함으로써 누설 전류(leakage current) 발생을 억제할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a self-aligned contact pad, wherein an interlayer insulating film is deposited on an entire surface of a semiconductor substrate on which a gate structure is formed. Some thicknesses of the interlayer insulating film in the region between the adjacent gate structures and the semiconductor substrate under the interlayer insulating film are etched to form a pad contact hole. As such, by forming the bottom of the pad contact hole to be recessed with respect to the top surface of the semiconductor substrate, it is possible to increase the contact area of the contact pad and the junction region, thereby reducing the contact pad. The interface resistance can be reduced. At this time, damage to the semiconductor substrate of the recessed region may be removed through silicon RF surface treatment, and a gradual junction region may be formed under the pad contact hole through an ion implantation process. By forming, leakage current can be suppressed.

Description

자기정렬 콘택 패드의 제조 방법{METHOD OF FABRICATING SELF-ALIGNED CONTACT}Manufacturing method of self-aligned contact pad {METHOD OF FABRICATING SELF-ALIGNED CONTACT}

도 1은 본 발명의 실시예에 따른 DRAM 셀의 레이아웃을 보여주는 도면; 1 shows a layout of a DRAM cell according to an embodiment of the invention;

도 2a 내지 도 2d는 도 1의 A-A' 라인(line)을 따라 절개한 단면도로서, 본 발명의 실시예에 따른 자기정렬 콘택 패드의 제조 방법의 공정들을 순차적으로 보여주는 단면도. 2A through 2D are cross-sectional views taken along the line AA ′ of FIG. 1, and are cross-sectional views sequentially illustrating processes of a method of manufacturing a self-aligned contact pad according to an exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

100 : 반도체 기판101 : 활성 영역100 semiconductor substrate 101 active region

102 : 소자격리막104 : 게이트 전극막 패턴102 element isolation film 104 gate electrode film pattern

105 : 게이트 마스크막 패턴106 : 제 1 접합 영역105: gate mask film pattern 106: first junction region

108 : 게이트 스페이서110 : 층간절연막108: gate spacer 110: interlayer insulating film

110a - 110c : 패드 콘택홀112 : 제 2 접합 영역110a-110c: pad contact hole 112: second junction region

114 : 제 3 접합 영역120a - 120c : 콘택 패드114: third bonding region 120a-120c: contact pad

본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로는 자 기정렬 콘택 패드(self-aligned contact pad)의 제조 방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a self-aligned contact pad.

DRAM이 고집적화 됨에 따라, 종래 자기정렬 콘택 패드의 제조 방법에 있어서 콘택 패드의 하부면과 반도체 기판의 접촉 면적(contact area)의 한계로 인하여 콘택 내의 계면 저항(interface resistance)이 커지는 문제점이 발생된다. 이로 인해, DRAM 셀(cell)의 기능(function)이 저하되는 문제점이 발생된다. As DRAMs are highly integrated, there is a problem in that an interface resistance in a contact increases due to a limitation of a contact area of a bottom surface of a contact pad and a semiconductor substrate in a conventional method of manufacturing a self-aligned contact pad. This causes a problem that the function of the DRAM cell is degraded.

이에 따라, 콘택 패드와 반도체 기판의 계면 저항을 줄이기 위해 다방면의 기술적인 노력이 진행 중에 있으며, 접촉 면적을 증가시키는 것이 상기 계면 저항을 줄이기 위한 가장 효과적인 방법으로 여겨지고 있다. 그러나, 종래 기술에 있어서 접촉 면적의 증가는 디자인 룰(design rule)의 스케일다운(scale down)이라는 과제와 상반되는 것으로, 이에 대한 문제 해결이 요구된다. Accordingly, various technical efforts are underway to reduce the interface resistance between the contact pad and the semiconductor substrate, and increasing the contact area is considered the most effective method for reducing the interface resistance. However, the increase in the contact area in the prior art is contrary to the problem of scale down of the design rule, which requires a solution to the problem.

본 발명은 상술한 제반 문제점을 해결하기 위해 제안된 것으로서, 디자인 룰을 스케일 다운시키면서도 콘택 패드와 반도체 기판의 충분한 접촉 면적을 확보할 수 있고, 이로써 콘택 패드의 계면 저항을 줄일 수 있는 자기정렬 콘택 패드의 제조 방법을 제공함에 그 목적이 있다. SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and it is possible to secure a sufficient contact area between a contact pad and a semiconductor substrate while scaling down design rules, thereby reducing the interface resistance of the contact pad. Its purpose is to provide a method for producing the same.

(구성)(Configuration)

상술한 목적을 달성하기 위한 본 발명에 의하면, 자기정렬 콘택 패드의 제조 방법은, 반도체 기판 상에 형성된 적어도 두 개 이상의 도전 구조물과, 상기 도전 구조물은 도전막 패턴과, 도전막 패턴을 에워싸도록 형성된 질화막을 포함하고, 인 접한 도전 구조물 사이의 영역의 반도체 기판과 전기적으로 접속되도록 형성된 콘택 패드를 포함하는 자기정렬 콘택 패드의 제조 방법에 있어서, 상기 콘택 패드는 상기 도전 구조물을 포함하여 반도체 기판 전면에 절연막을 증착 하는 단계; 상기 인접한 도전 구조물 사이의 영역의 상기 절연막을 식각 하여 패드 콘택홀을 형성하되, 절연막 하부의 반도체 기판의 일부를 더 식각 하여 패드 콘택홀의 하부면이 반도체 기판의 상부 표면에 대해 리세스 되도록 형성하는 단계; 상기 패드 콘택홀이 채워지도록 절연막 상에 도전막을 증착 하는 단계; 및 상기 도전막을 평탄화 식각 하여 상기 콘택 패드를 형성하는 단계를 포함한다. According to the present invention for achieving the above object, a method of manufacturing a self-aligned contact pad, at least two conductive structures formed on a semiconductor substrate, the conductive structure to surround the conductive film pattern, the conductive film pattern A method of manufacturing a self-aligned contact pad including a formed nitride film, the contact pad including a contact pad formed to be electrically connected to a semiconductor substrate in an area between adjacent conductive structures. Depositing an insulating film on the substrate; Etching the insulating film in the region between the adjacent conductive structures to form a pad contact hole, and further etching a portion of the semiconductor substrate under the insulating film so that the bottom surface of the pad contact hole is recessed with respect to the upper surface of the semiconductor substrate ; Depositing a conductive film on an insulating film to fill the pad contact hole; And planarizing etching the conductive layer to form the contact pads.

(작용)(Action)

도 2d를 참조하면, 본 발명의 실시예에 따른 신규한 자기정렬 콘택 패드의 제조 방법은, 패드 콘택홀의 하부가 반도체 기판의 상부 표면에 대해 리세스(recess) 되도록 형성된다. 이때, 패드 콘택홀의 하부의 반도체 기판의 표면에 대해 실리콘 RF 표면 처리를 수행하여 반도체 기판 식각시 발생된 손상이 치유되도록 한다. 그리고, 패드 콘택홀의 하부에 불순물 이온(impurity ion)을 주입하여 단계적인 접합 영역(gradual junction region)이 형성되도록 하여 누설 전류 발생을 억제한다. 이로써, 콘택 패드와 접합 영역의 접촉 면적을 증가시킬 수 있고, 따라서 콘택 패드의 계면 저항을 줄일 수 있다. Referring to FIG. 2D, the novel self-aligned contact pad manufacturing method according to the embodiment of the present invention is formed such that the lower portion of the pad contact hole is recessed with respect to the upper surface of the semiconductor substrate. At this time, the silicon RF surface treatment is performed on the surface of the semiconductor substrate under the pad contact hole so that the damage generated during the etching of the semiconductor substrate is healed. In addition, impurity ions are implanted into the bottom of the pad contact hole so that a gradual junction region is formed to suppress leakage current. As a result, the contact area between the contact pad and the junction region can be increased, thereby reducing the interface resistance of the contact pad.

(실시예)(Example)

이하, 도 1 및 도 2를 참조하여 본 발명의 실시예를 상세히 설명한다. Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 and 2.

도 1은 본 발명의 실시예에 따른 DRAM 셀의 레이아웃(layout)을 보여주는 도 면이다. 1 is a diagram illustrating a layout of a DRAM cell according to an embodiment of the present invention.

도 1을 참조하면, 본 발명의 실시예에 따른 DRAM 셀의 레이아웃은, 활성 영역(101)과, 상기 활성 영역(101)을 지나도록 형성된 복수의 워드 라인(wordline)(WL)을 포함한다. 상기 활성 영역(101)은 일자형일 수 있고, 도시된 바와 같이 'T'자 형일 수도 있다. Referring to FIG. 1, a layout of a DRAM cell according to an embodiment of the present invention includes an active region 101 and a plurality of wordlines WL formed to pass through the active region 101. The active region 101 may be straight or may be 'T' shaped as shown.

그리고, 상기 레이아웃은 상기 워드 라인(WL) 사이의 활성 영역(101)과 오버랩 되도록 형성된 자기정렬 콘택 패드(120a - 120c)를 포함한다. The layout includes self-aligning contact pads 120a-120c formed to overlap the active region 101 between the word lines WL.

이때, 상기 콘택 패드(120a - 120c)는 패드 콘택홀(110a - 110c)을 통해 반도체 기판과 전기적으로 접속되도록 형성되는데, 상기 패드 콘택홀(110a - 110c)은 레이아웃 상에서 보여지는 표면적보다 더 넓은 표면적을 갖도록 형성되어 있다. In this case, the contact pads 120a-120c are formed to be electrically connected to the semiconductor substrate through the pad contact holes 110a-110c. The pad contact holes 110a-110c have a larger surface area than the surface area shown on the layout. It is formed to have.

이에 대한 상세한 설명은 도 2에 도시된 도면들을 참조하여 설명한다. Detailed description thereof will be described with reference to the drawings illustrated in FIG. 2.

도 2a 내지 도 2d는 도 1의 A-A' 라인을 따라 절개한 단면도로서, 본 발명의 실시예에 따른 자기정렬 콘택 패드의 제조 방법의 공정들을 순차적으로 보여주는 단면도이다. 2A through 2D are cross-sectional views taken along the line AA ′ of FIG. 1, and are cross-sectional views sequentially illustrating processes of a method of manufacturing a self-aligned contact pad according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 본 발명의 실시예에 따른 DRAM 셀의 자기정렬 콘택 패드 형성 방법은 먼저, p형 반도체 기판(100) 상에 활성 영역(active region)(101)과 비활성 영역(inactive region)을 정의하기 위해 소자격리막(device isolation layer)(102)이 형성된다. Referring to FIG. 2A, a method of forming a self-aligned contact pad of a DRAM cell according to an embodiment of the present invention, first, an active region 101 and an inactive region on a p-type semiconductor substrate 100. In order to define the device isolation layer (device isolation layer) 102 is formed.

여기서, 상기 활성 영역(101)은 레이아웃 상에서 일자형 또는 'T'자형으로 형성된다. 그리고, 상기 소자격리막(102)은 얕은 트렌치 격리(shallow trench isolation) 형성 방법으로 형성된다. 이때, 상기 소자격리막(102)은 후속 패드 콘택홀(110a - 110b)의 리세스(recess)양을 고려하여 소자 격리의 브레이크다운 전압(breakdown voltage)이 취약해지지 않도록 충분히 깊게 형성되도록 한다. Here, the active region 101 is formed in a straight or 'T' shape on the layout. In addition, the device isolation layer 102 is formed by a method of forming shallow trench isolation. In this case, the device isolation layer 102 is formed deep enough so that the breakdown voltage of device isolation is not weakened in consideration of the recess amount of the subsequent pad contact holes 110a-110b.

도 2b에 있어서, 상기 활성 영역(101) 및 비활성 영역을 지나도록 워드 라인이 형성된다. 상기 워드 라인은 게이트 전극막 패턴(gate electrode layer pattern)(104)과 게이트 마스크막 패턴(gate mask layer pattern)(105)이 차례로 적층된 형태의 게이트 스택(gate stack)이 형성된 후, 상기 게이트 스택의 양측벽에 게이트 스페이서(gate spacer)(108)가 형성됨으로써 완성된다. In FIG. 2B, a word line is formed to pass through the active region 101 and the inactive region. The word line is formed after a gate stack in which a gate electrode layer pattern 104 and a gate mask layer pattern 105 are sequentially stacked, and then the gate stack. This is completed by forming gate spacers 108 on both sidewalls of the gate spacers 108.

상기 게이트 마스크막 패턴(105) 및 게이트 스페이서(108)는 자기정렬 콘택 패드를 형성하기 위해 즉, 후속 층간절연막 식각 공정시 게이트 마스크막 패턴(105) 및 게이트 스페이서(108)가 식각 정지층(etch stopping layer)으로 작용하도록 일반적으로 질화막(nitride)으로 형성된다. The gate mask layer pattern 105 and the gate spacer 108 may form a self-aligned contact pad, that is, the gate mask layer pattern 105 and the gate spacer 108 may be etched away during a subsequent interlayer insulating layer etching process. It is generally formed of a nitride film to act as a stopping layer.

이때, 상기 게이트 스페이서(108) 형성 전에, 게이트 스택의 양측의 활성 영역(101) 상에 n형 불순물 이온이 주입되어 제 1 접합 영역(106)이 형성된다. In this case, before the gate spacer 108 is formed, n-type impurity ions are implanted into the active regions 101 on both sides of the gate stack to form a first junction region 106.

다음, 도 2c를 참조하면, 워드 라인을 포함하여 반도체 기판(100) 전면에 층간절연막(interlayer dielectric)(110)이 증착 된다. 상기 층간절연막(110)의 상부 표면이 CMP(chemical mechanical polishing) 공정 등으로 평탄화 식각(planarization etch) 된다. 이때, 상기 층간절연막(110)의 평탄화는 상기 게이트 마스크막 패턴(105)의 상부가 노출되도록 수행될 수도 있다. Next, referring to FIG. 2C, an interlayer dielectric 110 is deposited on the entire surface of the semiconductor substrate 100 including the word line. The upper surface of the interlayer insulating layer 110 is planarized etched by, for example, a chemical mechanical polishing (CMP) process. In this case, planarization of the interlayer insulating layer 110 may be performed so that an upper portion of the gate mask layer pattern 105 is exposed.

상기 층간절연막(110) 상에 자기정렬 콘택 패드 형성을 위한 마스크 패턴(mask pattern)(도면에 미도시)이 형성된 후, 상기 마스크 패턴을 사용하여 층간절연막(110) 및 반도체 기판(100)의 일부 두께(t)가 식각 되어 패드 콘택홀(110a - 110c)이 형성된다. After a mask pattern (not shown) is formed on the interlayer insulating layer 110 to form a self-aligned contact pad, a portion of the interlayer insulating layer 110 and the semiconductor substrate 100 are formed using the mask pattern. The thickness t is etched to form pad contact holes 110a-110c.

이와 같이, 상기 패드 콘택홀(110a - 110c)의 하부면은 반도체 기판(100)의 상부 표면에 대해 리세스 되도록 형성되어, 패드 콘택홀(110a - 110c)의 하부에 노출된 반도체 기판(100)의 표면적이 종래 보다 넓게 된다. As such, the lower surfaces of the pad contact holes 110a-110c are formed to be recessed with respect to the upper surface of the semiconductor substrate 100, so that the semiconductor substrate 100 exposed under the pad contact holes 110a-110c. The surface area of is wider than the conventional one.

상기 식각된 반도체 기판(100)의 두께(t)는 수 백 Å 내지 수 천 Å 예를 들어, 0.42㎛ 이하의 셀 피치(cell pitch)를 갖는 소자에 대해 200Å 내지 3000Å의 두께 범위를 갖는다. The thickness t of the etched semiconductor substrate 100 has a thickness in the range of 200 ns to 3000 ns for a device having a cell pitch of several hundreds of microseconds to several thousand microns, for example, 0.42 μm or less.

이때, 상기 층간절연막(110)은 게이트 마스크막 패턴(105) 및 게이트 스페이서(108)에 대해 높은 식각 선택비를 갖는 조건으로 식각 된다. In this case, the interlayer insulating layer 110 is etched under a condition having a high etching selectivity with respect to the gate mask layer pattern 105 and the gate spacer 108.

상기 패드 콘택홀(110a - 110c) 형성을 위한 식각 공정시 발생된 반도체 기판(100)의 손상(damage)을 제거하기 위해 실리콘 RF 표면 처리(surface treatment)가 수행된다. 상기 실리콘 RF 표면 처리는 이 분야에서 잘 알려진 손상층을 제거하기 위한 일종의 건식 식각(dry etch) 공정이다. 이어서, 반도체 기판(100)의 식각에 따른 누설 전류 패스(leakage current path)를 제거하기 위해서, 상기 패드 콘택홀(110a - 110c)의 하부에 n형 불순물 이온이 주입된다. Silicon RF surface treatment is performed to remove damage of the semiconductor substrate 100 generated during the etching process for forming the pad contact holes 110a-110c. The silicon RF surface treatment is a type of dry etch process for removing damage layers well known in the art. Subsequently, n-type impurity ions are implanted into the bottom of the pad contact holes 110a-110c to remove the leakage current path due to the etching of the semiconductor substrate 100.

상기 이온주입 공정은 적어도 1회 이상 수행되고, 바람직하게 얕은(shallow) 이온주입 공정과 깊은(deep) 이온주입 공정이 순서에 무관하게 각각 수행된다. 그러면, 제 2 접합 영역(112) 및 제 3 접합 영역(114)이 각각 형성된다. The ion implantation process is performed at least once, and preferably, shallow ion implantation processes and deep ion implantation processes are performed regardless of the order. Then, the second bonding region 112 and the third bonding region 114 are formed, respectively.

이때, 상기 제 2 접합 영역(112)은 상기 제 1 접합 영역(106) 내에 제 1 접합 영역(106) 보다 상대적으로 작은 폭을 갖도록 형성되고, 상기 제 3 접합 영역(114)은 상기 제 2 접합 영역(112)을 포함하고, 상기 제 1 접합 영역(106) 보다 상대적으로 작은 폭을 가지면서 상기 제 1 접합 영역(106) 보다 상대적으로 깊게 형성된다. In this case, the second junction region 112 is formed in the first junction region 106 to have a smaller width than the first junction region 106, and the third junction region 114 is the second junction. And a region 112, and having a relatively smaller width than the first junction region 106 and relatively deeper than the first junction region 106.

그리고, 상기 제 1 내지 제 3 접합 영역(106, 112, 114)은 바람직하게 단계적인 접합 농도를 갖도록 형성된다. 그리고, 제 1 내지 제 3 접합 영역(106, 112, 114)은 동일한 오더(order)의 도즈(dose)를 사용하여 형성되고, 이때 상기 제 2 및 제 3 접합 영역(112, 114)이 상기 제 1 접합 영역보다 더 높은 도즈를 사용하여 형성된다. The first to third junction regions 106, 112, and 114 are preferably formed to have a stepped junction concentration. The first to third junction regions 106, 112, and 114 are formed using the same order of dose, wherein the second and third junction regions 112, 114 are formed of the first order. It is formed using a dose higher than one junction region.

마지막으로, 상기 패드 콘택홀(110a - 110c)이 채워지도록 n형 폴리실리콘막 등의 도전막이 증착된 후, 상기 층간절연막(108)의 상부 표면이 노출되도록 도전막이 CMP 공정 또는 에치 백(etch back) 공정 등과 같은 평탄화 식각 공정으로 식각 된다. 그러면, 도 2d에 도시된 바와 같이, 본 발명에 따른 자기정렬 콘택 패드(120a - 120c)가 완성된다. Finally, after a conductive film such as an n-type polysilicon film is deposited to fill the pad contact holes 110a-110c, the conductive film is subjected to a CMP process or etch back so that the upper surface of the interlayer insulating film 108 is exposed. Etched by a planarization etching process, such as). Then, as illustrated in FIG. 2D, the self-aligning contact pads 120a-120c according to the present invention are completed.

상기 콘택 패드(120a - 120c)가 그 하부의 접합 영역과 접촉되는 면적이 종래 콘택 패드의 접합 영역과의 접촉 면적보다 더 크기 때문에 콘택 패드(120a - 120c)와 반도체 기판(100)의 계면 저항이 감소된다. Since the area where the contact pads 120a-120c are in contact with the junction area under the contact is larger than the contact area with the junction area of the conventional contact pad, the interface resistance between the contact pads 120a-120c and the semiconductor substrate 100 is increased. Is reduced.

본 발명은 패드 콘택홀의 하부가 반도체 기판의 상부 표면에 대해 리세스 되 도록 형성함으로써, 콘택 패드와 접합 영역의 접촉 면적을 증가시킬 수 있고, 따라서 콘택 패드의 계면 저항을 줄일 수 있는 효과가 있다. According to the present invention, the bottom of the pad contact hole is formed to be recessed with respect to the top surface of the semiconductor substrate, thereby increasing the contact area between the contact pad and the junction region, thereby reducing the interface resistance of the contact pad.

이때, 실리콘 RF 표면 처리를 통해 리세스된 부위의 반도체 기판의 손상을 치유할 수 있고, 패드 콘택홀의 하부에 단계적인 접합 영역이 형성되도록 하여 누설 전류 발생을 억제할 수 있다. At this time, damage to the semiconductor substrate of the recessed portion may be healed through the silicon RF surface treatment, and the leakage current may be suppressed by forming a stepped junction region under the pad contact hole.

Claims (4)

반도체 기판(100) 상에 형성된 적어도 두 개 이상의 도전 구조물(conductive structure)과, 상기 도전 구조물은 도전막 패턴(conductive layer pattern)(104)과, 도전막 패턴(104)을 에워싸도록 형성된 질화막(105, 108)을 포함하고, 인접한 도전 구조물 사이의 영역의 반도체 기판(100)과 전기적으로 접속되도록 형성된 콘택 패드(contact pad)(120a - 120c)를 포함하는 자기정렬 콘택 패드(self-aligned contact pad)의 제조 방법에 있어서, At least two conductive structures formed on the semiconductor substrate 100, the conductive structures may include a conductive layer pattern 104, and a nitride layer formed to surround the conductive layer pattern 104. Self-aligned contact pads including 105 and 108, and contact pads 120a-120c formed to be in electrical contact with the semiconductor substrate 100 in the region between adjacent conductive structures. In the manufacturing method of), 상기 콘택 패드(120a - 120c)는 상기 도전 구조물을 포함하여 반도체 기판(100) 전면에 절연막(110)을 증착 하는 단계; Depositing an insulating layer (110) on the entire surface of the semiconductor substrate (100) including the conductive structure; 상기 인접한 도전 구조물 사이의 영역의 상기 절연막(110)을 식각 하여 패드 콘택홀(pad contact hole)(110a - 110c)을 형성하되, 절연막(110) 하부의 반도체 기판(100)의 일부를 더 식각 하여 패드 콘택홀(110a - 110c)의 하부면이 반도체 기판(100)의 상부 표면에 대해 리세스(recess) 되도록 형성하는 단계;The insulating layer 110 in the region between the adjacent conductive structures is etched to form pad contact holes 110a-110c, and a portion of the semiconductor substrate 100 under the insulating layer 110 is further etched. Forming lower surfaces of the pad contact holes 110a-110c to recess the upper surface of the semiconductor substrate 100; 상기 패드 콘택홀(110a - 110c)의 하부의 반도체 기판(100)의 표면에 대해 실리콘 표면 처리(Si surface treatment)를 수행하여 패드 콘택홀(110a - 110c) 형성시 발생된 반도체 기판(100)의 손상(damage)을 제거하는 단계;Si surface treatment is performed on the surface of the semiconductor substrate 100 under the pad contact holes 110a-110c to form the pad contact holes 110a-110c. Removing the damage; 상기 패드 콘택홀(110a - 110c)이 채워지도록 절연막 상에 도전막을 증착 하는 단계; 및 Depositing a conductive film on an insulating film to fill the pad contact holes (110a-110c); And 상기 도전막을 평탄화 식각 하여 상기 콘택 패드(120a - 120c)를 형성하는 단계를 포함하는 것을 특징으로 하는 자기정렬 콘택 패드의 제조 방법. And forming the contact pads (120a to 120c) by planarizing etching of the conductive layer. 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 도전막 증착 전에, 상기 패드 콘택홀(110a - 110c)의 하부에 불순물 이온(impurity ion)을 주입하는 단계를 더 포함하고, 상기 불순물 이온주입 공정은 적어도 1회 이상 수행되는 것을 특징으로 하는 자기정렬 콘택 패드의 제조 방법. The method may further include implanting impurity ions into the lower portions of the pad contact holes 110a to 110c before depositing the conductive layer, wherein the impurity ion implantation process is performed at least once. Method of manufacturing the alignment contact pads. 제 1 항에 있어서, The method of claim 1, 상기 리세스는 수 백 Å 내지 수 천 Å의 두께 범위를 갖는 것을 특징으로 하는 자기정렬 콘택 패드의 제조 방법. And the recess has a thickness in the range of several hundred microseconds to several thousand microseconds.
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