KR100702119B1 - Bonding pad in semiconductor device and method for fabricating the same - Google Patents

Bonding pad in semiconductor device and method for fabricating the same Download PDF

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KR100702119B1
KR100702119B1 KR1020010038914A KR20010038914A KR100702119B1 KR 100702119 B1 KR100702119 B1 KR 100702119B1 KR 1020010038914 A KR1020010038914 A KR 1020010038914A KR 20010038914 A KR20010038914 A KR 20010038914A KR 100702119 B1 KR100702119 B1 KR 100702119B1
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contact
wafer
bonding pad
back side
insulating layer
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KR1020010038914A
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Korean (ko)
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KR20030002170A (en
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김동훈
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar

Abstract

본딩패드의 면적 비율 증가를 해결할 수 있으며, 한 웨이퍼당 얻을 수 있는 칩수 증가로 제품 생산 원가를 절감하기에 알맞은 반도체소자의 본딩패드 및 그 제조방법을 제공하기 위한 것으로, 이와 같은 목적을 달성하기 위한 반도체소자의 본딩패드는 배선층을 구비한 1차 가공이 완료되었으며 백 사이드가 그라인딩된 웨이퍼의 상부면에 접합된 더미 웨이퍼, 상기 1차 가공이 완료된 웨이퍼의 그라인딩된 백 사이드상에 형성된 절연층, 상기 1차 가공이 완료된 웨이퍼의 백 사이드면에서 상기 배선층 하부면이 드러나도록 형성된 콘택홀, 상기 콘택홀의 측면에 형성된 측벽스페이서, 상기 배선층의 하부면과 콘택되도록 상기 콘택홀내에 형성된 콘택플러그, 상기 콘택플러그와 접하면서 상기 절연층상에 연장형성된 본딩패드를 포함함을 특징으로 한다. The purpose of the present invention is to provide a bonding pad for a semiconductor device and a method of manufacturing the same, which can solve the increase in the area ratio of the bonding pad and reduce the production cost by increasing the number of chips per wafer. The bonding pad of the semiconductor device may include a dummy wafer bonded to an upper surface of a wafer having a primary side with a wiring layer and a back side ground, an insulating layer formed on the ground back side of the wafer on which the primary process is completed, and A contact hole formed to expose the lower surface of the wiring layer on the back side surface of the wafer, on which the primary processing is completed, a sidewall spacer formed on the side of the contact hole, a contact plug formed in the contact hole to contact the lower surface of the wiring layer, and the contact plug And a bonding pad extending on the insulating layer while in contact with the insulating layer.

본딩패드, 그라인딩Bonding Pads, Grinding

Description

반도체소자의 본딩패드 및 그 제조방법 {BONDING PAD IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}Bonding pad of semiconductor device and manufacturing method thereof {BONDING PAD IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

도 1은 종래 기술에 따른 본딩패드의 레이아웃도 1 is a layout view of a bonding pad according to the prior art

도 2는 본 발명의 실시예에 따른 본딩패드의 레이아웃도2 is a layout view of a bonding pad according to an embodiment of the present invention.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 본딩패드의 제조방법을 나타낸 공정단면도3A to 3C are cross-sectional views illustrating a method of manufacturing a bonding pad according to an embodiment of the present invention.

도면의 주요 부분에 대한 부호의 설명 Explanation of symbols for the main parts of the drawings

31 : 실리콘기판 32 : 게이트전극 31 silicon substrate 32 gate electrode

33 : 비트라인 34 : 커패시터 33: bit line 34: capacitor

35 : 배선 36 : 평탄절연막 35 wiring 36 flat insulating film

37 : 절연층 38 : 측벽스페이서 37: insulating layer 38: side wall spacer

39 : 콘택플러그 40 : 본딩패드39: contact plug 40: bonding pad

본 발명은 반도체소자에 대한 것으로, 특히 반도체소자의 본딩패드 및 그 제조방법에 관한 것이다. The present invention relates to a semiconductor device, and more particularly to a bonding pad and a method of manufacturing the semiconductor device.                         

첨부 도면을 참조하여 종래 반도체소자의 본딩패드에 대하여 설명하면 다음과 같다. Referring to the accompanying drawings, a bonding pad of a conventional semiconductor device will be described.

도 1은 종래 기술에 따른 본딩패드의 레이아웃도이다. 1 is a layout view of a bonding pad according to the prior art.

종래에는 웨이퍼 가공면에 셀을 포함한 모든 회로를 형성하고, 패키지를 위한 본딩패드를 형성하였으며, 이때 본딩패드는 칩 사이즈의 축소를 위한 디자인룰 감소율 대비 거의 변화하지 않아 본딩패드가 차지하는 면적 비중은 증가하고 있다. Conventionally, all circuits including cells are formed on the wafer processing surface, and bonding pads for packages are formed. At this time, the bonding pads are hardly changed from the reduction rate of the design rule for reducing chip size. Doing.

그 이유는 본딩패드와 패키지 리드 프레임(lead frame)을 연결하는 와이어 본딩을 위한 장치 및 콘택 사이즈가 디자인룰 대비 거의 줄어들지 않고 있기 때문이다. This is because the device and contact size for wire bonding connecting the bonding pad and the package lead frame are hardly reduced compared to the design rule.

상기와 같이 종래 반도체소자의 본딩패드는 도 1에 도시한 바와 같이 본딩패드용 노말 콘택과 접속한 본딩패드 배선과 연결되었는데, 이때 본딩패드는 본딩패드 배선과 본딩패드용 노말 콘택의 크기에 비해서 넓은 면적을 차지하고 있다. As described above, the bonding pad of the conventional semiconductor device is connected to the bonding pad wiring connected to the normal contact for the bonding pad, as shown in FIG. 1, wherein the bonding pad is wider than the size of the bonding pad wiring and the bonding pad normal contact. Occupies an area.

상기와 같은 종래 반도체소자의 본딩패드는 다음과 같은 문제가 있다. The bonding pad of the conventional semiconductor device as described above has the following problems.

본딩패드의 면적이 칩 사이즈 축소를 위한 디자인룰(Design Rule) 감소율 대비 거의 변화하지 않아서 그 차지하는 면적 비중이 점차 증가하여 칩 사이즈 축소에 한계가 있다. Since the bonding pad area is hardly changed compared to the reduction rate of the design rule for reducing the chip size, the area portion of the bonding pad gradually increases, thereby limiting the chip size reduction.

본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 본딩패드의 면적 비율 증가를 해결할 수 있으며, 한 웨이퍼당 얻을 수 있는 칩수 증가로 제품 생산 원가를 절감하기에 알맞은 반도체소자의 본딩패드 및 그 제조방법을 제 공하는데 그 목적이 있다. The present invention has been made to solve the above problems, in particular, can solve the increase in the area ratio of the bonding pad, the bonding pad of the semiconductor device suitable for reducing the production cost of the product by increasing the number of chips per wafer and Its purpose is to provide a method of manufacture.

상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 본딩패드는 배선층을 구비한 1차 가공이 완료되었으며 백 사이드가 그라인딩된 웨이퍼의 상부면에 접합된 더미 웨이퍼, 상기 1차 가공이 완료된 웨이퍼의 그라인딩된 백 사이드상에 형성된 절연층, 상기 1차 가공이 완료된 웨이퍼의 백 사이드면에서 상기 배선층 하부면이 드러나도록 형성된 콘택홀, 상기 콘택홀의 측면에 형성된 측벽스페이서, 상기 배선층의 하부면과 콘택되도록 상기 콘택홀내에 형성된 콘택플러그, 상기 콘택플러그와 접하면서 상기 절연층상에 연장형성된 본딩패드를 포함함을 특징으로 한다. Bonding pad of the semiconductor device of the present invention for achieving the above object is a dummy wafer bonded to the upper surface of the wafer, the first side is completed with a wiring layer, the back side is ground, grinding of the wafer is completed An insulating layer formed on the back side, a contact hole formed so that the lower surface of the wiring layer is exposed from the back side surface of the wafer on which the primary processing is completed, a sidewall spacer formed on the side of the contact hole, and contacting the bottom surface of the wiring layer. And a contact pad formed in the contact hole, the bonding pad extending on the insulating layer while being in contact with the contact plug.

상기와 같은 구성을 갖는 본 발명 반도체소자의 본딩패드 제조방법은 배선층을 구비한 1차 가공된 웨이퍼를 준비하는 단계, 상기 1차 가공된 웨이퍼의 상면에 더미 웨이퍼를 접합하는 단계, 상기 1차 가공된 웨이퍼의 백 사이드를 그라인딩(grinding)하는 단계, 상기 그라인딩된 웨이퍼의 백 사이드 상면에 절연층을 형성하는 단계, 상기 그라인딩된 웨이퍼의 백 사이드면에서 상기 배선층 하부면이 드러나도록 콘택홀을 형성하는 단계, 상기 콘택홀의 측면에 측벽스페이서를 형성하는 단계, 상기 배선층의 하부면과 콘택되도록 상기 콘택홀내에 콘택플러그를 형성하는 단계, 상기 콘택플러그와 접하면서 상기 절연층상에 연장형성되도록 본딩패드를 형성하는 단계를 포함함을 특징으로 한다. Bonding pad manufacturing method of the semiconductor device of the present invention having the configuration as described above comprises the steps of preparing a primary processed wafer having a wiring layer, bonding the dummy wafer to the upper surface of the primary processed wafer, the primary processing Grinding a back side of the wafer, forming an insulating layer on an upper surface of the back side of the ground wafer, and forming a contact hole so that the lower surface of the wiring layer is exposed on the back side of the ground wafer. Forming a sidewall spacer on a side surface of the contact hole, forming a contact plug in the contact hole so as to contact the bottom surface of the wiring layer, and forming a bonding pad to be formed on the insulating layer while being in contact with the contact plug Characterized in that it comprises a step.

본 발명은 반도체 설계 및 제조시에 칩면적 증가의 원인이 되는 본딩패드 부분을 최소화하여, 칩 크기를 최소화할 수 있는 구조 및 방법에 관한 것으로, 제품 설계시에 패드콘택을 위한 최소한의 면적만 형성하고, 칩 제조공정을 완료한 후 웨이퍼 접착 및 백 사이드 그라인딩(Back side grinding)후 패드 콘택을 형성하고 이후에 패드 형성을 하여 완성된 칩의 백 사이드에 본딩할 수 있도록 한 것이다. The present invention relates to a structure and a method for minimizing chip size by minimizing a bonding pad portion which causes an increase in chip area during semiconductor design and manufacturing, and forming only a minimum area for pad contact during product design. After the chip manufacturing process is completed, the pad contact is formed after wafer bonding and back side grinding, and then the pad is formed to be bonded to the back side of the completed chip.

이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예에 따른 반도체소자의 본딩패드 및 그 제조방법에 대하여 설명하면 다음과 같다. Hereinafter, a bonding pad of a semiconductor device and a method of manufacturing the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 본딩패드의 레이아웃도이고, 도 3a 내지 도 3c는 본 발명의 실시예에 따른 본딩패드의 제조방법을 나타낸 공정단면도이다. 2 is a layout view of a bonding pad according to an embodiment of the present invention, Figures 3a to 3c is a cross-sectional view showing a manufacturing method of the bonding pad according to an embodiment of the present invention.

본 발명의 실시예에 따른 반도체소자의 본딩패드는 도 2와 도 3a와 도 3c에 도시한 바와 같이 배선(35)을 구비한 1차 가공이 완료되었으며 백 사이드가 그라인딩된 웨이퍼의 상부면에 접합된 더미 웨이퍼(41)와, 상기 1차 가공이 완료된 웨이퍼의 그라인딩된 백 사이드상에 형성된 절연층(37)과, 상기 1차 가공이 완료된 웨이퍼의 백 사이드면에서 상기 배선(35)의 하부면이 드러나도록 형성된 콘택홀과, 상기 콘택홀의 측면에 형성된 측벽스페이서(37)와, 상기 배선(35)의 하부면과 콘택되도록 상기 콘택홀내에 형성된 콘택플러그(39)와, 상기 콘택플러그(39)와 접하면서 상기 절연층(37)상에 연장 형성된 본딩패드(37)를 포함하여 구성된다. In the bonding pad of the semiconductor device according to the embodiment of the present invention, as shown in FIGS. 2, 3A, and 3C, the first processing having the wiring 35 is completed and the back side is bonded to the upper surface of the ground wafer. A dummy wafer 41, an insulating layer 37 formed on the ground back side of the wafer on which the primary processing is completed, and a lower surface of the wiring 35 on the back side surface of the wafer on which the primary processing is completed. The contact hole formed to be exposed, the side wall spacer 37 formed on the side of the contact hole, the contact plug 39 formed in the contact hole to be in contact with the lower surface of the wiring 35, and the contact plug 39. And bonding pads 37 extending on the insulating layer 37 while being in contact with each other.

상기에서 도면에 나타난 1차 가공이 완료된 웨이퍼는 디램제품의 단면을 예로 든 것으로, 셀영역과 페리영역으로 구분된 실리콘기판(31)의 격리영역에 격리산화막들과, 실리콘기판(31)내에 영역을 구분하여 복수개 형성된 웰들과, 실리콘기판(31)의 셀영역의 일영역상에 소오스/드레인영역 및 게이트전극(32)을 구비한 트랜지스터와, 드레인영역과 소오스영역에 콘택되게 각각 형성된 콘택플러그 와, 드레인영역과 콘택된 콘택플러그상에 비트라인(33)과, 소오스영역과 콘택된 콘택플러그와 접촉하도록 상부에 커패시터(34)와, 더미영역의 실리콘기판(31)과 콘택되도록 형성된 콘택플러그들과 도전라인들과, 커패시터 상부 및 페리영역의 도전라인들에 전압을 인가하기 위해서 그 상부에 형성된 콘택플러그와 이 콘택플러그와 접하고 있는 배선(35)들과, 상기 배선(35)들을 포함한 실리콘기판(31) 전면에 형성된 평탄절연막(36)을 포함한다. As shown in the drawings, the wafer having the primary processing is taken as an example of a cross section of a DRAM product. A plurality of wells formed by dividing the plurality of wells, a transistor including a source / drain region and a gate electrode 32 on one region of the cell region of the silicon substrate 31, a contact plug formed to contact the drain region and the source region, respectively; Contact plugs formed to contact the bit line 33 on the contact plugs in contact with the drain region, the capacitor 34 at the top to contact the contact plugs in contact with the source region, and the silicon substrate 31 in the dummy region. And the conductive plugs, the contact plugs formed thereon to apply voltage to the conductive lines of the capacitor and the ferry region, and the wirings 35 in contact with the contact plugs, And a flat insulating film 36 formed on the entire surface of the silicon substrate 31 including the wirings 35.

그리고 그라인딩되고 남은 웨이퍼의 두께는 기준 웰 두께의 대략 2배정도이다. The remaining wafer thickness is approximately twice the thickness of the reference well.

상기와 같이 웨이퍼의 백 사이드에 본딩패드를 형성하면 도 2에서와 같이 본딩패드의 폭이 줄어든 것을 알 수 있다. 다시말해서 본딩패드용 노말 콘택과 본딩패드용 백사이드 콘택의 면적과 비교할 때 본딩패드의 폭이 종래보다 상당히 줄어들었다. As described above, when the bonding pad is formed on the back side of the wafer, the width of the bonding pad may be reduced as shown in FIG. 2. In other words, the width of the bonding pads is considerably reduced compared to the areas of the normal contacts for the bonding pads and the backside contacts for the bonding pads.

그리고 레이아웃 상에서 보면 본딩패드용 노말 콘택의 사이에 위치하도록 웨이퍼의 백 사이드에 본딩패드용 백 사이드 콘택을 형성할 수 있으므로 본딩패드간 여유도 확보하기 쉽다. In terms of layout, the bonding pad back side contact can be formed on the back side of the wafer so as to be positioned between the bonding pad normal contacts, so that the clearance between bonding pads is easily secured.

상기와 같은 구성을 갖는 본 발명의 실시예에 따른 반도체소자의 본딩패드 제조방법에 대하여 설명한다. A method of manufacturing a bonding pad of a semiconductor device according to an embodiment of the present invention having the above configuration will be described.

먼저, 도 3a에 도시한 바와 같이 1차 가공이 완료된 웨이퍼를 형성하는 단계로써, 이때 도면에 나타난 웨이퍼는 디램제품의 단면을 예로 든 것으로, 웨이퍼의 백 사이드(Back Side)에 본딩패드를 형성할 수 있도록 설계된다. First, as shown in FIG. 3A, a process of forming a wafer having a primary process is completed. In this case, the wafer shown in the drawing is a cross section of a DRAM product, and a bonding pad may be formed on the back side of the wafer. Is designed to be.                     

상기 웨이퍼의 1차 가공은 개략적으로 다음과 같은 방법에 의해서 진행한다. The primary processing of the wafer proceeds schematically by the following method.

먼저 셀영역과 페리영역으로 구분된 실리콘기판(31)의 격리영역에 격리산화막들을 형성하고, 실리콘기판(31)내에 영역을 구분하여 복수개의 웰들을 형성한다. First, isolation oxide films are formed in an isolation region of the silicon substrate 31 divided into a cell region and a ferry region, and a plurality of wells are formed by dividing the regions in the silicon substrate 31.

그리고 실리콘기판(31)의 셀영역의 일영역상에 소오스/드레인영역 및 게이트전극(32)을 구비한 트랜지스터를 형성하고, 드레인영역과 소오스영역에 콘택되게 각각 콘택플러그를 형성하고, 드레인영역과 콘택된 콘택플러그상에 비트라인(33)을 형성하고, 소오스영역과 콘택된 콘택플러그와 접촉하도록 상부에 커패시터(34)를 형성한다. Then, a transistor including a source / drain region and a gate electrode 32 is formed on one region of the cell region of the silicon substrate 31, and contact plugs are formed in contact with the drain region and the source region, respectively. A bit line 33 is formed on the contact plug, and a capacitor 34 is formed on the contact plug so as to contact the contact plug in contact with the source region.

그리고 더미영역에도 실리콘기판(31)과 콘택되도록 콘택플러그들과 도전라인들을 형성한다. Contact plugs and conductive lines are formed in the dummy region to be in contact with the silicon substrate 31.

그리고 커패시터상부 및 페리영역의 도전라인들에 전압을 인가하기 위해서 그 상부에 콘택플러그를 형성하고 배선(35)들을 형성한다. In order to apply a voltage to the conductive lines of the capacitor and the ferry region, a contact plug is formed on the upper portion of the capacitor and the wirings 35 are formed.

이후에 상기 배선(35)들을 포함한 실리콘기판(31) 전면에 평탄절연막(36)을 형성한다. Thereafter, the planar insulating layer 36 is formed on the entire surface of the silicon substrate 31 including the interconnections 35.

다음에 진행할 공정은 도 3b에 도시한 바와 같이 1차 가공이 완료된 상태의 웨이퍼와 더미웨이퍼(41)를 접합한 후에 1차 가공된 웨이퍼의 백 사이드를 그라인딩(grinding)한다. In the next step, as shown in FIG. 3B, the wafer in which the primary processing is completed is bonded to the dummy wafer 41, and then the back side of the primary processed wafer is ground.

좀 더 자세하게는 도 3b와 같이 1차 가공된 웨이퍼상면의 평탄절연막(36)상에 더미 웨이퍼(41)를 접합한다. 이것은 도면에 점선으로 나타내었다. More specifically, as shown in FIG. 3B, the dummy wafer 41 is bonded onto the flat insulating film 36 on the wafer upper surface that is primarily processed. This is indicated by dotted lines in the figures.

그리고 실리콘기판(31)의 백사이드를 그라인딩(도면에 점선으로 나타내었음) 시키는 것으로, 이때 실리콘기판(31)이 남는 두께는 반도체 제품의 특성에 영향을 주지 않을 정도로 가능한한 얇게 한다. 이때 남는 두께는 기준 웰 깊이의 대략 2배정도가 되도록 한다. Then, the backside of the silicon substrate 31 is ground (indicated by a dotted line in the drawing), where the thickness of the silicon substrate 31 remains as thin as possible so as not to affect the characteristics of the semiconductor product. At this time, the remaining thickness is approximately twice the depth of the reference well.

다음에 진행할 공정은 도 3c에 도시한 바와 같이 그라인딩한 면에 콘택홀과 콘택플러그와 본딩패드를 형성하는 것이다. The next step is to form contact holes, contact plugs, and bonding pads on the ground as shown in FIG. 3C.

좀더 자세히 설명하면, 그라인딩된 실리콘기판(31)의 하면상에 얇은 두께의 절연층(37)을 형성하고, 그라인딩된 실리콘기판(31)의 백사이드에 배선층(35)의 하부면이 드러나도록 콘택홀을 형성한다. In more detail, a thin insulating layer 37 is formed on the bottom surface of the ground silicon substrate 31, and the contact hole is exposed so that the bottom surface of the wiring layer 35 is exposed on the backside of the ground silicon substrate 31. To form.

그리고 상기와 같이 형성된 콘택홀의 측면에 실리콘기판(31)과의 쇼트를 방지하기 위하여 전면에 산화막이나 질화막을 증착한 후 에치백공정을 진행해서 콘택홀의 측면에 측벽스페이서(38)를 형성하고, 콘택홀내에 차후에 배선(35)과 패드를 연결하기 위해서 배선(35) 하부면과 콘택되도록 콘택플러그(39)를 형성한다. In order to prevent a short circuit with the silicon substrate 31 on the side of the contact hole formed as described above, an oxide film or a nitride film is deposited on the entire surface, and an etch back process is performed to form sidewall spacers 38 on the side of the contact hole. The contact plug 39 is formed to contact the lower surface of the wiring 35 so as to connect the wiring 35 and the pad later in the hole.

이후에 배선(35)과 연결된 콘택플러그(39) 및 그에 연장되도록 절연층(37)상에 본딩패드(40)를 형성한다. 이때 본딩패드(40)는 배선에 많이 사용되는 금속 예를 들어 텅스텐(W)이나 알루미늄(Al)이나 텅스텐 실리사이드(WSix)와 같은 물질을 사용한다. Thereafter, a bonding pad 40 is formed on the contact plug 39 connected to the wiring 35 and the insulating layer 37 to extend therefrom. In this case, the bonding pad 40 uses a metal such as tungsten (W), aluminum (Al), or tungsten silicide (WSix), which are frequently used for wiring.

상기와 같은 방법은 본딩패드(40) 형성공정 뿐만아니라 파워 라인(Power line) 배선과 같이 큰 면적을 소모하는 패턴 형성에도 적용할 수 있다. The above method can be applied not only to the bonding pad 40 forming process but also to the formation of a pattern consuming a large area such as power line wiring.

상기와 같은 본 발명 반도체소자의 본딩패드 및 그 제조방법은 다음과 같은 효과가 있다. As described above, the bonding pad and the method of manufacturing the semiconductor device of the present invention have the following effects.

동일 면적내에 보다 많은 패턴을 형성할 수 있고, 칩 사이즈가 축소되는 동향에서 문제가 되는 본딩패드의 면적 비율 증가를 해결하면서 효율적으로 소자설계를 할 수 있다. More patterns can be formed in the same area, and the device design can be efficiently carried out while solving an increase in the area ratio of the bonding pad, which is a problem in the trend of shrinking the chip size.

또한 상기와 같이 칩 사이즈의 축소가 가능하게되면 한 웨이퍼당 얻을 수 있는 칩수 증가로 제품 생산 원가를 절감할 수 있다는 효과가 있다. In addition, if the chip size can be reduced as described above, the production cost can be reduced by increasing the number of chips per wafer.

Claims (4)

배선층을 구비한 1차 가공이 완료되었으며 백 사이드가 그라인딩된 웨이퍼의 상부면에 접합된 더미 웨이퍼, The dummy wafer bonded to the upper surface of the wafer, in which the primary processing with the wiring layer is completed and the back side is ground, 상기 1차 가공이 완료된 웨이퍼의 그라인딩된 백 사이드상에 형성된 절연층, An insulating layer formed on the ground back side of the wafer on which the primary processing is completed, 상기 1차 가공이 완료된 웨이퍼의 백 사이드면에서 상기 배선층 하부면이 드러나도록 형성된 콘택홀, A contact hole formed to expose the lower surface of the wiring layer on the back side surface of the wafer on which the primary processing is completed; 상기 콘택홀의 측면에 형성된 측벽스페이서, Sidewall spacers formed on side surfaces of the contact holes; 상기 배선층의 하부면과 콘택되도록 상기 콘택홀내에 형성된 콘택플러그, A contact plug formed in the contact hole to contact the lower surface of the wiring layer; 상기 콘택플러그와 접하면서 상기 절연층상에 연장형성된 본딩패드를 포함함을 특징으로 하는 반도체소자의 본딩패드. Bonding pads extending on the insulating layer while being in contact with the contact plugs. 배선층을 구비한 1차 가공된 웨이퍼를 준비하는 단계, Preparing a primary processed wafer having a wiring layer, 상기 1차 가공된 웨이퍼의 상면에 더미 웨이퍼를 접합하는 단계, Bonding a dummy wafer to an upper surface of the first processed wafer, 상기 1차 가공된 웨이퍼의 백 사이드를 그라인딩(grinding)하는 단계, Grinding the back side of the primary processed wafer, 상기 그라인딩된 웨이퍼의 백 사이드 상면에 절연층을 형성하는 단계, Forming an insulating layer on an upper surface of a back side of the ground wafer, 상기 그라인딩된 웨이퍼의 백 사이드면에서 상기 배선층 하부면이 드러나도록 콘택홀을 형성하는 단계, Forming a contact hole to expose a lower surface of the wiring layer on a back side surface of the ground wafer, 상기 콘택홀의 측면에 측벽스페이서를 형성하는 단계, Forming a sidewall spacer on a side of the contact hole; 상기 배선층의 하부면과 콘택되도록 상기 콘택홀내에 콘택플러그를 형성하는 단계, Forming a contact plug in the contact hole to be in contact with the bottom surface of the wiring layer; 상기 콘택플러그와 접하면서 상기 절연층상에 연장형성되도록 본딩패드를 형성하는 단계를 포함함을 특징으로 하는 반도체소자의 본딩패드 제조방법. Forming a bonding pad in contact with the contact plug to extend on the insulating layer. 제2항에 있어서, The method of claim 2, 상기 본딩패드는 텅스텐이나 알루미늄이나 텅스텐 실리사이드로 형성할수 있음을 특징으로 하는 반도체소자의 본딩패드 제조방법. The bonding pad may be formed of tungsten, aluminum or tungsten silicide. 제2항에 있어서, The method of claim 2, 상기 측벽스페이서는 상기 콘택홀을 포함한 상기 절연층상에 산화막이나 질화막을 증착한 후에 에치백하여 형성할 수 있음을 특징으로 하는 반도체소자의 본딩패드 제조방법. And the sidewall spacers may be formed by etching back an oxide film or a nitride film on the insulating layer including the contact hole.
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