KR100234211B1 - Manufacturing method of semiconductor memory device - Google Patents

Abstract

In the production of the SOI substrate according to the present invention, the nonuniformity of the film thickness of the silicon layer to be polished after bonding is reduced. P which functions as an etching stop layer before bonding board | substrates together Type impurity layer is formed, and the single crystal silicon layer laminated on the impurity layer is bonded to another silicon substrate via an insulating silicon oxide film. The etching to the impurity layer is performed before the final selective polishing, and since the uniform surface is obtained on the impurity layer at the time of stopping the etching, the nonuniformity of the film thickness of the silicon layer is reduced even after the selective polishing.

A method of manufacturing a nonvolatile memory device in which a surface of a floating gate electrode layer stacked on a substrate is polished and planarized, and then a control gate electrode layer is laminated through a gate insulating film, wherein the number of electrons emitted by the thermal energy from the floating gate electrode is increased. It can reduce the number and improve the data retention characteristics.

Description

Manufacturing Method of Semiconductor Memory Device

1 (a) to 1 (g) show a conventional method for producing a bonded SOI.

2 is a cross-sectional view of a conventional EEPROM.

3 (a) to 3 (e) are sectional views of the manufacturing process of the semiconductor device having the SOI structure according to the first embodiment of the present invention.

4 (a) to 4 (f) are cross-sectional views of the manufacturing process of the semiconductor device having the SOI structure according to the second embodiment of the present invention.

5 (a) to 5 (f) are cross-sectional views of a manufacturing process of a semiconductor device having an SOI structure according to a third embodiment of the present invention.

6 (a) to 6 (f) are sectional views of the manufacturing process of an EEPROM device formed using the manufacturing process of the SOI device according to the fourth embodiment of the present invention.

The present invention relates to a method of manufacturing a semiconductor memory device having a silicon on insul (a) tor (SOI) structure. SOI is used as a structure of electronic components, such as a semiconductor device, for example, and this invention can be used as a formation method of various SOI structures.

In particular, the present invention can be used in SRAM or EEPROM.

In the case of an EEPROM, the present invention relates to a method of manufacturing a nonvolatile memory device in which a control gate electrode layer is laminated on an floating gate electrode layer through an insulating film.

Conventionally, the SOI structure is a method of forming a silicon portion on an insulating portion and forming various semiconductor elements on the silicon portion, and is mainly used in the field of electronic materials.

As one of the means for forming the SOI structure, a technique in which a silicon portion is present on the insulating portion by bonding another substrate to the surface on the side of the insulating portion of the silicon substrate on which the insulating portion is formed and polishing the silicon substrate is provided. Known. This is generally called a bonded SOI or the like.

The bonded abrasive SOI structure and its process enable high integration of electronic materials, and devices can be made above and below the silicon layer, contributing to further high integration of ICs and the like.

A conventional method for forming such bonded SOI structure will be described with reference to FIGS. 1 (a) to 1 (g). (Extended abstracts of the 21st Conference on Solid State Devices and Material 15, Tokyo, 1989, pp. See M .. Hashimodo et al., "Low Leakage SOIMOSFETs Fabricated Using a Wafer Bonding Method" of 89-92n).

As shown in Fig. 1 (a), one surface of the silicon substrate 1 (generally, a high flatness silicon wafer is used. This is referred to as substrate (a)) may be formed using photolithography or etching techniques. Patterning is performed to form recesses having a depth of 1500 mm or less.

Next, the insulating portion 2 is formed on this surface by forming a SiO 2 film by CVD or the like. Thereby, as shown in FIG. 1 (b), a structure in which the insulating portion 2 is formed on one side of the silicon substrate 1 can be obtained. The insulating portion 2 is formed as a film having irregularities as shown in accordance with the surface shape of the patterned silicon substrate 1.

Further, the polysilicon film 3 is formed on the insulating portion 2 by about 5 mu m thickness by CVD or the like. Thereby, it is set as the structure of FIG. 1 (c). The polysilicon film 3 is for forming a highly smooth bonding surface when bonding the other board | substrate 4 (the board | substrate 4 shown by B in FIG. 1 (e)) at a later process.

Next, the surface of the polysilicon film 3 is planarized and polished to obtain a highly smooth surface (FIG. 1 (d)). Here, as the remaining film, the polysilicon film 3 is made to have a thickness of 3 µm or less.

Another substrate 4 (this is referred to as substrate B) is brought into close contact with the polished surface of the polysilicon film 3. Both surfaces are joined by close contact, and as a result, a joining structure as shown in FIG. 1 (e) is obtained. In general, it is said that solid bonding is achieved by hydrogen bonding interposed on both sides. It is usually heated to heat bond to achieve a very tight bond. Bonding strength is generally 200 kg / cm 2 or more, and may be 2000 kg / cm 2 in some cases. It is common for the other substrate 4 (substrate B) to be bonded to use the same silicon substrate as the substrate 1 (substrate (a). Since the heating process is often performed after the bonding, the physical properties such as the coefficient of thermal expansion are the same. If there is no such problem, for example, in the prior art shown, since the other board | substrate 4 only serves as a support stand, it does not necessarily need to be a silicon board | substrate. However, when the element is also formed on the other substrate 4 (substrate B) to be bonded, it is necessary to be a semiconductor substrate capable of forming an element.

Subsequently, the substrate 1 is ground, so that the silicon portion of the substrate 1 is about 5 µm or less as a residual film to have the structure shown in FIG. 1 (f). FIG. 1 (f) is the inverse of FIG. 1 (e). This is because the substrate 1 is turned upside down for the grinding and the subsequent selective polishing.

Subsequently, selective polishing is performed. In this case, precise finishing polishing is performed until the insulator 2 is exposed. As a result, as shown in FIG. 1 (g), a structure is formed in which the silicon portion 10 is present on the insulating portion 2 surrounded by the uneven portion 2. This silicon portion 10 becomes an SOI film. Thus, various elements are formed in the silicon part 10 (SOI film) with respect to the structure (SOI structure) in which the silicon part 10 exists on the insulator 2. As shown in FIG. 1 (g), since each silicon portion 10 is surrounded by the insulating portion 2, the element is separated from the beginning.

In addition, in the above-described manufacturing method of the SOI substrate, since the film thickness of the silicon portion 10 during the first (g) becomes nonuniform in the wafer surface, the island-like single crystal silicon thin film formed in the required pattern also has uneven film thickness. Done.

In addition, selective polishing is performed until the interface between the silicon wafer and the silicon oxide film is exposed to make the single crystal silicon thin film a desired pattern, but in this case, some overpolishing is required, and thus the surface of the silicon is prolonged for a long time. Exposure to an alkaline polishing liquid causes the silicon surface to become rough. In the case where a TFT (thin film transistor) is formed on the roughened silicon surface, the reliability of the gate insulating film is lowered, and thus it is not a device having good characteristics.

Further, in the SOI process using the bonded polishing method or the constant voltage deposition method as described above, various devices can be formed in the front and back of the SOI section (silicon part 10 in the first (g) diagram), thereby increasing the mounting density. It is possible to paint. By employing this technique, memory cells such as DRAM can be reduced. By the way, in the conventionally proposed technique, the densification of circuits such as memory cells is emphasized, while the advantages of this technique have not been fully utilized in peripheral circuits. For example, in terms of memory devices such as DRAM and SRAM, it is considered to reduce the size of memory cells using SOI technology. However, SOI technology is not necessarily used for other peripheral circuits. In order to increase the performance (for example, to increase the speed), the in-transistor has not been performed.

In addition, in the manufacturing method of a memory device such as an EEPROM, the electrical properties can be improved by applying the polishing method used for SOI.

By the way, in this process, when the floating gate electrode layer is formed, the surface thereof is not formed flat, and as shown in FIG. 2, the spire-shaped protrusions 15 are formed. And where these projections 15 exist, it becomes a structure which an electric field concentrates.

Therefore, although the second gate insulating film between the floating gate electrode 13 and the control gate electrode 14 is thinned by the protrusions 15, when the LSI is manufactured and voltage is applied in this state, , Where the projections 15 are located, the electric field is concentrated. The electron concentration in the floating gate electrode is drawn by the electric field applied to the control gate electrode due to the electric field concentration, and the retention characteristic of the signal data is generated, resulting in a problem that the threshold value of the memory transistor cannot be maintained at a high level.

Accordingly, a first object of the present invention is to provide a method for producing an SOI substrate which improves the uniformity of the surface of the silicon layer to be polished.

It is a second object of the present invention to realize a higher density mounting using SOI technology, and to provide a method for manufacturing an SOI substrate that fully utilizes the advantages of SOI technology even in a peripheral circuit portion, for example.

A third object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory which prevents data retention characteristics from deteriorating in a memory device such as an EEPROM using a technique used to form an SOI and maintains the threshold value of a memory transistor at a high level. To provide.

According to the present invention, in the method of manufacturing an SOI substrate in which a thin silicon layer is formed on an insulating substrate by bonding the substrates, the step of forming an etching stop layer on the surface of the silicon substrate, and the etching stop layer image Forming an epitaxially grown silicon layer, bonding the silicon substrate on which the silicon layer is formed to another substrate to be the insulator gas, and grinding the silicon substrate from the back side thereof to the etching stop layer. The present invention provides a method for producing an SOI substrate, comprising a step of etching until the exposure is performed and a step of removing the etching stop layer.

Next, a preferred embodiment of the present invention will be described with reference to the drawings.

First, a first embodiment according to the present invention will be described.

This embodiment is a manufacturing method of an SOI substrate which is produced by bonding a pair of silicon wafers together, in particular, as the etching stop layer. It is a method of forming a type impurity layer. Next, the present embodiment will be described with reference to FIGS. 3 (a) to 3 (e) according to the process.

First, a P ⁺ type impurity layer 22 having a thickness X is formed on the surface of the (100) surface of the P ⁻ type single crystal silicon substrate 21. This P ⁺ type impurity layer 22 functions as an etching stop layer. This P The impurity layer 22 is formed by introducing impurities such as boron into the surface of the silicon substrate 21 by ion implantation, thermal diffusion, or the like. The impurity concentration of the P ⁺ type impurity layer 22 is about 10 ²⁰ cm ^-3 , and P The impurity concentration of the silicon substrate 21 is about 10 ¹⁴ cm ^-3 . Since the silicon substrate 21 is initially finished as a mirror surface, the P ⁺ type impurity layer 22 also has a small variation in thickness X.

Subsequently, as shown in FIG. 3 (a), P is formed by the epitaxial growth method. P on the surface of the silicon substrate 21 on which the impurity layer 22 of the type The silicon layer 23 of the type | mold is formed. By the epitaxial growth method, the silicon layer 23 is a single crystal reflecting the crystallinity of the substrate.

After the silicon layer 23 as the epitaxial growth layer is formed, a step 24 is formed in accordance with the pattern of island regions to be formed on the surface 23 (a) of the silicon layer 23. The height of the step 24 corresponds to the film thickness of the single crystal silicon thin film to be formed, and after the step 24 is formed, the silicon oxide film 25 is deposited on the entire surface as shown in FIG. 3 (b). .

Another silicon substrate 26 is prepared, and as shown in FIG. 3 (c), the silicon substrate 21 having the silicon oxide film 25 deposited on its surface via the polysilicon layer 27 is subjected to a conventional bonding method. Join together. The film thickness of the silicon layer 23 is set so that the impurities of the P ⁺ type impurity layer 22 do not diffuse to the portion of the bottom 24 (a) of the step 24 by the heat treatment up to the bonding step. desirable.

Next, the silicon substrate 21 is ground from the back side of the silicon substrate 21 to such an extent that the P ⁺ type impurity layer 22 as the etching stop layer is not exposed, thereby reducing the thickness of the silicon substrate 21. After grinding, P is etched using an impurity concentration difference. The silicon substrate 21 is ground until the impurity layer 22 of the type appears. This etching is etching using an ethylenediamine-pyrocatechol-pure water mixture as an etching solution. When the etching rate of the P ⁺ -type impurity layer is 1 with respect to the silicon on the (100) plane, the P ^- type silicon substrate is used. The etching rate of (21) is 400, so that etching with a very high selectivity is performed. Since the P ⁺ type impurity layer 22 having high uniformity is already formed using the mirror-finished silicon substrate 21, the third (d) also reflects the P ⁺ type impurity layer 22. As shown in Fig. 3, etching stops in a state where the variation in film thickness is very small.

And, since the etching speed ratio of 400 to 1, at the surface of the P ⁺ -type impurity layer 22, the thickness X is at least P ⁺ -type impurity layer 22 of up to a bottom (24 (a) of the step (24) What is necessary is just more than 400th of the distance Z.

After the etching is stopped uniformly on the surface of the P ⁺ type impurity layer 22, the P ⁺ type impurity layer 22 and the silicon layer 23 formed by epitaxial growth are polished by selective polishing. do. At this time, since in-plane unevenness is suppressed on the surface of the P ⁺ type impurity layer 22, the exposed surface 23b of the silicon layer 23 obtained by selective polishing also becomes a single crystal silicon thin film having excellent uniformity.

As described above, in the manufacturing method of the SOI substrate of this embodiment, since the etching stops at a uniform surface by the P ⁺ type impurity layer 22, even if selective polishing is performed, the film thickness of the single crystal silicon thin film in the island region is uneven. Will be suppressed. In addition, because of its excellent uniformity, excessive polishing is unnecessary, and the exposed surface 23b of the silicon layer 23 is not exposed to the alkaline polishing liquid for a long time. Thus, the reliability of the SOI device is also improved.

In the method for producing an SOI substrate of the present invention, the etching stop layer is uniformly formed on the surface of the silicon substrate, and reflecting the uniformity, the etching from the back surface of the silicon substrate after bonding can be stopped. Therefore, the uniformity of the film thickness of the single crystal silicon thin film becomes excellent, and selective polishing also ends in a short time. Therefore, by applying the manufacturing method of the SOI substrate of this invention, the reliability of the device formed on an SOI substrate can also be improved significantly.

Next, a second embodiment according to the present invention will be described with reference to FIGS. 4 (a) to 4 (f).

As shown in Fig. 4A, one surface of the silicon substrate 31 is patterned.

Next, the insulating portion 32 is formed thereon, and then, at the position on one side of the surface on which the insulating portion 32 of the silicon substrate 31 is formed, that is, the position to form the transistor which is the peripheral circuit in this embodiment, The first conductive portions 43a and 43b (the first gate electrode in this embodiment) are formed to have the structure shown in FIG. 4 (b).

Next, the connection hole 44 is formed at the other position on the same surface of the silicon substrate 31, that is, in this embodiment, at the position where the cell portion of the semiconductor memory element such as DRAM is to be formed. (45) is formed and it is set as the structure of FIG.

Next, a groove 46 is formed on the connecting portion 45 to form a trench function portion (a memory capacitor comprising an accumulation electrode 47 and a capacitor insulating film 48 in the illustrated example). Thus, the structure of Fig. 4 (d) is obtained.

Thereafter, as described with reference to FIG. 1, the polysilicon film 33 is appropriately formed, polished (see also FIG. 4 (e)), and the other substrate 53 is bonded to each other. The substrate 52 is not particularly shown in FIG. 4, but is the same as in FIG. 1.

In addition, the other surface of the silicon substrate 31 is polished to form a silicon portion 40, and then a second conductive portion (peripheral circuit side in the illustrated example) is disposed at the one position and the other position. The second gate electrodes 49a and 49b of the transistor and the second gate electrode 49c on the cell side serving as the word electrode) are formed to form the SOI structure shown in FIG. 4 (f).

More specifically, this embodiment takes steps (1) to (7) described below as specific configurations.

(1) Silicon RIE is performed on the silicon substrate 31 to form isolation regions between elements. The etching depth is about 100 nm or less. Thereby, the structure of FIG. 4 (a) is obtained.

(2) An insulating portion 32 made of SiO 2 is formed by surface oxidation. This also serves as the first gate insulating film 41 of the peripheral circuit transistor. In the peripheral circuit portion, first gate electrodes, which are the first conductive portions 43a and 43b, are formed of polysilicon or the like.

(3) The interlayer film 50 is formed on the entire surface by CVDSiO2 or the like. A contact, which is a connection hole 44 for taking out the storage electrode, is opened in the cell portion and embedded in polysilicon or the like to form a connection portion 45 (polysilicon plug). This is obtained by forming polysilicon on the whole surface and etching it back. Thereby, the structure of FIG. 4 (c) is obtained.

(4) In addition, as the interlayer film 51, SiO2 was deposited by CVD, and then, grooves 46 were formed in the cell portion, and this was used as grooves for forming storage electrodes. After the groove 46 is formed, polysilicon or the like is formed on the entire surface (part shown by the broken line in FIG. 4 (d)), and then etched back to form the storage electrode 47.

(5) A capacitor insulating film 48 is formed using a silicon nitride film or the like. Thereby, the structure of FIG. 4 (d) is obtained.

(6) After that, the plate electrode 33 is formed of polysilicon or the like, and the surface is planarized by polishing. Thereby, the structure of FIG. 4 (e) is obtained.

(7) The support substrate 52 (not shown) and the polishing surface of the plate electrode 33 are bonded to each other by bonding or constant voltage bonding. Subsequently, the silicon substrate 31 on the device side is polished using SiO2 as the insulating portion 32 as a stopper. The surface is oxidized again to form the SiO 2 film 42. Second conductive portions 49a to 49c are formed on the substrate to form a gate electrode. This is a word line (second conductive portion 49c) in the cell, and a second electrode (second conductive portions 49a, 49b) of the double gate in the peripheral circuit portion. This second electrode is connected to the first electrode through a contact hole in advance.

Subsequent processes form the semiconductor memory device through the same process as the various processes (source, drain injection, aluminum wiring, etc.) which have conventionally been employed to form memory cells and their peripheral circuits.

According to this embodiment, since the peripheral transistor circuit can be configured with a double gate, the density of the peripheral circuit can be realized.

Next, a third embodiment according to the present invention will be described.

The process flow of this embodiment is shown in FIGS. 5 (a) to 5 (f).

As shown in FIG. 5 (b) of the method for forming the SOI structure of the present embodiment, the other substrate (on the surface on which the insulating portion 62 is formed of the silicon substrate 61 on which the insulating portion 62 is formed) is formed. 80 is bonded (bonded to the upper surface of FIG. 5 (e)), and the other surface of the silicon substrate 61 is polished, so that the silicon portion 70 is formed on the insulating portion 62 as shown in FIG. 5F. In the SOI structure formation method which obtains this existing SOI structure, each of the following steps is taken.

That is, as shown in Fig. 5A, one surface of the silicon substrate is patterned.

Next, the insulator 62 is formed thereon, and at one position on the surface where the insulator 62 of the silicon substrate 61 is formed, that is, at the position where the transistor which is the peripheral circuit in this embodiment is to be formed. The connection holes 75 are formed at the other positions on the same side of the silicon substrate 61, that is, at the positions at which cell portions of semiconductor memory elements such as DRAMs in this embodiment are to be formed. ) Is formed to have a structure as shown in FIG. 5 (b).

Next, the openings 66a and 66b are filled with polysilicon or the like to form the first conductive portions 72a and 72b, i.e., the conductive portions 72a to be the first gate electrodes in this embodiment, It forms 72b. At the same time, the connection hole 75 is embedded, and the connection portion 76 is formed to have the structure shown in FIG. 5 (c).

Next, a groove 77 is formed on the connection portion 76, and a trench function portion (a memory trench capacitor as in the second embodiment) is formed in the groove 77 to have the structure shown in FIG. 5 (d).

Thereafter, in the same manner as in Example 2, another substrate (not shown) is bonded through the structure shown in FIG. 5 (e), and the other surface of the silicon substrate 61 is polished again to form the silicon portion 70. ), And thereafter, second conductive portions 74a to 74c as in Example 2 are formed at the one position and the other position to obtain the SOI structure shown in FIG. 5 (f). .

In this embodiment, the method of forming the first conductive portions 72a and 72b (the first electrode) is different from that of the second embodiment, and the conductive material at the time of forming the polysilicon plug in the cell portion, which is the connecting portion 76, is formed. (Polysilicon) is also used as the first electrode of the double gate of the peripheral transistor. The first gate oxide film 71 in the peripheral circuit portion uses a resist mask in the previous step of FIG. 5 (b), and the cell portion is etched away with dilute fluoric acid or the like to obtain the structure of FIG. 5 (b). . The subsequent process is the same as Example 2.

The insulating portion 62 can be formed by CVD of SiO 2. In Fig. 5, reference numeral 68 is an interlayer film, which is formed by CVDSiO2 or the like.

This embodiment can also obtain the same effects as in the second embodiment.

In the second and third embodiments, the first conductive portion is the first electrode for double gate configuration of the peripheral transistor of the memory element, but the present invention is not limited to this. For example, the present invention may be applied to the formation of a MOS transistor structure to configure the first conductive portion as a connection wiring for connecting the NMOS and the PMOS. It can be used as other various wiring structures.

As described above, according to the present invention, higher density is realized by using an SOI technique. For example, the peripheral circuit can be embodied as a method for forming an SOI structure that fully utilizes the advantages of the SOI technology.

Further, in the second and third embodiments, the P ⁺ type impurity layer 22 and the P ⁻ type silicon layer (on the P ⁻ type silicon substrate 21 described in the first embodiment of the present invention) 23, and in the same manner, the silicon portion (SOI film) 40 in FIG. 4 (f) and the silicon portion (SOI film) 70 in FIG. 5 (f) may be formed with high precision. have.

Next, a fourth embodiment according to the present invention will be described.

First, as shown in FIG. 6 (a), the surface of the silicon substrate 81 is oxidized to form the first gate insulating film 82, and then pure polysilicon free of impurities in the first layer as the floating gate electrode layer. Form layer 83. When the polysilicon layer 83 of the first layer is formed, the projections 86 have already occurred as shown in FIG. 6 (a). Thereafter, P (phosphorus) is diffused into the polysilicon layer 83 in order to make the floating gate electrode layer conductive.

Then, for example, the PSG (phosphorus) film 87 or the like is formed by this diffusion, but as shown in FIG. 6 (b), the projection 86 does not disappear, but rather the PSG film 87 It grows naturally again on the back, and the height of the projection 86 reaches 500-1000 kPa.

Thus, the projection 86 is removed. Removal of the projections 86 first removes the PSG (phosphorus) film 87 or the like formed at the time of diffusion of the P (phosphorus) by etching.

Then, before patterning the polysilicon layer 83 of the first layer, the grown projections 86 are polished using the following apparatus.

The apparatus used for polishing the protrusion 86 is composed of an upper half 90 and a lower half 89 as shown in FIG. 6 (d). It is a ceramic plate. In the other lower half 89, a polishing cloth 88 is disposed on the surface portion thereof. As the polishing cloth 88 of the lower half 89, a soft polishing cloth (soft cloth) is used.

The silicon substrate 81 on which the protrusions 86 are grown on the polysilicon layer 83 as the first layer on the upper half 90 of the ceramic plate is placed downward. Then, the lower half 89 at which the polishing cloth 88 is disposed is rotated at least.

In the experiment conducted by the inventor of the present invention, the circumferential speed was set at 50 m / sec and the pressurization was set at 140 g / cm 2, respectively.

Then, the polishing liquid flows on the polishing cloth 88 of the lower half 89. This polishing liquid was prepared by adding an abrasive (dispersed colloidal silica in a strong alkaline liquid), where the flow rate was 5 kPa / min.

Under these conditions, the lower half 89 was rotated to polish the projections 86 on the polysilicon layer 83 of the first layer as the floating gate electrode layer.

Then, as shown in FIG. 6 (f), the surface is polished to remove the projections to form the first polysilicon layer 83 that is flattened. As described above, polishing was performed by combining chemical polishing using an abrasive and mechanical polishing using an abrasive cloth. In the experimental example performed by the present inventors, polishing the surface of the polysilicon layer 83 of the first layer with high precision was performed under the above conditions. It was confirmed that it could be done.

After that, the polysilicon layer 85 of the second layer for the control gate electrode layer is grown through the second gate insulating film 83.

Then, as shown in FIG. 6 (c), since the surface of the floating gate electrode layer 83 is already formed flat, there is no place where the oxide film of the second gate insulating film 84 is thinned. Therefore, the breakdown voltage between the floating gate electrode layer 83 and the control gate electrode layer 85 can be improved.

Thereafter, even when the LSI is manufactured and a voltage is applied, the electric field is no longer locally concentrated between the floating gate electrode layer 83 and the control gate electrode layer 85 as in the prior art. Therefore, the data holding characteristic is improved.

In addition, although the nonvolatile semiconductor memory of EEPROM is used in this embodiment, it can also be used for CCD and the like.

The present invention can eliminate the projections on the surface by polishing the surface of the floating gate electrode layer as described above. Therefore, the oxide film of the second gate insulating film is not partially thinned. As a result, even when an operating voltage is applied to the nonvolatile memory device, electrons are drawn from the floating gate electrode by the electric field, thereby retaining data. There is no deterioration.

That is, when the element is stored for a long time after the initial writing, the number of electrons emitted by the thermal energy from the floating gate electrode can be reduced, and the data holding characteristic can be improved. Therefore, the threshold of the memory transistor can be maintained at a higher level.

Claims (3)

A method of manufacturing an SOI substrate in which a thin silicon layer is formed on an insulating substrate by bonding the substrates together, the method comprising: forming an etching stop layer on the surface of the silicon substrate; and having a rectangular step on the etching stop layer. Epitaxially growing a silicon layer, bonding the silicon substrate on which the silicon layer is formed to another substrate to be the insulating substrate, and a range in which the etching stop layer is not exposed from the back side of the silicon substrate; And a step of grinding until etch stop layer is exposed using ethylenediamine and pyrocatechol solution, and a step of removing the etch stop layer. Insulation is formed by forming an insulating layer on one surface of the first silicon substrate, bonding the second silicon substrate to the surface on which the insulating layer of the first silicon substrate is formed, and polishing the other surface of the first silicon substrate. A method of manufacturing an SOI substrate which obtains an SOI structure in which a silicon portion is present in floating, comprising: patterning one surface of the first silicon substrate in a surface relief pattern to form the insulating portion thereon; Forming a first conductive portion in one position, forming a connection hole through the insulating portion at a second position, and filling the connection hole to form a buried connection portion; and forming a groove in the connection portion to form a trench in the groove. A step of forming a part, and then a step of bonding the second silicon substrate to each other, and a hole for polishing the other surface of the first silicon substrate to form the silicon part And, then the method of producing a SOI substrate comprising a step of forming a second conductive portion in the first and second position. Insulation is formed by forming an insulating layer on one surface of the first silicon substrate, bonding the second silicon substrate to the surface on which the insulating layer of the first silicon substrate is formed, and polishing the other surface of the first silicon substrate. A method of manufacturing an SOI substrate which obtains an SOI structure in which a silicon portion is present in floating, comprising: patterning one surface of the first silicon substrate in a surface relief pattern to form the insulating portion thereon; Forming an opening at a position; forming a connection hole through the insulating portion at a second position; embedding the opening to form a first conductive portion; embedding the connection hole to form a connection portion; Forming a trench in the groove by forming a groove on the connecting portion, and then bonding the second silicon substrate to the other side of the first silicon substrate; A step of polishing the surface to form the silicone portion and a method of producing a SOI substrate comprising a step of forming a second conductive portion in the first and second position.