KR20010084438A - Method of fabricating semiconductor device with fuse - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device with a fuse is provided to prevent the exposure of a flowable oxide layer to the outside when forming a fuse box. CONSTITUTION: An insulated bit line fuse(201) is formed on a semiconductor substrate. The first insulating layer(202) is formed on the whole surface of the semiconductor substrate. An etching barrier(203) is formed on a predetermined region of the first insulating layer(202). The second insulating layer(204) is formed on the whole surface of the substrate. A fuse box(207) for exposing the etching barrier(203) is formed by patterning the second insulating layer(204). The first dummy metal pattern(210) is formed to cover a sidewall of the fuse box(207). The third insulating layer(213) is formed on the whole surface of the substrate. The first dummy metal pattern(210) and the etching barrier(203) are exposed by patterning the third insulating layer(213). The second dummy metal pattern(220) is formed to cover an upper face of the first dummy metal pattern(210) and a sidewall of the third insulating layer(213). The exposed etching barrier(203) is stripped.

Description

The manufacturing method of the semiconductor device which has a fuse {METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH FUSE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a fuse.

As semiconductor memory devices are highly integrated, the size of memory cells is reduced and the size of metal patterns is becoming smaller. When the existing interlayer insulating film is used on such a metal pattern, problems such as a bridge are formed between the metal wires due to void generation or poor planarization.

Recently, SOG (spin-on-glass) or flowable oxide (hereinafter referred to as FOX) is mainly used as an interlayer insulating material to improve this. FOX is a precursor of SiO ₂ that uses hydrogen silsesquioxane (HSQ) instead of siloxane, which is used in conventional SOG. Have. However, FOX is highly hygroscopic and there is a risk of outgassing, so when exposed to the outside, impurities such as moisture can penetrate the metal wiring and change the stress of the FOX layer.

Meanwhile, when a defective cell occurs in a semiconductor device, a fuse is formed for a repair technique for replacing the defective cell with a spare cell. The fuse should be cut using a laser or the like if necessary. Accordingly, in order to easily cut the fuse, an interlayer insulating layer stacked on the fuse is selectively etched to form a fuse box. At this time, FOX, which is an interlayer insulating film, is exposed to the sidewall of the fuse box.

1 is a cross-sectional view of a fuse box showing the problems of the prior art.

Referring to FIG. 1, in a method of forming a fuse box, an insulated bit line fuse 101 is formed on a semiconductor substrate. A first insulating layer 102 is formed to cover the bit line fuse 101. A metal contact plug 104 is formed in the first insulating layer 102 around the bit line fuse 101. A first metal wire 107 is formed on the first insulating layer 102 and the metal contact plug 104. The second insulating film 110 is formed by sequentially stacking the first plasma oxide film 110a, the FOX film 110b, and the second plasma oxide film 110c on the first metal wire 107. A via plug 113 is formed by filling a via hole penetrating the inside of the second insulating layer 110 with a conductive material, and forming a second metal wire on the second insulating layer 110 including the via plug 113. 114). A third plasma oxide film, which is a passivation layer 116, is formed on the second metal wire 114 and the second insulating film 110. The fuse box 120 is completed by etching the passivation layer 116, the second insulating layer 110, and the first insulating layer 102 on the bit line fuse 101 to a predetermined thickness.

As shown in FIG. 1, the FOX film 110b is exposed to the outside on the sidewall of the fuse box 120, and particularly, the corrosion of the metal or the stress change of the FOX film in the metal contact portion indicated by the reference F in FIG. 1. Defects will occur.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing a semiconductor device which can prevent the FOX film from being exposed to the outside when the fuse box is formed.

1 is a cross-sectional view of a semiconductor device manufactured according to an embodiment of the prior art.

2A through 2F are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

101, 201: bit line fuse 102, 202, 204: insulating film

203: etch stop film 104, 208: metal contact plug

107 and 209 first metal wiring 210 first dummy metal pattern

110a, 213a: first plasma oxide film 110b, 213b: FOX

110c and 213c: second plasma oxide film 113 and 218: via plug

114 and 219: second metal wiring 220: second dummy metal pattern

116, 222: protective film 120, 207: fuse box

(Configuration)

According to the present invention for achieving the above object, a manufacturing method of a semiconductor device having a fuse comprises the steps of: forming an insulated fuse line pattern on a semiconductor substrate; Forming a first insulating film on an entire surface of the semiconductor substrate including the fuse line pattern; Forming an etch stop layer on the predetermined region of the first insulating layer to cover the fuse line pattern; Forming a second insulating film on an entire surface of the resultant product on which the etch stop film is formed; Patterning the second insulating layer to form a fuse box exposing the etch stop layer; Forming a first dummy metal pattern covering sidewalls of the fuse box; Forming a third insulating film on an entire surface of the resultant product on which the first dummy metal pattern is formed; Patterning the third insulating layer to expose the first dummy metal pattern and the etch stop layer; And forming a second dummy metal pattern covering an upper surface of the first dummy metal pattern and a sidewall of the patterned third insulating layer adjacent to the first dummy metal pattern, and simultaneously removing the exposed etch stop layer. Include.

The etch stop layer is preferably formed of a polysilicon layer.

The third insulating film is preferably formed by stacking a first plasma oxide film, a FOX film, and a second plasma oxide film in order.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an insulated bit line fuse 201 is formed on a semiconductor substrate. A first insulating film 202, an etch stop film 203, and a second insulating film 204 are sequentially formed on the entire surface of the semiconductor substrate including the bit line fuse 201. The etch stop layer 203 is formed of a material having an etch selectivity with respect to the first insulating layer 202 and the second insulating layer 204, and is formed in a predetermined region on the bit line fuse 201. For example, in the case of a DRAM device, a plate conductive layer to be used as the etch stop layer 203 is formed in a predetermined region on the bit line fuse 201 when the plate electrode of the capacitor is formed in the cell region although not shown in the drawing. Form. Therefore, the etch stop layer 203 is formed of polysilicon which is widely used as a plate electrode, and the first insulating layer 202 and the second insulating layer 204 are formed of a silicon oxide layer.

The second insulating layer 204 and the first insulating layer 202 are sequentially etched to form a contact hole 206. At the same time during the etching process for forming the contact hole 206, the second insulating film 204 on the etch stop layer 203 is etched to form a fuse box 207 exposing the etch stop layer 203. .

Referring to FIG. 2B, the contact hole 206 is filled with a conductive material to form a metal contact plug 208. For example, tungsten is deposited to fill the contact hole 206 on the second insulating layer 204 including the contact hole 206, and then etched back to form the metal contact plug 208. ). In this case, a tungsten spacer 208a may be formed on the sidewall of the fuse box 207.

Referring to FIG. 2C, a first metal wiring material layer is deposited on the second insulating layer 204 including the metal contact plug 208 and then patterned to form a first metal wiring 209. When the first metal wiring 209 is formed by the patterning process, a first dummy metal pattern 210 covering the sidewall of the fuse box 207 is formed. During the patterning process, the first metal wire 209 and the etch stop layer 203 are etched to have an etching selectivity.

Referring to FIG. 2D, a third insulating layer 213 is formed on the entire surface of the resultant product on which the first metal wiring 209 and the first dummy metal pattern 210 are formed. The third insulating film 213 is preferably formed by laminating a first plasma oxide film 213a, a FOX film 213b, and a second plasma oxide film 213c in this order. The first and second plasma oxide films 213a and 213c prevent the FOX film 213b from directly contacting the metal lines 209. The third insulating layer 213 is patterned to expose the first dummy metal pattern 210 and the etch stop layer 203 in the fuse box 207, and at the same time, the predetermined first metal wiring 209 is exposed. A via hole 215 is formed that exposes the region.

Referring to FIG. 2E, a via plug 218 is formed by filling the via hole 215 in the third insulating layer 213 with a conductive material. The process of forming the via plug 218 may be omitted. A second metal wiring material layer is deposited and patterned on the third insulating layer 213 including the via hole 215 or the via plug 218. The second dummy metal pattern 220 is formed on the first dummy metal pattern 210 while forming the second metal wire 219 covering the via hole 215 or the via plug 218 by the patterning process. Form. In this case, the etch stop layer 203 is also etched. The first and second dummy metal patterns 210 and 220 formed in this manner prevent the third insulating layer 213 from being exposed to the outside through sidewalls of the fuse box 207. Therefore, it is possible to prevent impurities such as moisture from penetrating through the FOX film 213b of the third insulating film 213 or to generate stress in a subsequent process.

Referring to FIG. 2F, a plasma oxide film, which is a protective film 222, is formed on an entire surface of a semiconductor substrate including the second metal wire 219 and the second dummy metal pattern 220. The passivation layer 222 on the bit line fuse 201 is etched. Although not shown in FIG. 2F, if necessary, the first insulating film 202 on the bit line fuse 201 may be further etched to a predetermined thickness.

According to the present invention, a dummy metal pattern is formed around a fuse box to prevent exposure of a highly hygroscopic insulating film, such as a FOX film, to the outside, whereby impurities such as moisture penetrate and induce a defect in the metal wiring. .

Claims (3)

Forming an insulated fuse line pattern on the semiconductor substrate; Forming a first insulating film on an entire surface of the semiconductor substrate including the fuse line pattern; Forming an etch stop layer on the predetermined region of the first insulating layer to cover the fuse line pattern; Forming a second insulating film on an entire surface of the resultant product on which the etch stop film is formed; Patterning the second insulating layer to form a fuse box exposing the etch stop layer; Forming a first dummy metal pattern covering sidewalls of the fuse box; Forming a third insulating film on an entire surface of the resultant product on which the first dummy metal pattern is formed; Patterning the third insulating layer to expose the first dummy metal pattern and the etch stop layer; And Forming a second dummy metal pattern covering a top surface of the first dummy metal pattern and a sidewall of the patterned third insulating layer adjacent to the first dummy metal pattern, and simultaneously removing the exposed etch stop layer. The manufacturing method of the semiconductor device. The method of claim 1, The etch stop layer is a method of manufacturing a semiconductor device, characterized in that formed of a polysilicon film. The method of claim 1, And the third insulating film is formed by stacking a first plasma oxide film, a fluid oxide film, and a second plasma oxide film in sequence.