KR20070101655A - Semiconductor device having metal fuse - Google Patents

Abstract

A semiconductor device is provided to secure a stable operation of a metal fuse by improving a profile distribution of the metal fuse using an interlayer dielectric etching process for exposing an upper portion of the metal fuse to the outside. A semiconductor device includes a semiconductor substrate(110), lower conductive patterns, a first interlayer dielectric, metal lines, and a plurality of metal fuses. The lower conductive patterns(120) are formed on the substrate. The first interlayer dielectric(125) includes contact plugs connected to the lower conductive patterns. The metal lines(140ml) are formed on the contact plugs. The plurality of metal fuses(140mf) are made of the same material of that of the metal line. The height of the metal fuse is the same as that of the metal line. An upper portion of the metal fuse is exposed to the outside. The metal line adjacent to the metal fuse is extended to the metal fuse side.

Description

Semiconductor device having a metal fuse {Semiconductor Device Having Metal Fuse}

1 is a cross-sectional view illustrating a metal wiring of a semiconductor device including a metal fuse according to the prior art;

2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device and a metal fuse including a metal fuse according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a metal wiring of a semiconductor device including a metal fuse according to another embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a metal fuse.

As the degree of integration of memory semiconductor devices such as DRAM (Dynamic Random Access Memory) increases, it is increasingly difficult to obtain high quality products in the semiconductor manufacturing process. To solve this problem, a spare memory cell (redundancy cell) is adopted. The preliminary memory cell can increase the production yield by replacing the defective memory cell generated in the semiconductor manufacturing process.

After the process of processing the semiconductor substrate is completed, the defective memory cell can be found through quality inspection and a fuse electrically connected to the defective memory cell can be used to replace the spare circuit or the spare memory cell with the defective memory cell. .

As a material of a fuse used in such a circuit, polysilicon or a metal material may be used. A common fuse is formed at the same time as forming elements or wiring, so that no additional process is required. Accordingly, additional manufacturing production costs due to metal fuse formation may not increase.

1 is a cross-sectional view illustrating a metal wiring of a semiconductor device including a metal fuse according to the prior art.

Referring to FIG. 1, a semiconductor device including a metal fuse 40mf includes a semiconductor substrate 10, lower conductive patterns 20 formed on a cell region A of the semiconductor substrate 10, and lower conductive patterns ( A first interlayer insulating film 25 provided with contact plugs 30a connected to 20, metal wires 40ml on contact plugs 30a, vias connected to metal wires 40ml, A second interlayer insulating film 45 provided with 50a and a planarization insulating film 60 provided with an upper metal wiring 55 on the via 50a. Unexplained reference numerals 30 and 50 designate a contact hole and a via hole, respectively.

Since the metal fuse 40mf formed in the fuse region B is formed at the same time in the process of forming the metal lines 40ml, the metal fuse 40mf is provided at the same material and height as the metal lines 40ml. The upper portion of the metal fuse 40mf is exposed to be easily cut by a laser beam or the like.

The metal fuse 40mf formed at the same time as the metal wires 40ml is covered by the second interlayer insulating film 45 and the planarization insulating film 60, and then the upper portion of the fuse region B including the metal fuse 40mf. The planarization insulating layer 60 and the second interlayer insulating layer 45 may be selectively etched and exposed.

On the other hand, as the directivity and density of semiconductor elements increase, multilayer wiring is used. The protective film for applying the multilayer wiring is formed of a film excellent in flatness and coating performance. The presence of moisture in the protective film can cause the metal fuses to corrode. A silicon nitride film (SiN) having low hygroscopicity may be provided between the metal wire and the metal fuse to be used as a moisture absorption prevention film.

In the space between the metal wiring and the metal fuse which are adjacent to each other, as shown by the reference numeral C, the phenomenon that the insulating film is cut off may occur. As a result, in the etching process of exposing the upper portion of the fuse, the profile of the metal fuse adjacent to the metal wiring is deteriorated. The reduction of the profile spread of the metal fuse has a problem that causes the malfunction of the metal fuse.

In order to prevent the insulation of the insulation layer occurring in the space between the metal wiring and the metal fuse adjacent to each other, the space between the two may be reduced or the overall thickness of the insulation layer may be solved. However, reducing the space between the metal wiring and the metal fuse adjacent to each other is limited by the etching margin in the etching process exposing the upper portion of the metal fuse. In addition, increasing the thickness of the insulating film by increasing the deposition amount of the insulating film has a limitation because a fill margin for filling the via hole is reduced in a subsequent process for forming a via.

An object of the present invention is to provide a semiconductor device including a metal fuse that can improve the profile distribution of the metal fuse in the etching process of exposing the metal fuse.

In order to solve the above technical problem, the present invention provides a semiconductor device including a metal fuse. The semiconductor device has the same material and height as the semiconductor substrate, the lower conductive patterns formed on the semiconductor substrate, the first interlayer insulating film including the contact plugs connected to the lower conductive patterns, the metal wires formed on the contact plug and the metal wires. It includes a plurality of metal fuses exposed on the top. The metal wiring adjacent to the metal fuse is characterized in that it extends toward the metal fuse and protrudes.

Metal wires and metal fuses may be made of aluminum.

The metal wire adjacent to the metal fuse may be connected to the plurality of contact plugs.

The semiconductor device may further include a second interlayer insulating layer including vias connected to the metal lines and a planarization insulating layer including an upper metal line and an upper metal line formed on the via.

The second interlayer insulating film may be a film in which a pieteose film, a flow oxide film, and a pieteose film are sequentially stacked.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of films and regions are exaggerated for clarity. Also, if it is mentioned that the film is on another film or substrate, it may be formed directly on the other film or substrate or a third film may be interposed therebetween.

2A through 2F are cross-sectional views illustrating a method of forming a semiconductor device and a metal fuse including a metal fuse according to an exemplary embodiment of the present invention.

2A and 2B, a first interlayer insulating layer 125 is formed to cover the semiconductor substrate 110 including the cell region A and the fuse region B in which the lower conductive patterns 120 are formed. The lower conductive patterns 120 may be devices such as a transistor or a capacitor.

The first interlayer insulating layer 125 is patterned to form a contact hole 130 exposing predetermined regions of the lower conductive patterns 120 on the semiconductor substrate 110. The contact holes 130 are filled to form contact plugs 130a. The contact plugs 130a may be formed of tungsten (W).

Referring to FIG. 2C, a plurality of metal wires 140ml are formed on the first interlayer insulating layer 125 to connect the contact plugs 130a, and a plurality of fuses B are adjacent to the cell area A. The metal fuse 140mf is formed. The metal wires 140ml and the metal fuse 140mf may be formed of aluminum (Al).

Unlike the prior art, the metal wire 140ml adjacent to the metal fuse 140mf may extend to the metal fuse 140mf and be formed asymmetrically.

2D and 2E, after forming the second interlayer insulating layer 145 covering the metal lines 140ml and the metal fuse 140mf, the second interlayer insulating layer 145 is patterned to form the via holes 150. To form. The second interlayer insulating layer 145 may be formed of a film in which a PTEOS film (PETEOS: Plasma Enhanced TetraEthylOrthoSilicate), a flow oxide film (Fox), and a phyteose film are sequentially stacked. The reason for using the fluidized oxide film is that as described above in the related art, the protective film to which the multilayer wiring is applied can be formed into a film excellent in flatness and coating performance in terms of prevention of disconnection.

The via hole 150 is filled to form the via 150a. Via 150a may be formed of tungsten. An upper metal wiring 155 is formed in a predetermined region on the second interlayer insulating layer 145 including the vias 150.

The upper metal wire 155 may be formed of tungsten. The planarization insulating layer 160 covering the upper metal wiring 155 is formed.

Referring to FIG. 2F, the planarization insulating layer 160 and the second interlayer insulating layer 145 on the fuse region B are etched to expose the upper portion of the metal fuse 140mf. By exposing the upper portion of the metal fuse 140mf, the metal fuse 140mf can be easily cut by a laser beam or the like.

Unlike the prior art, the metal fuse 140mf and the metal wiring 140ml adjacent to each other are extended to the metal fuse 140mf and formed asymmetrically, so that the metal wire 140ml and the metal fuse 140mf are adjacent to each other. Space can be reduced. Accordingly, it is possible to prevent the second interlayer insulating film generated in the space between the metal wiring 140ml and the metal fuse 140mf which are adjacent to each other.

Accordingly, in the etching process of exposing the upper portion of the metal fuse 140mf, the profile of the metal fuse 140mf adjacent to the metal wire 140ml may be improved. Such improvement in profile distribution of the metal fuse 140mf may ensure stable operation of the metal fuse 140mf.

3 is a cross-sectional view illustrating a metal wiring of a semiconductor device including a metal fuse according to another embodiment of the present invention.

Referring to FIG. 3, a semiconductor device including a metal fuse 240mf includes a semiconductor substrate 210, lower conductive patterns 220 and lower conductive patterns formed on a cell region A of the semiconductor substrate 210. A first interlayer insulating film 225 including contact plugs 230a connected to 220, a metal wire 240ml formed on the contact plugs 230a, and a via 250a connected to the metal wire 240ml. The planarization insulating layer 260 including the second interlayer insulating layer 245 and the upper metal wiring 255 formed on the via 250a may be provided. Reference numerals 230 and 250, which are not described, indicate contact holes and via holes, respectively.

Since the metal fuse 240mf formed in the fuse region B is formed at the same time in the process of forming the metal wiring 240ml, the metal fuse 240mf may be provided at the same material and height as the metal wiring 240ml. The upper portion of the metal fuse 240mf may be exposed to be easily cut by a laser beam or the like.

In addition, the metal wire 240ml adjacent to the metal fuse 240mf may be connected to the plurality of contact plugs 230a. Accordingly, the process of forming the metal wiring 240ml and the metal fuse 240mf is simplified, and at the same time, the metal wiring 240ml and the metal wiring 240ml adjacent to each other are formed to extend toward the metal fuse 240mf, thereby adjoining each other. The space between the metal wire 240ml and the metal fuse 240mf can be reduced. Accordingly, it is possible to prevent the second interlayer insulating film 245 generated in the space between the metal wiring 240ml and the metal fuse 240mf which are adjacent to each other.

Therefore, in the etching process of exposing the upper portion of the metal fuse 240mf, the profile of the metal fuse 240mf adjacent to the metal wire 240ml may be improved. Such an improvement in profile distribution of the metal fuse 240mf may ensure stable operation of the metal fuse 240mf.

By using the metal wiring of the semiconductor device including the metal fuse as described above, the profile distribution of the metal fuse may be improved in the etching process of exposing the metal fuse. Accordingly, it is possible to provide a semiconductor device including a metal fuse capable of ensuring stable operation of the metal fuse.

As described above, according to the present invention, since the profile distribution of the metal fuse is improved in the etching process of exposing the metal fuse, it is possible to provide a semiconductor device including a metal fuse capable of ensuring stable operation of the metal fuse.

Claims (5)

Semiconductor substrates; Lower conductive patterns formed on the semiconductor substrate; A first interlayer insulating layer including contact plugs connected to the lower conductive patterns; Metal wires formed on the contact plugs; And It includes a plurality of metal fuses provided on the same material and the same height as the metal wires, the upper portion of the metal wires, wherein the metal wires adjacent to the metal fuses extend toward the metal fuses and includes a metal fuse Semiconductor device. The method of claim 1, And the metal wires and the metal fuse are made of aluminum. The method of claim 1, And the metal wire adjacent to the metal fuse is connected to a plurality of contact plugs. The method of claim 1, A second interlayer insulating film including vias connected to the metal wires; And And a planarization insulating film including an upper metal wiring and an upper metal wiring formed on the via. The method of claim 4, wherein The second interlayer insulating film is a semiconductor device comprising a metal fuse, characterized in that the film is a stack of a phyteose film, a flow oxide film and a phyteose film sequentially.

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