CN108598009A - Pad in wafer stage chip and preparation method thereof - Google Patents
Pad in wafer stage chip and preparation method thereof Download PDFInfo
- Publication number
- CN108598009A CN108598009A CN201810359963.9A CN201810359963A CN108598009A CN 108598009 A CN108598009 A CN 108598009A CN 201810359963 A CN201810359963 A CN 201810359963A CN 108598009 A CN108598009 A CN 108598009A
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- Prior art keywords
- layer
- metal
- wafer stage
- boss
- pad
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 72
- 238000002161 passivation Methods 0.000 claims abstract description 56
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000010949 copper Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000004411 aluminium Substances 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 208000037656 Respiratory Sounds Diseases 0.000 abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000523 sample Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical group [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses the pads and preparation method thereof in a kind of wafer stage chip.The pad includes the first passivation layer, the first metal layer, the second passivation layer, second metal layer.First passivation layer includes boss and flatness layer, and the flatness layer is located at the right and left of the boss.The first metal layer, is all covered in the flat layer surface of first passivation layer, and the first metal layer is concordant with the boss.Second passivation layer includes raceway groove, and the raceway groove is across the boss and the part the first metal layer of described boss the right and left.Second metal layer is filled in the raceway groove of second passivation layer, tie point of the second metal layer as the wafer stage chip and the external devices.The first metal layer is different with the material of the second metal layer.The metal layer of connection wafer stage chip internal circuit is not in metal wire crackle and leads to the abnormal situation of chip internal circuits function pad in the wafer stage chip and preparation method thereof on pad after needle survey.
Description
Technical field
The present invention relates to wafer stage chip technical field, more particularly to the pad in a kind of wafer stage chip and its making side
Method.
Background technology
Integrated circuit is a certain number of common electronic components, such as resistance, capacitance, transistor and these elements
Between line, the circuit with specific function integrated by semiconductor technology.
Current people are production of integrated circuits on chip, and chip is cut into from wafer.The manufacture of wafer
Process is exactly the manufacturing process of chip.After wafer manufactures, electrically connected with extraneous device by the pad on chip
It connects.The quality of pad quality directly affects the use of chip on wafer.
Chip performance in order to ensure encapsulation is normal, first has to carry out wafer test after wafer manufactures, wafer is surveyed
It tries to be exactly to survey each chip on wafer into the hand-manipulating of needle, the probe of the thin such as hair of installation on detector, on probe and chip under test
Contact pads, test its electrical characteristic.
Fig. 1 is a kind of wafer stage chip pad structure of the prior art.In the prior art in wafer stage chip pad structure
Probe contact point is located on aluminium (Al), and aluminium contacts up and down with metallic copper (Cu), when this structure needle is surveyed pressure can be conducted from aluminium to
Metallic copper is easy to cause metallic copper and metal wire crackle occurs after needle survey, since metallic copper connects internal circuit, so metallic copper
Crackle may lead to internal circuit open circuit and then chip functions are abnormal.
Being disclosed in the information of the background technology part, it is only intended to increase understanding of the overall background of the invention, without answering
It has been the prior art well known to persons skilled in the art when being considered as recognizing or imply that the information is constituted in any form.
Invention content
The purpose of the present invention is to provide the pads and preparation method thereof in a kind of wafer stage chip, after needle survey on pad
The metal layer of connection wafer stage chip internal circuit is not in metal wire crackle and causes chip internal circuits function abnormal
The case where.
To achieve the above object, the present invention provides the pads in a kind of wafer stage chip.The pad is the wafer
The connection unit of grade chip and external devices.The pad includes：First passivation layer, the first metal layer, the second passivation layer, second
Metal layer.First passivation layer includes boss and flatness layer, and the flatness layer is located at the right and left of the boss.The first metal layer
It is all covered in the flat layer surface of first passivation layer, the first metal layer is concordant with the boss, first gold medal
Belong to layer with the internal circuit of the wafer stage chip to be connected, forms conductive channel.Second passivation layer includes raceway groove, the raceway groove
Across the boss and the part the first metal layer of described boss the right and left.Second metal layer is filled in second passivation
In the raceway groove of layer, tie point of the second metal layer as the wafer stage chip and the external devices.First gold medal
It is different with the material of the second metal layer to belong to layer.
In a preferred embodiment, the material of first passivation layer and second passivation layer is titanium dioxide
Silicon.
In a preferred embodiment, the material of the first metal layer is copper.
In a preferred embodiment, the material of the second metal layer is aluminium.
The present invention also provides a kind of production methods of the pad in wafer stage chip.It includes the following steps：It is heavy to provide
The substrate of the first passivation layer is accumulated；First passivation layer is patterned to form boss on first passivation layer；In shape
At the first metal is deposited on the first passivation layer after the boss, the first metal layer identical with the boss height is formed；
The second passivation layer is deposited on the first metal layer；Second passivation layer is patterned to be formed on second passivation layer
Raceway groove, the raceway groove is across the boss and first metal of part of described boss the right and left；Is deposited in the raceway groove
Two metals, if there is the second metal deposit of part in second passivation layer surface, then the second metal of the part is carved
Eating away.First metal is different with the bimetallic material.
In a preferred embodiment, the material of first passivation layer and second passivation layer is titanium dioxide
Silicon.
In a preferred embodiment, the material of the first metal layer is copper.
In a preferred embodiment, the material of the second metal layer is aluminium.
Compared with prior art, the pad and preparation method thereof in wafer stage chip according to the present invention, have has as follows
Beneficial effect：
It is not merely the first metal layer below second metal of the pad, further includes first blunt among the first metal layer
Change layer, when needle is surveyed, the first passivation layer can replace second metal layer to disperse a part of pressure, connection wafer stage chip internal circuit
The first metal layer hardly experiences needle measuring pressure, thus the first metal layer is not in metal wire crackle and causes in chip
The abnormal situation of portion's circuit function.
Description of the drawings
Fig. 1 is a kind of wafer stage chip pad structure of the prior art.
Fig. 2 is the pad structure of wafer stage chip according to an embodiment of the present invention.
Fig. 3 is the pad fabrication processing figure of wafer stage chip according to an embodiment of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in detail, it is to be understood that the guarantor of the present invention
Shield range is not restricted by specific implementation.
Unless otherwise explicitly stated, otherwise in entire disclosure and claims, term " comprising " or its change
It changes such as "comprising" or " including " etc. and will be understood to comprise stated element or component, and do not exclude other members
Part or other component parts.
Fig. 2 is the pad structure of wafer stage chip according to an embodiment of the present invention.
Preferably, the pad structure in the wafer stage chip includes the first passivation layer, the first metal layer, the second passivation
Layer, second metal layer.
Preferably, first passivation layer is silica (SiO2) layer.First passivation layer includes boss and flatness layer,
The flatness layer is located at the right and left of the boss.
Preferably, the first metal layer is layers of copper, is all covered in the flat layer surface of first passivation layer, described
The first metal layer is concordant with the boss, and the layers of copper is connected with the internal circuit of the wafer stage chip, is formed conductive logical
Road；
Preferably, the second passivation layer is silicon dioxide layer, including raceway groove.The raceway groove is across boss and boss the right and left
Part layers of copper.
Preferably, second metal layer is aluminium layer, is filled in the raceway groove of second passivation layer, described in the aluminium layer conduct
The tie point of wafer stage chip and the external devices.
There is silicon dioxide layer, when needle is surveyed, probe acts in the pad structure of the wafer stage chip below aluminium layer
Aluminium layer, silicon dioxide layer can sponge a part of pressure, and layers of copper is almost not felt by pressure, therefore it is possible to prevente effectively from metal wire
(copper) crackle, to which the function of chip will not be damaged.
Fig. 3 is the pad fabrication processing figure of wafer stage chip according to an embodiment of the present invention.Preferably, institute
The manufacture craft for stating pad includes：
Step 1, the substrate that deposited the first passivation layer (preferably, selecting silica) is provided, in first passivation
Photoresist is coated on layer and is exposed, is developed, etching, removing extra photoresist to be formed on first passivation layer
Boss.
Step 2, the first metal (preferably, selecting copper) is deposited on the first passivation layer after forming the boss and is ground
The first extra metal is ground to form the first metal layer concordant with boss.
Step 3, the second passivation layer (preferably, select silica) is deposited on the first metal layer, described the
Photoresist is coated on two passivation layers and is exposed, is developed, etching, removing extra photoresist in second passivation layer
Upper formation raceway groove, the raceway groove is across the boss and first metal of part of described boss the right and left.
Step 4, the second metal (preferably, aluminium) is deposited in the raceway groove, and light is coated on second metal
Photoresist is simultaneously exposed, is developed, etching, removing extra photoresist so that not having the second gold medal above second passivation layer
Belong to covering.
In conclusion the technics comparing of pad of the present invention is simple, by al deposition on silicon dioxide layer, in needle
Layers of copper hardly experiences needle measuring pressure when survey, leads to chip internal circuits function due to without copper lines crackle
Abnormal situation.
The description of the aforementioned specific exemplary embodiment to the present invention is in order to illustrate and illustration purpose.These descriptions
It is not wishing to limit the invention to disclosed precise forms, and it will be apparent that according to the above instruction, can much be changed
And variation.The purpose of selecting and describing the exemplary embodiment is that explaining the specific principle of the present invention and its actually answering
With so that those skilled in the art can realize and utilize the present invention a variety of different exemplary implementation schemes and
Various chooses and changes.The scope of the present invention is intended to be limited by claims and its equivalents.
Claims (8)
1. the pad in a kind of wafer stage chip, the pad is the wafer stage chip and the connection unit of external devices,
It is characterized in that, the pad includes：
First passivation layer, including boss and flatness layer, the flatness layer are located at the right and left of the boss；
The first metal layer is all covered in the flat layer surface of first passivation layer, the first metal layer and the boss
Concordantly, the first metal layer is connected with the internal circuit of the wafer stage chip, forms conductive channel；
Second passivation layer, including raceway groove, the raceway groove is across the boss and first gold medal of part of described boss the right and left
Belong to layer；And
Second metal layer is filled in the raceway groove of second passivation layer, and the second metal layer is as the wafer stage chip
With the tie point of the external devices,
Wherein, the first metal layer is different with the material of the second metal layer.
2. the pad in wafer stage chip according to claim 1, which is characterized in that first passivation layer and described
The material of two passivation layers is silica.
3. the pad in wafer stage chip according to claim 1, which is characterized in that the material of the first metal layer is
Copper.
4. the pad in wafer stage chip according to claim 1, which is characterized in that the material of the second metal layer is
Aluminium.
5. a kind of production method of the pad in wafer stage chip, which is characterized in that include the following steps：
The substrate that deposited the first passivation layer is provided；
First passivation layer is patterned to form boss on first passivation layer；
The first metal is deposited on the first passivation layer after forming the boss, forms the first gold medal identical with the boss height
Belong to layer；
The second passivation layer is deposited on the first metal layer；
Second passivation layer is patterned to forming raceway groove on second passivation layer, the raceway groove across the boss and
First metal of part of described boss the right and left；And
The second metal is deposited in the raceway groove, if there is the second metal deposit of part in second passivation layer surface, that
Second metal etch of the part is fallen,
Wherein, first metal is different with the bimetallic material.
6. the production method of the pad in wafer stage chip according to claim 5, which is characterized in that first passivation
The material of layer and second passivation layer is silica.
7. the production method of the pad in wafer stage chip according to claim 5, which is characterized in that first metal
The material of layer is copper.
8. the production method of the pad in wafer stage chip according to claim 5, which is characterized in that second metal
The material of layer is aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810359963.9A CN108598009A (en) | 2018-04-20 | 2018-04-20 | Pad in wafer stage chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810359963.9A CN108598009A (en) | 2018-04-20 | 2018-04-20 | Pad in wafer stage chip and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108598009A true CN108598009A (en) | 2018-09-28 |
Family
ID=63614313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810359963.9A Pending CN108598009A (en) | 2018-04-20 | 2018-04-20 | Pad in wafer stage chip and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108598009A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1519923A (en) * | 2003-01-30 | 2004-08-11 | 恩益禧电子股份有限公司 | Semiconductor device and its mfg. method |
| CN1612333A (en) * | 2003-10-29 | 2005-05-04 | 台湾积体电路制造股份有限公司 | Bonding pad structure |
| CN1941344A (en) * | 2005-09-27 | 2007-04-04 | 台湾积体电路制造股份有限公司 | Bond pad structure |
| CN101494212A (en) * | 2008-01-04 | 2009-07-29 | 三星电子株式会社 | Bonding pad structure and semiconductor device including the bonding pad structure |
-
2018
- 2018-04-20 CN CN201810359963.9A patent/CN108598009A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1519923A (en) * | 2003-01-30 | 2004-08-11 | 恩益禧电子股份有限公司 | Semiconductor device and its mfg. method |
| CN1612333A (en) * | 2003-10-29 | 2005-05-04 | 台湾积体电路制造股份有限公司 | Bonding pad structure |
| CN1941344A (en) * | 2005-09-27 | 2007-04-04 | 台湾积体电路制造股份有限公司 | Bond pad structure |
| CN101494212A (en) * | 2008-01-04 | 2009-07-29 | 三星电子株式会社 | Bonding pad structure and semiconductor device including the bonding pad structure |
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Application publication date: 20180928 |
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