JPH05160183A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH05160183A JPH05160183A JP32493391A JP32493391A JPH05160183A JP H05160183 A JPH05160183 A JP H05160183A JP 32493391 A JP32493391 A JP 32493391A JP 32493391 A JP32493391 A JP 32493391A JP H05160183 A JPH05160183 A JP H05160183A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- wire bonding
- semiconductor chip
- wire
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lasers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特に、半導体チップと該半導体チップを固定した
リードフレームまたはセラミックパッケージのリードま
たはメタライズパターンとを接続するワイヤボンディン
グに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to wire bonding for connecting a semiconductor chip to a lead frame or a ceramic package lead or metallized pattern to which the semiconductor chip is fixed.
【０００２】近年の半導体装置は、多ピン化が進んで上
記ワイヤボンディングのワイヤが相互間で狭くなる傾向
にあり、それに伴いワイヤが不要な接触を起こして短絡
するというトラブルが発生し易くなっている。In recent semiconductor devices, the number of pins has been increased, and the wires for wire bonding have a tendency to become narrower between them, and as a result, troubles such as unnecessary contact of the wires and short-circuiting are likely to occur. There is.
【０００３】本発明はそのトラブルを防止しようとする
ものである。The present invention is intended to prevent the trouble.
【０００４】[0004]
【従来の技術】多ピン化が進んだ半導体装置の製造にお
いて、半導体チップと該半導体チップを固定したリード
フレームまたはセラミックパッケージのリードまたはメ
タライズパターンとを接続するワイヤボンディングで
は、ループカーブが発生した際にワイヤが隣接リードに
接触する場合がある。2. Description of the Related Art In the manufacture of a semiconductor device having a large number of pins, in wire bonding for connecting a semiconductor chip to a lead frame or a ceramic package lead or metallized pattern to which the semiconductor chip is fixed, when a loop curve occurs, In some cases, the wire may contact adjacent leads.
【０００５】この接触はワイヤの電気的短絡を招くの
で、それを防止する方策として、従来は、ワイヤボンデ
ィング箇所を残してリードまたはメタライズパターンを
絶縁膜で被覆しておくという方法がある。Since this contact causes an electrical short circuit of the wire, conventionally, there is a method of covering the lead or the metallized pattern with an insulating film while leaving the wire bonding portion as a measure to prevent it.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、リード
フレームでは、その製造をプレス加工で行うのでリード
の傾きがあるため、上記ワイヤボンディング箇所を残し
た絶縁膜の形成が困難である。However, since the lead frame is manufactured by press working in the lead frame, it is difficult to form the insulating film leaving the wire bonding portion.
【０００７】また、上記絶縁膜を設けたリードフレーム
またはセラミックパッケージは、リードまたはメタライ
ズパターン上のワイヤボンディング箇所が予め定められ
ているので、ワイヤが半導体チップのエッジに接触した
りワイヤ相互間が接触したりした際に、それを回避する
ように上記ワイヤボンディング箇所を変更しようとして
も、その変更を行うことができない。ちなみに、上記絶
縁膜がない場合は、ワイヤボンディングのプログラム変
更により、上記ワイヤボンディング箇所の変更を適宜に
行うことができる。Further, in the lead frame or ceramic package provided with the above-mentioned insulating film, the wire bonding portion on the lead or the metallized pattern is predetermined, so that the wire contacts the edge of the semiconductor chip or the wires contact each other. However, even if the wire bonding portion is changed so as to avoid it, the change cannot be made. By the way, when the insulating film is not provided, the wire bonding location can be changed appropriately by changing the wire bonding program.
【０００８】そこで本発明は、半導体装置の製造方法に
係り、半導体チップと該半導体チップを固定したリード
フレームまたはセラミックパッケージのリードまたはメ
タライズパターンとを接続するワイヤボンディングに関
し、ワイヤの隣接リードとの接触による短絡を防止する
ためリードを被覆する絶縁膜が容易に形成でき、且つ、
リードまたはメタライズパターンのワイヤボンディング
箇所を容易に変更できるようにすることを目的とする。Therefore, the present invention relates to a method for manufacturing a semiconductor device, and relates to wire bonding for connecting a semiconductor chip to a lead frame or a ceramic package lead or metallized pattern to which the semiconductor chip is fixed, and to contact a wire with an adjacent lead. An insulating film that covers the leads can be easily formed to prevent a short circuit due to
The purpose of the present invention is to make it possible to easily change the wire bonding portion of the lead or the metallized pattern.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体装置の製造方法は、半導体チッ
プを固定するリードフレームまたはセラミックパッケー
ジは、ワイヤボンディングにより該半導体チップと接続
するリードまたはメタライズパターンをワイヤボンディ
ング箇所も含めて絶縁膜で被覆しておき、前記ワイヤボ
ンディングの直前に、該絶縁膜の一部を選択的に除去す
るレーザビームの照射により該リードまたはメタライズ
パターンのワイヤボンディング箇所を表出させることを
特徴としている。In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a lead frame for fixing a semiconductor chip or a ceramic package has a lead or a lead connected to the semiconductor chip by wire bonding. The metallized pattern is covered with an insulating film including the wire bonding portion, and immediately before the wire bonding, the wire bonding portion of the lead or the metallized pattern is irradiated with a laser beam that selectively removes a part of the insulating film. It is characterized by expressing.
【００１０】[0010]
【作用】上記絶縁膜は、上記ワイヤボンディングのワイ
ヤの隣接リードまたは隣接メタライズパターンとの接触
による短絡を防止するため上記リードまたはメタライズ
パターンを被覆するのものであるが、ワイヤボンディン
グ箇所を残して被覆する必要がないので形成が容易であ
る。The insulating film covers the lead or the metallized pattern in order to prevent a short circuit due to the contact of the wire of the wire bonding with the adjacent lead or the adjacent metallized pattern. It is easy to form because it does not need to be formed.
【００１１】そして、ワイヤボンディングは、その以前
に上記絶縁膜の一部を除去してリードまたはメタライズ
パターンのワイヤボンディング箇所を表出させてあるの
で問題なく実行できる。The wire bonding can be carried out without any problem because the wire bonding portion of the lead or the metallized pattern is exposed by removing a part of the insulating film before that.
【００１２】また、上記リードまたはメタライズパター
ンのワイヤボンディング箇所の表出が上記ワイヤボンデ
ィングの直前に上記レーザビームの照射によって行われ
るので、そのワイヤボンディング箇所を容易に変更でき
る。この変更は、先に述べたように、ワイヤが半導体チ
ップのエッジに接触したりワイヤ相互間が接触したりす
るトラブルの回避に役立つ。Further, since the wire bonding portion of the lead or metallized pattern is exposed by the irradiation of the laser beam immediately before the wire bonding, the wire bonding portion can be easily changed. This modification is useful for avoiding the trouble that the wires come into contact with the edges of the semiconductor chip or between the wires as described above.
【００１３】[0013]
【実施例】以下本発明の実施例について図１を用いて説
明する。この実施例はリードフレームを例にとった場合
であり、セラミックパッケージの場合も要部は同じであ
る。Embodiments of the present invention will be described below with reference to FIG. In this embodiment, the lead frame is taken as an example, and the main part is the same in the case of the ceramic package.
【００１４】図１において、図１(a) は半導体チップを
リードフレームに固定した状態を示し、１は半導体チッ
プ、２はリードフレームのダイステージ、３はリードフ
レームのリード、４はリード３を被覆する絶縁膜であ
る。図１(a) の状態ではリード３のワイヤボンディング
箇所も絶縁膜４で被覆されているため、半導体チップ１
とリード３とを接続するワイヤボンディングができな
い。絶縁膜４は、例えば厚さ10μm 程度のポリイミド膜
であり、ワイヤボンディング箇所を残した被覆にする必
要がないので容易に形成できる。In FIG. 1, FIG. 1A shows a state in which a semiconductor chip is fixed to a lead frame, 1 is a semiconductor chip, 2 is a lead frame die stage, 3 is a lead frame lead, and 4 is a lead 3. It is an insulating film to cover. In the state of FIG. 1 (a), the wire bonding portion of the lead 3 is also covered with the insulating film 4, so that the semiconductor chip 1
Wire bonding that connects the lead 3 and the lead 3 cannot be performed. The insulating film 4 is, for example, a polyimide film having a thickness of about 10 μm and can be easily formed because it is not necessary to cover the wire bonding portions.
【００１５】図１(b) はリード３のワイヤボンディング
箇所を表出させるレーザビームの照射を示し、５がレー
ザビーム、６がワイヤボンディング箇所である。レーザ
ビーム５は外径が例えば 100〜200 μm 程度で照射位置
を適宜に移動させることができ、レーザには例えばＣＯ
2 レーザなどを用いる。レーザビーム５が照射された箇
所は絶縁膜４が除去されてリード３が表出しワイヤボン
ディング箇所６となる。従って、リード３のワイヤボン
ディング箇所６を容易に変更することができる。そし
て、ワイヤボンディング箇所６の表出により半導体チッ
プ１とリード３とを接続するワイヤボンディングができ
る状態となる。FIG. 1 (b) shows the irradiation of the laser beam for exposing the wire bonding portion of the lead 3, where 5 is the laser beam and 6 is the wire bonding portion. The laser beam 5 has an outer diameter of, for example, about 100 to 200 μm, and the irradiation position can be appropriately moved.
2 Use a laser or the like. The insulating film 4 is removed at the portion irradiated with the laser beam 5, and the lead 3 becomes exposed and becomes the wire bonding portion 6. Therefore, the wire bonding portion 6 of the lead 3 can be easily changed. Then, the wire bonding connecting the semiconductor chip 1 and the lead 3 is made possible by exposing the wire bonding portion 6.
【００１６】図１(c) は半導体チップ１とリード３とを
接続するワイヤボンディングを示し、７がワイヤであ
る。ワイヤ７は一端が半導体チップ１にボンディングさ
れ他端がリード３のワイヤボンディング箇所６にボンデ
ィングされる。FIG. 1 (c) shows wire bonding for connecting the semiconductor chip 1 and the leads 3, and 7 is a wire. The wire 7 has one end bonded to the semiconductor chip 1 and the other end bonded to the wire bonding portion 6 of the lead 3.
【００１７】上述から容易に理解されるように、ワイヤ
７がループカーブにより隣接のリード３接触しても電気
的短絡を起こすことはない。図１(a) におけるリード３
の絶縁膜４による被覆を図１(d1)または(d2)のようにリ
ード３の側面乃至裏面まで施すとより一層確実である。As can be easily understood from the above, even if the wire 7 contacts the adjacent lead 3 due to the loop curve, no electrical short circuit occurs. Lead 3 in Figure 1 (a)
It is more reliable to cover the side surface or the back surface of the lead 3 with the insulating film 4 as shown in FIG. 1 (d1) or (d2).
【００１８】また、当初目論んだリード３のワイヤボン
ディング箇所６により、ワイヤ７が半導体チップ１のエ
ッジに接触したりワイヤ７相互間が接触したりした際に
は、次回からそれを回避するようにワイヤボンディング
箇所６を変更することができる。その変更は、レーザビ
ーム５の照射位置変更とワイヤボンディングのプログラ
ム変更により容易に行うことができる。Further, when the wire 7 comes into contact with the edge of the semiconductor chip 1 or the wires 7 come into contact with each other due to the initially intended wire bonding portion 6 of the lead 3, it should be avoided from the next time. The wire bonding location 6 can be changed. The change can be easily performed by changing the irradiation position of the laser beam 5 and changing the program of wire bonding.
【００１９】なお、上述の実施例は半導体チップ１の固
定対象がリードフレームの場合であるが、セラミックパ
ッケージの場合であってもリード３がメタライズパター
ンに変わって同様になし得ることは改めて説明するまで
もない。In the above-mentioned embodiment, the semiconductor chip 1 is fixed to the lead frame, but it will be explained again that the lead 3 can be changed to a metallized pattern even in the case of a ceramic package. There is no end.
【００２０】[0020]
【発明の効果】以上説明したように本発明によれば、半
導体装置の製造方法に係り、半導体チップと該半導体チ
ップを固定したリードフレームまたはセラミックパッケ
ージのリードまたはメタライズパターンとを接続するワ
イヤボンディングに関し、ワイヤの隣接リードまたは隣
接メタライズパターンとの接触による短絡を防止するた
めリードを被覆する絶縁膜が容易に形成でき、且つ、リ
ードまたはメタライズパターンのワイヤボンディング箇
所を容易に変更できて、半導体装置の多ピン化に伴い相
互間隔が狭くなるワイヤの不要な接触により発生する短
絡トラブルを防止する措置が容易になり、半導体装置の
多ピン化進展に寄与するところが大である。As described above, the present invention relates to a method for manufacturing a semiconductor device, and more particularly to wire bonding for connecting a semiconductor chip to a lead frame or a ceramic package lead or metallized pattern to which the semiconductor chip is fixed. In order to prevent a short circuit due to contact between a wire and an adjacent lead or an adjacent metallized pattern, an insulating film for covering the lead can be easily formed, and a wire bonding portion of the lead or the metallized pattern can be easily changed. With the increase in the number of pins, it is easy to take measures to prevent a short-circuit trouble caused by unnecessary contact of wires, which becomes narrower in mutual spacing, and this largely contributes to the progress in increasing the number of pins in a semiconductor device.
【図１】 実施例を説明するための側面図FIG. 1 is a side view for explaining an embodiment.
１ 半導体チップ ２ リードフレームのダイステージ ３ リードフレームのリード ４ リードを被覆する絶縁膜 ５ レーザビーム ６ ワイヤボンディング箇所 ７ ワイヤ 1 Semiconductor Chip 2 Die Stage of Lead Frame 3 Lead of Lead Frame 4 Insulating Film Covering Lead 5 Laser Beam 6 Wire Bonding Site 7 Wire
Claims (2)
は、ワイヤボンディングにより該半導体チップと接続す
るリードをワイヤボンディング箇所も含めて絶縁膜で被
覆しておき、 前記ワイヤボンディングの直前に、該絶縁膜の一部を選
択的に除去するレーザビームの照射により該リードのワ
イヤボンディング箇所を表出させることを特徴とする半
導体装置の製造方法。1. A lead frame for fixing a semiconductor chip has a lead for connecting to the semiconductor chip, which includes a wire bonding portion, covered with an insulating film by wire bonding. Immediately before the wire bonding, A method of manufacturing a semiconductor device, which comprises exposing a wire bonding portion of the lead by irradiating a laser beam for selectively removing a part thereof.
ケージは、ワイヤボンディングにより該半導体チップと
接続するメタライズパターンをワイヤボンディング箇所
も含めて絶縁膜で被覆しておき、 前記ワイヤボンディングの直前に、該絶縁膜の一部を選
択的に除去するレーザビームの照射により該メタライズ
パターンのワイヤボンディング箇所を表出させることを
特徴とする半導体装置の製造方法。2. A ceramic package for fixing a semiconductor chip, wherein a metallized pattern connected to the semiconductor chip by wire bonding is covered with an insulating film including a wire bonding portion, and the insulating film is provided immediately before the wire bonding. A method for manufacturing a semiconductor device, characterized in that the wire bonding portion of the metallized pattern is exposed by irradiation with a laser beam for selectively removing a part of the metallized pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32493391A JPH05160183A (en) | 1991-12-10 | 1991-12-10 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32493391A JPH05160183A (en) | 1991-12-10 | 1991-12-10 | Fabrication of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05160183A true JPH05160183A (en) | 1993-06-25 |
Family
ID=18171238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32493391A Withdrawn JPH05160183A (en) | 1991-12-10 | 1991-12-10 | Fabrication of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05160183A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999043032A3 (en) * | 1998-02-20 | 1999-11-25 | Siemens Ag | sEMICONDUCTOR COMPONENT WITH A STRUCTURED LEADFRAME AND METHOD FOR PRODUCING THE SAME |
-
1991
- 1991-12-10 JP JP32493391A patent/JPH05160183A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999043032A3 (en) * | 1998-02-20 | 1999-11-25 | Siemens Ag | sEMICONDUCTOR COMPONENT WITH A STRUCTURED LEADFRAME AND METHOD FOR PRODUCING THE SAME |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |