JPH065734A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPH065734A
JPH065734A JP16088292A JP16088292A JPH065734A JP H065734 A JPH065734 A JP H065734A JP 16088292 A JP16088292 A JP 16088292A JP 16088292 A JP16088292 A JP 16088292A JP H065734 A JPH065734 A JP H065734A
Authority
JP
Japan
Prior art keywords
integrated circuit
signal
circuit package
pad
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP16088292A
Other languages
Japanese (ja)
Inventor
Hisashi Yamanobuta
恒 山信田
Michihiro Takahashi
道広 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP16088292A priority Critical patent/JPH065734A/en
Publication of JPH065734A publication Critical patent/JPH065734A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate necessity of modifying signal wires after an integrated circuit package is mounted on a device board and providing a signal pad for an electric test on the board by exposing a signal pattern wire for connecting a semiconductor integrated circuit to outer leads on the surface of the package. CONSTITUTION:A signal wire of a semiconductor integrated circuit 2 placed on an integrated circuit package 1 is connected to a signal pattern wire 1 of the package 1. A signal pattern wire 11 is once output to a surface of the package 1 before it is connected to outer lead 10 to form a signal pad 12. The pad 12 is formed of an inner signal pad 21, an outer signal pad 20 and a connecting wire 22. When connection of a signal is altered after the package is mounted on a device board, the wire 22 is cut, and a signal wire may be newly connected from the pad 20 or 21.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路を搭載
する集積回路パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit package mounting a semiconductor integrated circuit.

【0002】[0002]

【従来の技術】従来の集積回路パッケージ1は、図2に
示すように、半導体集積回路2と外部リード10の間を
接続する信号パタン線11は、集積回路パッケージ1の
内層を通っていた。
2. Description of the Related Art In a conventional integrated circuit package 1, as shown in FIG. 2, a signal pattern line 11 connecting a semiconductor integrated circuit 2 and an external lead 10 passes through an inner layer of the integrated circuit package 1.

【0003】[0003]

【発明が解決しようとする課題】この従来の集積回路パ
ッケージでは、半導体集積回路と外部リードとの間を接
続する信号パタン線が集積回路パッケージの内層を通っ
ているために、この集積回路パッケージを装置基板上に
実装した後の信号線の改造や電気試験の為の信号線への
電圧印加を行なう為に装置基板上に専用の信号パッドを
設ける必要があり、高密度実装をさまたげるという問題
点があった。
In this conventional integrated circuit package, since the signal pattern line connecting the semiconductor integrated circuit and the external lead passes through the inner layer of the integrated circuit package, the integrated circuit package is The problem is that it is necessary to provide a dedicated signal pad on the device board in order to modify the signal line after mounting it on the device board or to apply voltage to the signal line for electrical testing, which impedes high-density mounting. was there.

【0004】[0004]

【課題を解決するための手段】本発明の集積回路パッケ
ージは、半導体集積回路と外部リードの間を接続する信
号パタン線が集積回路パッケージの表面に露出してい
る。
In the integrated circuit package of the present invention, the signal pattern line connecting between the semiconductor integrated circuit and the external lead is exposed on the surface of the integrated circuit package.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0006】図1(A)は本発明の一実施例の集積回路
パッケージの断面図である。集積回路パッケージ1に搭
載された半導体集積回路2の信号線は、ボンディングワ
イヤー3によって集積回路パッケージ1の信号パタン線
11に接続される。信号パタン線11は、集積回路パッ
ケージ1の内層を通り、外部リード10に接続する前に
一旦集積回路パッケージ1の表面に出て信号パッド12
を形成している。
FIG. 1A is a sectional view of an integrated circuit package according to an embodiment of the present invention. The signal line of the semiconductor integrated circuit 2 mounted on the integrated circuit package 1 is connected to the signal pattern line 11 of the integrated circuit package 1 by the bonding wire 3. The signal pattern line 11 passes through the inner layer of the integrated circuit package 1 and once comes out on the surface of the integrated circuit package 1 before being connected to the external lead 10.
Is formed.

【0007】なお、半導体集積回路2と集積回路パッケ
ージ1との信号線の接続は、必ずしもボンディングワイ
ヤー3によって行なう必要はない。
The connection of the signal line between the semiconductor integrated circuit 2 and the integrated circuit package 1 does not necessarily have to be performed by the bonding wire 3.

【0008】次に、図1(B)は、図1(A)に示した
実施例集積回路パッケージ1における信号パッド12の
構成例である。
Next, FIG. 1B shows an example of the structure of the signal pad 12 in the embodiment integrated circuit package 1 shown in FIG.

【0009】本信号パッド12は、半導体集積回路2と
信号パタン線11を介して接続する内部信号パッド21
と、集積回路パッケージ1の外部リード10と信号パタ
ン線11を介して接続する外部信号パッド20と、内部
信号パッド21と外部信号パッド20の間を接続する接
続線22からなる。
The signal pad 12 is an internal signal pad 21 connected to the semiconductor integrated circuit 2 via a signal pattern line 11.
And an external signal pad 20 connected to the external lead 10 of the integrated circuit package 1 via the signal pattern line 11, and a connection line 22 connecting the internal signal pad 21 and the external signal pad 20.

【0010】本発明の集積回路パッケージを装置基板に
実装した後に、改造が必要となり、信号の接続を変更す
る場合には、接続線22を切断し、外部信号パッド20
もしくは、内部信号パッド21から新たに信号線を接続
する。
After the integrated circuit package of the present invention is mounted on the device substrate, modification is required. When changing the signal connection, the connection line 22 is cut and the external signal pad 20 is used.
Alternatively, a new signal line is connected from the internal signal pad 21.

【0011】又、装置基板に実装した後に、電気試験を
行なう場合も、外部信号パッド20又は、内部信号パッ
ド21を介して外部より信号を印加したり、半導体集積
回路の信号を観測することが可能である。
Also, when an electrical test is carried out after mounting on the device substrate, it is possible to apply a signal from the outside through the external signal pad 20 or the internal signal pad 21 and observe the signal of the semiconductor integrated circuit. It is possible.

【0012】[0012]

【発明の効果】以上説明したように本発明は、半導体集
積回路と外部リードの間を接続する信号パタン線が集積
回路パッケージの表面に露出しているので、この集積回
路パッケージを装置基板上に実装した後の信号線の改造
や電気試験の為の信号パッドを装置基板上に設ける必要
がなくなり、高密度実装が可能になるという結果を有す
る。
As described above, according to the present invention, since the signal pattern line connecting the semiconductor integrated circuit and the external lead is exposed on the surface of the integrated circuit package, this integrated circuit package is mounted on the device substrate. The result is that it is not necessary to provide a signal pad for modifying the signal line after mounting and a signal pad for an electrical test on the device substrate, which enables high-density mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

【図2】従来例の断面図である。FIG. 2 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

1 集積回路パッケージ 2 半導体集積回路 3 ボンディングワイヤー 10 外部リード 11 信号パタン線 12 信号パッド 20 外部信号パッド 21 内部信号パッド 22 接続線 1 Integrated Circuit Package 2 Semiconductor Integrated Circuit 3 Bonding Wire 10 External Lead 11 Signal Pattern Line 12 Signal Pad 20 External Signal Pad 21 Internal Signal Pad 22 Connection Line

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路と外部リードの間を接続
する信号パタン線が集積回路パッケージの表面に露出し
ていることを特徴とする集積回路パッケージ。
1. An integrated circuit package, wherein a signal pattern line connecting between a semiconductor integrated circuit and an external lead is exposed on a surface of the integrated circuit package.
【請求項2】 前記信号パタン線の外部からの切断及び
接続を可能とする信号パッドを集積回路パッケージの表
面に有することを特徴とする請求項1記載の集積回路パ
ッケージ。
2. The integrated circuit package according to claim 1, further comprising a signal pad on the surface of the integrated circuit package that enables disconnection and connection of the signal pattern line from the outside.
JP16088292A 1992-06-19 1992-06-19 Integrated circuit package Withdrawn JPH065734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16088292A JPH065734A (en) 1992-06-19 1992-06-19 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16088292A JPH065734A (en) 1992-06-19 1992-06-19 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPH065734A true JPH065734A (en) 1994-01-14

Family

ID=15724415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16088292A Withdrawn JPH065734A (en) 1992-06-19 1992-06-19 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPH065734A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003837A (en) * 2008-06-19 2010-01-07 Kyocera Corp Package and electronic apparatus using the same, as well as light emitting device employing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003837A (en) * 2008-06-19 2010-01-07 Kyocera Corp Package and electronic apparatus using the same, as well as light emitting device employing the same

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990831