JPS60113451A - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JPS60113451A
JPS60113451A JP22264383A JP22264383A JPS60113451A JP S60113451 A JPS60113451 A JP S60113451A JP 22264383 A JP22264383 A JP 22264383A JP 22264383 A JP22264383 A JP 22264383A JP S60113451 A JPS60113451 A JP S60113451A
Authority
JP
Japan
Prior art keywords
package
leads
ground
lead
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22264383A
Other languages
Japanese (ja)
Other versions
JPH0160949B2 (en
Inventor
Takashi Kondo
隆 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22264383A priority Critical patent/JPS60113451A/en
Publication of JPS60113451A publication Critical patent/JPS60113451A/en
Publication of JPH0160949B2 publication Critical patent/JPH0160949B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To prevent the malfunction of a contained semiconductor element by a method wherein inner leads are surrounded by ground leads, which are then connected to a ground terminal, a die area, or a seal area. CONSTITUTION:The inner leads 2 are surrounded by the ground leads 8, which are then connected to any of the ground terminal 7, the die are 4, and the seal area 3. The, noises due to the interference among the leads 2 for giving and taking signals provided in proximity to each other are eliminated, and the malfunction of the contained semiconductor element can be prevented.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半４捧素子を収納する気密型パッケージに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an airtight package for housing a semi-quad element.

〔従来技術〕[Prior art]

従来、この柚のパッケージとして第１図（ａ）。 Conventionally, this yuzu package was shown in Figure 1 (a).

（ｂ）に示すものがあった。これらの図において、１は
パッケージ基体で、通常、セラミックやプリント基板か
らなり、その主表面に内部リード２と、シールエリア３
と、ダイエリア４とからなり、それぞれ印刷や蒸着等の
プルセスにより導体が、絶縁体からなるパッケージ基体
１上に付与バターニングされる。また、パッケージ基体
１の他の面にはこのパンケージ基体１を貫通して、第１
図（ｂ）に示すように導体のスルーホール５と接続され
た外部リード６が設けられている。There was one shown in (b). In these figures, 1 is a package base, which is usually made of ceramic or a printed circuit board, and has internal leads 2 and a sealing area 3 on its main surface.
and a die area 4, and a conductor is applied and patterned onto the package base 1 made of an insulator by a process such as printing or vapor deposition. Further, on the other surface of the package base 1, a first
As shown in Figure (b), an external lead 6 connected to the conductor through hole 5 is provided.

なお、通常は内部リード２の内１つ以上がグランド端子
７として用いられ、ダイエリア４（あるいはシールエリ
ア３）と連結されている。Note that one or more of the internal leads 2 are normally used as the ground terminal 7 and are connected to the die area 4 (or seal area 3).

このような従来のパッケージでは、通常、相互に近接し
て設けられている信号授受用の内部リード２間の干渉に
よるノイズのため、収納された半導体素子が誤動作する
ことがあった。In such conventional packages, the semiconductor elements housed therein sometimes malfunction due to noise caused by interference between the internal leads 2 for signal exchange, which are usually provided close to each other.

〔発明の概要〕[Summary of the invention]

この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、内部リードヶ取り囲むようにグ
ランドリードな設けた半４捧パッケージを提供すること
を目的としている。The present invention was made to eliminate the above-mentioned drawbacks of the conventional package, and an object of the present invention is to provide a semi-quad-bar package having a ground lead surrounding an internal lead.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を第２図について説明する。 An embodiment of the present invention will be described below with reference to FIG.

第２図において、８はグランドリードで、それぞれ内部
リード２を取り囲み、少なくともその一部が、グランド
端子７．ダイエリア４．′ｅたはシールエリア３のいず
れかに連結されている（第２図は全部に連結されている
場合を示す）。In FIG. 2, reference numeral 8 denotes ground leads, each of which surrounds the internal lead 2, and at least a part of which is connected to the ground terminal 7. Die area 4. 'e or the seal area 3 (FIG. 2 shows the case where they are all connected).

なお、第２図の実施例では全ての内部リード２をグラン
ドリード８で囲っているが、これはもちろん必要な内部
リード２だげを囲うようにしてもよい。In the embodiment shown in FIG. 2, all the internal leads 2 are surrounded by the ground lead 8, but it is of course possible to surround only the necessary internal leads 2.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、所要個所の内部リー
ドをグランドリードで取り囲み、少な（ともその一部を
グランド端子またはタイエリアまたはシールエリアと接
続した構成としたので、従来と全く同じプロセスで半導
体パッケージが製造でき、したがって、特別な装置も不
要で、かつ、性能のよい半導体パッケージの提供が可能
である。As explained above, this invention has a configuration in which internal leads at required locations are surrounded by ground leads, and a small number (or at least a part of them) is connected to a ground terminal, tie area, or seal area, so the process is exactly the same as the conventional one. A semiconductor package can be manufactured, therefore, no special equipment is required, and a semiconductor package with good performance can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、（ｂ）は従来の半導体パッケージの平面
図および側面図、第２図はこの発明の一実施例を示す平
面図である。 図中、１はパッケージ基体、２は内部リード、３はシー
ルエリア、４はダイエリア、５はスルーホール、６は外
部リード、７はグランド端子、８はグランドリードであ
る。 なお、図中の同一符号は同一または相当部分を示す。 代理人　大岩　増雄　（外２名）FIGS. 1(a) and 1(b) are a plan view and a side view of a conventional semiconductor package, and FIG. 2 is a plan view showing an embodiment of the present invention. In the figure, 1 is a package base, 2 is an internal lead, 3 is a seal area, 4 is a die area, 5 is a through hole, 6 is an external lead, 7 is a ground terminal, and 8 is a ground lead. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others)

Claims (1)

【特許請求の範囲】[Claims] 半導体素子７収容固着するダイエリアと、前記半導体素
子とパッケージとを電気的に接続するための複数の内部
リードと、封止のためのシールエリアとを同一平面上に
形成した絶縁体からなるパッケージ基体と、このパッケ
ージ基体に形成されたスルーホールを貫通して外部リー
ドと前記内部リードとが接続されこの内部リードのうち
所要のもの７クランド端子とした構造の半導体パッケー
ジにおいて、前記複数の内部リードのＷｒ要のものケグ
ラントリードで取り囲み、かつ、このグランドリードを
少なくとも前記グランド端子、またはダイエリア、また
はシールエリアと接続したこと’Ｙ％徴とする半導体パ
ッケージ。A package made of an insulator in which a die area for accommodating and fixing a semiconductor element 7, a plurality of internal leads for electrically connecting the semiconductor element and the package, and a seal area for sealing are formed on the same plane. In a semiconductor package having a structure in which an external lead and the internal lead are connected to each other through a through hole formed in a base body and a through hole formed in the package base body, and seven required ones of the internal leads are ground terminals, the plurality of internal leads are connected to each other. A semiconductor package characterized in that a key component of Wr is surrounded by a kegrant lead, and the ground lead is connected to at least the ground terminal, the die area, or the seal area.
JP22264383A 1983-11-24 1983-11-24 Semiconductor device package Granted JPS60113451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22264383A JPS60113451A (en) 1983-11-24 1983-11-24 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22264383A JPS60113451A (en) 1983-11-24 1983-11-24 Semiconductor device package

Publications (2)

Publication Number Publication Date
JPS60113451A true JPS60113451A (en) 1985-06-19
JPH0160949B2 JPH0160949B2 (en) 1989-12-26

Family

ID=16785663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22264383A Granted JPS60113451A (en) 1983-11-24 1983-11-24 Semiconductor device package

Country Status (1)

Country Link
JP (1) JPS60113451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020113656A (en) * 2019-01-11 2020-07-27 株式会社デンソー Electronic device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020113656A (en) * 2019-01-11 2020-07-27 株式会社デンソー Electronic device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0160949B2 (en) 1989-12-26

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