JPS58131638U - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS58131638U JPS58131638U JP2693382U JP2693382U JPS58131638U JP S58131638 U JPS58131638 U JP S58131638U JP 2693382 U JP2693382 U JP 2693382U JP 2693382 U JP2693382 U JP 2693382U JP S58131638 U JPS58131638 U JP S58131638U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- circuit device
- outer periphery
- electrical components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の混成集積回路装置の断面図、第２図は本
考案の混成集積回路装置の断面図、第３図は絶縁性の枠
の拡大斜視図である。
ｌａ、ｌｂ、１０ａ、１０ｂ−・・混成集積回路基板、
２．１２・・・外部接続用リード端子、３ａ、 ３ｂ
。
３ｃ、 ３ｂ・・・半導体素子等、４．５． ６・・
・コーティング用樹脂、７・・・接続線、８・・・枠、
９・・・導体パターン、１１・・・接続部、１３・・・
接着剤。FIG. 1 is a sectional view of a conventional hybrid integrated circuit device, FIG. 2 is a sectional view of the hybrid integrated circuit device of the present invention, and FIG. 3 is an enlarged perspective view of an insulating frame. la, lb, 10a, 10b--hybrid integrated circuit board,
2.12... Lead terminal for external connection, 3a, 3b
. 3c, 3b... semiconductor element, etc., 4.5. 6...
・Coating resin, 7... Connection wire, 8... Frame,
9... Conductor pattern, 11... Connection part, 13...
glue.
Claims (1)
て適当な間隔で平行に配置した複数枚の混成集積回路基
板の間に、前記混成集積回路基板の回路量接続を行なう
導体パターンを外周に形成した絶縁性の枠を前記混成集
積回路基板の外周縁に位置するよう介設し、前記半導体
素子等の電気部品を封止したことを特徴とする混成集積
回路装置。Between a plurality of hybrid integrated circuit boards arranged in parallel at appropriate intervals with the surfaces on which electrical components such as semiconductor elements are mounted inside each other, a conductive pattern for connecting the circuits of the hybrid integrated circuit boards is placed around the outer periphery. A hybrid integrated circuit device, characterized in that an insulating frame formed on the hybrid integrated circuit board is interposed so as to be located at the outer periphery of the hybrid integrated circuit board, and electrical components such as the semiconductor element are sealed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2693382U JPS58131638U (en) | 1982-02-26 | 1982-02-26 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2693382U JPS58131638U (en) | 1982-02-26 | 1982-02-26 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58131638U true JPS58131638U (en) | 1983-09-05 |
Family
ID=30038858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2693382U Pending JPS58131638U (en) | 1982-02-26 | 1982-02-26 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58131638U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61190172U (en) * | 1985-05-20 | 1986-11-27 | ||
| JPH0286198U (en) * | 1988-12-22 | 1990-07-09 |
-
1982
- 1982-02-26 JP JP2693382U patent/JPS58131638U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61190172U (en) * | 1985-05-20 | 1986-11-27 | ||
| JPH0286198U (en) * | 1988-12-22 | 1990-07-09 |
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