JPS60263452A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPS60263452A
JPS60263452A JP12016784A JP12016784A JPS60263452A JP S60263452 A JPS60263452 A JP S60263452A JP 12016784 A JP12016784 A JP 12016784A JP 12016784 A JP12016784 A JP 12016784A JP S60263452 A JPS60263452 A JP S60263452A
Authority
JP
Japan
Prior art keywords
integrated circuit
terminals
ceramic substrate
terminal
grounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12016784A
Other languages
Japanese (ja)
Inventor
Hideki Nishimori
西森　英樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12016784A priority Critical patent/JPS60263452A/en
Publication of JPS60263452A publication Critical patent/JPS60263452A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To miniaturize an overall package by means of reducing the number of terminals as well as the space of insulating substrate by a method wherein a metallic cap covering an integrated circuit is provided with terminals. CONSTITUTION:The second terminals 41 as grounding terminals are planted in a metallic cap 40 by brazing process to be connected to another grounding terminal of an integrated circuit 20 through the intermediary of a metallic cap 40, a ring type electrode 12, a bonding pad 14 and a bonding wire 13. Next the ring type electrode part 12 is provided around an integrated circuit 20 of a ceramic substrate 10 to be connected to multiple grounding terminals of the integrated circuit 20. Then the circuit 20 is covered with the metallic cap 40 with grounding terminals 41 so that a rim 40a of cap 40 may abut against the electrode part 12. Through these procedures, the number of terminals 11 directly planted in the ceramic substrate 10 may be reduced by the number of grounding terminals 41. Resultantly, an averall package may be miniaturized by means of reducing the space of ceramic substrate 10.

Description

【発明の詳細な説明】 〔技術分野〕 本発゛明は、集積回路を橿う金属製キャップ上に端子を
設けた集積回路パッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an integrated circuit package having terminals on a metal cap that covers the integrated circuit.

〔従来技術〕[Prior art]

従来、集積回路パッケージは、放熱のためにセラミック
基板の片面に放熱板を固着し、その反対面に集積回路を
搭載してその端子に基板内配線を介してセラミック基板
上の入出力端子を設けた構成である。Conventionally, integrated circuit packages have a heat dissipation plate fixed to one side of a ceramic substrate for heat dissipation, an integrated circuit mounted on the other side, and input/output terminals on the ceramic substrate connected to the terminals via wiring inside the substrate. The configuration is as follows.

しかしながら、セラミック基板上の複数の入出力端子は
、コネクター等の接続のため一定間隔を以って離間配置
される必要があるため、これにより、セラミック基板は
一定の面積以上に限定されてしまい、集積回路パッケー
ジの小型化が困雛であった。However, the plurality of input/output terminals on the ceramic substrate need to be spaced apart from each other to connect connectors, etc., so the ceramic substrate is limited to a certain area or more. It has been difficult to miniaturize integrated circuit packages.

〔発明の目的〕[Purpose of the invention]

本発明は、上記の問題点を解決するもので、集積回路を
覆う金属製キャップに端子を設けることによシ、絶縁基
板上の端子数の減少を図り、絶縁基板の面積を小さくな
し、パッケージ全体を小型化しうる集積回路パッケージ
を提供することを目的とする。The present invention solves the above problems by providing terminals on the metal cap covering the integrated circuit, thereby reducing the number of terminals on the insulating substrate, reducing the area of the insulating substrate, and packaging the integrated circuit. The purpose of the present invention is to provide an integrated circuit package that can be miniaturized as a whole.

〔発明の構成〕[Structure of the invention]

本発明の目的を達成するだめの、本発明に係る集積回路
パッケージの構成は、絶縁性基板上に設けた集積回路と
、集積回路の端子に配線を介して接続する絶縁基板上の
第１の端子とを有する集積回路パッケージにおいて、集
積回路の端子に接続する電極部を絶縁性基板上に設ける
と共に、電極部に集積回路を覆う金属製キャップを固着
し、金属製キャップ上に第２の端子を設けてなるもので
める。The structure of the integrated circuit package according to the present invention, which achieves the object of the present invention, includes an integrated circuit provided on an insulating substrate, and a first integrated circuit provided on the insulating substrate connected to terminals of the integrated circuit via wiring. In an integrated circuit package having a terminal, an electrode part connected to the terminal of the integrated circuit is provided on an insulating substrate, a metal cap covering the integrated circuit is fixed to the electrode part, and a second terminal is attached on the metal cap. It is made by setting up.

〔実施例の説明〕[Explanation of Examples]

次に、本発明の一実施例を図面に基づいて説明する。 Next, one embodiment of the present invention will be described based on the drawings.

第１図は、本発明に係る集積回路パッケージの一実施例
を示す分解斜視図である。FIG. 1 is an exploded perspective view showing an embodiment of an integrated circuit package according to the present invention.

智 １　図中、１０は絶縁性基板としてのセラミック基板で
、その片面上中央には集積回路２０が搭載されている。1 In the figure, numeral 10 is a ceramic substrate serving as an insulating substrate, and an integrated circuit 20 is mounted on the center of one side of the ceramic substrate.

１１はセラミック基板１０の周縁部に一定間隔ごとに植
設された第１の端子としての入出力端子でアシ、これら
は集積回路２０の所定の端子とボンディングワイヤ２１
、ポンディングパッド２２、基板内配線（図示せず）を
介して接続されている。Reference numerals 11 denote input/output terminals as first terminals implanted at regular intervals on the periphery of the ceramic substrate 10, and these are connected to predetermined terminals of the integrated circuit 20 and bonding wires 21.
, the bonding pad 22, and are connected via wiring within the board (not shown).

１２は集積回路２０の周囲に設けられた環状の電極部で
あシ、集積回路２０の複数の接地端子とボンディングワ
イヤ１３、ポンディングパッド１４を介して接続されて
いる。４０は集積回路２０を覆いシールド効果を果す箱
型の金属製キャップで、そのリム４０ａは環状の電極部
１２に衝合するように形成されておシ、金属製キャップ
２０はろう付けにより固着される。４１は金属製キャッ
プ４１上にろう付けにより植設された第２の端子として
の接地端子で、これは金属製キャップ４０、環状の電極
部１２、ポンプイングツくラド１４、ボンディングワイ
ヤ１３を介して集積回路２０の接地端子と接続している
。Reference numeral 12 denotes an annular electrode portion provided around the integrated circuit 20 and connected to a plurality of ground terminals of the integrated circuit 20 via bonding wires 13 and bonding pads 14. Reference numeral 40 denotes a box-shaped metal cap that covers the integrated circuit 20 and provides a shielding effect, the rim 40a of which is formed to abut against the annular electrode portion 12, and the metal cap 20 is fixed by brazing. Ru. Reference numeral 41 denotes a ground terminal as a second terminal which is implanted on the metal cap 41 by brazing. It is connected to the ground terminal of the circuit 20.

なお、３０はセラミック基板１０の裏面に固着された放
熱板である。Note that 30 is a heat sink fixed to the back surface of the ceramic substrate 10.

このように、セラミック基板１０上の集積回路２０の周
囲に環状の電極部１２を設け、集積回路２０の複数の接
地端子をこの電極部１２に接続し、接地端子４１を有す
る金属キャップ４０をそのリム４０ａが環状の電極部１
２に衝合するよう集積回路２０を種う構造であるから、
接地端子４１の数の分だけセラミック基板１０上に直接
植設する端子１１の数を減らすことができる。これによ
シセラミック基板１０の面積を滅らすことができ、ノく
ツケージを小型化しうる。またセラミック基板１０の周
縁部までの基板内配線が減少するから、この分、セラミ
ック基板の面積を減らすことができ、更に一層パッケー
ジの小型化を図りうる。金属製キャップ４０上の端子４
１は接地端子としているから、集積回路２０に対するシ
ールド効果を高めることができる。In this way, the annular electrode part 12 is provided around the integrated circuit 20 on the ceramic substrate 10, the plurality of ground terminals of the integrated circuit 20 are connected to this electrode part 12, and the metal cap 40 having the ground terminal 41 is attached to the electrode part 12. Electrode part 1 whose rim 40a is annular
Since the structure is such that the integrated circuit 20 is arranged so as to match 2,
The number of terminals 11 directly implanted on ceramic substrate 10 can be reduced by the number of ground terminals 41. This allows the area of the ceramic substrate 10 to be reduced and the size of the socket cage to be reduced. Furthermore, since the wiring within the substrate up to the periphery of the ceramic substrate 10 is reduced, the area of the ceramic substrate can be reduced accordingly, and the package can be further downsized. Terminal 4 on metal cap 40
Since 1 is a ground terminal, the shielding effect for the integrated circuit 20 can be enhanced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明に係る集積回路パッケージ
によれば、集積回路の端子に接続する電極部を絶縁性基
板上に設けると共に、その電極部に集積回路を覆う金属
製キャップを固着し、この金属製キャップ上に端子を設
けた点に特徴を有するため、集積回路の上部スペースを
有効利用しておシ、絶縁性基板の端子の数を減らすこと
ができ、この分、絶縁性基板の面積を小さくできるから
、集積回路パッケージを小型化、高密度化しうるという
効果を奏する。また、集積回路を覆う金属製キャップに
よるシールド効果がある。As explained above, according to the integrated circuit package according to the present invention, an electrode portion connected to a terminal of the integrated circuit is provided on an insulating substrate, and a metal cap covering the integrated circuit is fixed to the electrode portion, Since the terminals are provided on the metal cap, the space above the integrated circuit can be used effectively, and the number of terminals on the insulating board can be reduced. Since the area can be reduced, the integrated circuit package can be made smaller and more dense. Additionally, a metal cap covering the integrated circuit has a shielding effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明に係る集積回路パッケージの一実施例
を示す分解斜視図である。 １０・・・セラミック基板 １１・・・第１の端子としての入出力端子１２・・・環
状の電極部 １３．２１・・・ボンディングワイヤ １４．２２・・・ポンディングパッド ２０・・・集積回路 ３０・・・放熱板 ４０・・・金属製キャップ ４０ａ・・・リム ４１・・・第２の端子としての接地端子出願人　日本電
気株式会社 艷 第１図FIG. 1 is an exploded perspective view showing an embodiment of an integrated circuit package according to the present invention. DESCRIPTION OF SYMBOLS 10... Ceramic substrate 11... Input/output terminal 12 as a first terminal... Annular electrode portion 13.21... Bonding wire 14.22... Bonding pad 20... Integrated circuit 30... Heat sink 40... Metal cap 40a... Rim 41... Grounding terminal as second terminal Applicant: NEC Corporation Figure 1

Claims (1)

【特許請求の範囲】[Claims] 絶縁性基板上に設けた集積回路と、前記集積回路の端子
に配線を介して接続する前記絶縁基板上の第１の端子と
を有する集積回路パッケージにおいて、前記集積回路の
端子に接続する電極部を前記絶縁性基板上に設けると共
に、前記電極部に前記集積回路を覆う金属製キャップを
固着し、前記金属製キャップ上に第２の端子を設けてな
ることを特徴とする集積回路パッケージ。An integrated circuit package having an integrated circuit provided on an insulating substrate and a first terminal on the insulating substrate connected to the terminal of the integrated circuit via wiring, an electrode portion connected to the terminal of the integrated circuit. is provided on the insulating substrate, a metal cap covering the integrated circuit is fixed to the electrode portion, and a second terminal is provided on the metal cap.
JP12016784A 1984-06-12 1984-06-12 Integrated circuit package Pending JPS60263452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12016784A JPS60263452A (en) 1984-06-12 1984-06-12 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12016784A JPS60263452A (en) 1984-06-12 1984-06-12 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPS60263452A true JPS60263452A (en) 1985-12-26

Family

ID=14779598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12016784A Pending JPS60263452A (en) 1984-06-12 1984-06-12 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS60263452A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712767A (en) * 1994-11-16 1998-01-27 Nec Corporation Circuit elements mounting
US5805427A (en) * 1996-02-14 1998-09-08 Olin Corporation Ball grid array electronic package standoff design

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712767A (en) * 1994-11-16 1998-01-27 Nec Corporation Circuit elements mounting
US5805427A (en) * 1996-02-14 1998-09-08 Olin Corporation Ball grid array electronic package standoff design

Similar Documents

Publication Publication Date Title
JP2008252152A (en) Perimeter matrix ball grid array circuit package with populated center
JPH04307943A (en) Semiconductor device
US5650660A (en) Circuit pattern for a ball grid array integrated circuit package
JP2809945B2 (en) Semiconductor device
JP3138539B2 (en) Semiconductor device and COB substrate
JPS60263452A (en) Integrated circuit package
JPS60263451A (en) Integrated circuit package
US5126828A (en) Wafer scale integration device
JP3910694B2 (en) Manufacturing method of semiconductor device with external terminal
JPH0499056A (en) Composite integrated circuit chip
JPS62123744A (en) Semiconductor device
JPS60263450A (en) Integrated circuit package
JPS617657A (en) Package for multi-chip
JPH02164057A (en) Pin grid array semiconductor package
JPH11307684A (en) Semiconductor package
JP2562773Y2 (en) Semiconductor integrated circuit device
JPH0730067A (en) Semiconductor device
JPS5823469A (en) Composite power transistor
JPS60254755A (en) Package for mounting semiconductor
JPH02205055A (en) Resin-sealed semiconductor device
JPH03257853A (en) Semiconductor device
JPH01205457A (en) Systematized semiconductor device
JPH05315529A (en) Resin-sealed semiconductor device
JPS60113451A (en) Semiconductor device package
JPH07193186A (en) Semiconductor device