JPH0730067A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0730067A JPH0730067A JP5154001A JP15400193A JPH0730067A JP H0730067 A JPH0730067 A JP H0730067A JP 5154001 A JP5154001 A JP 5154001A JP 15400193 A JP15400193 A JP 15400193A JP H0730067 A JPH0730067 A JP H0730067A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- tab
- semiconductor device
- metal layer
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はパッケージの小型化技
術、特に、高機能化及び高集積化を図るために用いて効
果のある技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing the size of a package, and more particularly to a technique effectively used for achieving high functionality and high integration.
【０００２】[0002]
【従来の技術】近年、半導体装置の高機能化及び高集積
化に伴って急速に多ピン化が進み、これに比例して電源
ピン（またはリード）も増加の傾向にある。通常、１つ
のＬＳＩ（大規模集積回路）は、数本の電源ピンとグラ
ンド（ＧＮＤ）ピンを備えている。2. Description of the Related Art In recent years, the number of pins has rapidly increased as the functionality and integration of semiconductor devices have increased, and in proportion to this, the number of power supply pins (or leads) has been increasing. Usually, one LSI (large scale integrated circuit) includes several power supply pins and ground (GND) pins.
【０００３】[0003]
【発明が解決しようとする課題】本発明者の検討によれ
ば、高機能化及び高集積化に伴ってパッケージサイズの
拡大、アナログ／デジタル回路の混在等により複雑化し
た半導体装置は、多ピン化が避けられず、基板上に実装
したときのパターン引き回し設計に多大の時間と労力を
要するという問題がある。また、配線の引き回しによ
り、電位差を大きくするという問題もある。According to the study by the present inventor, a semiconductor device having a complicated structure due to an increase in package size, a mixture of analog / digital circuits, and the like, which accompanies higher functionality and higher integration, has a large number of pins. Inevitably, there is a problem that a great deal of time and labor is required for designing the pattern layout when it is mounted on the substrate. There is also a problem in that the potential difference is increased by arranging the wiring.
【０００４】そこで、本発明の目的は、ピン数またはリ
ード数の低減を図りパッケージサイズの小型化を可能に
する技術を提供することにある。Therefore, an object of the present invention is to provide a technique capable of reducing the number of pins or leads and reducing the package size.
【０００５】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００６】[0006]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【０００７】すなわち、タブ上に実装された半導体チッ
プのパッドとリードまたはピンをボンディングワイヤで
接続する半導体装置であって、前記半導体チップの周囲
の前記タブ上に絶縁層を介してメタル層を設け、このメ
タル層に対し前記半導体チップ上の電圧が共通する電源
パッドの各々を接続すると共に、前記タブを共通のグラ
ンドパターンとし、このグランドパターンに前記半導体
チップ上のグランドパッドの各々を接続すると共に、前
記タブを共通のグランドパターンとし、このグランドパ
ターンに前記半導体チップ上のグランドパッドの各々を
接続するようにしている。That is, in a semiconductor device in which pads or leads or pins of a semiconductor chip mounted on a tab are connected by a bonding wire, a metal layer is provided on the tab around the semiconductor chip via an insulating layer. , Each of the power supply pads on the semiconductor chip having a common voltage is connected to the metal layer, the tab is used as a common ground pattern, and each of the ground pads on the semiconductor chip is connected to the ground pattern. The tab is used as a common ground pattern, and each of the ground pads on the semiconductor chip is connected to this ground pattern.
【０００８】[0008]
【作用】上記した手段によれば、半導体チップの周辺に
共通電源パターンとなるメタル層を設け、このメタル層
に半導体チップ上の電源パッド（電圧が共通するもの）
の各々が接続される。これにより、半導体チップ上の電
源パッドの各々に対応してリードを設ける必要がなくな
るので、ピン（またはリード）数の低減が可能になり、
基板実装時の基板上配線（パターン）の設計も容易にな
るため、パッケージの小型化が可能になる。According to the above means, the metal layer serving as the common power source pattern is provided around the semiconductor chip, and the power source pad on the semiconductor chip (having a common voltage) is provided in the metal layer.
Are connected to each other. This eliminates the need to provide a lead corresponding to each of the power supply pads on the semiconductor chip, so that the number of pins (or leads) can be reduced,
Since the design of the wiring (pattern) on the board at the time of mounting on the board becomes easy, the package can be downsized.
【０００９】[0009]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１０】（実施例１）図１は本発明による半導体装
置の一実施例を示す平面図である。また、図２は図１の
実施例の断面図である。(Embodiment 1) FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention. FIG. 2 is a sectional view of the embodiment shown in FIG.
【００１１】タブ１上の中央部には、上面の周囲にバン
プ２ａが設けられた半導体チップ２が実装（搭載）さ
れ、この半導体チップ２を取り囲むようにしてタブ１上
には枠形のメタル層３が絶縁層４を介して形成されてい
る。メタル層３に隣接させて、タブ１の周辺には放射状
に複数のリード５が水平に配設されている。このリード
５に対し、ボンディングワイヤ６によってメタル層３及
び半導体チップ２上のパッドとの接続が行われている。A semiconductor chip 2 having a bump 2a provided around the upper surface is mounted (mounted) on the central portion of the tab 1, and a frame-shaped metal is formed on the tab 1 so as to surround the semiconductor chip 2. The layer 3 is formed via the insulating layer 4. A plurality of leads 5 are radially arranged horizontally around the tab 1 so as to be adjacent to the metal layer 3. The leads 5 are connected to the metal layer 3 and pads on the semiconductor chip 2 by bonding wires 6.
【００１２】また、タブ１は金属製であるため、これを
共通のＧＮＤ端子として用いることができる。すなわ
ち、半導体チップ２上のグランド用パッド２ｃ及びリー
ド５をメタル層３の両側より露出するタブ１の表面にワ
イヤボンディングで接続することにより、グランド用の
リードは１本で済むことになる。Since the tab 1 is made of metal, it can be used as a common GND terminal. That is, by connecting the ground pad 2c and the lead 5 on the semiconductor chip 2 to the surface of the tab 1 exposed from both sides of the metal layer 3 by wire bonding, only one ground lead is required.
【００１３】このように、半導体チップ２の周囲のスペ
ースを生かし、このスペースにメタル層３を設けること
で共通電源パターンを作成することができ、この共通電
源パターンに半導体チップ２上の電源用パッド２ｂの各
々を接続すれば、電源用のリード５は１本で済むことに
なり、リード数を低減できることによってパッケージの
小型化を図ることができる。そして、メタル層３は幅広
に形成できる結果、電位差を最小限に抑えることができ
る。As described above, the space around the semiconductor chip 2 is utilized, and the metal layer 3 is provided in this space, whereby the common power supply pattern can be created. The power supply pad on the semiconductor chip 2 is formed in the common power supply pattern. By connecting each of 2b, only one power supply lead 5 is required, and the number of leads can be reduced, so that the package can be downsized. As a result of the metal layer 3 being formed wide, the potential difference can be minimized.
【００１４】同様に、タブ１をグランド用パターンとし
て用いることでグランド用リードを１本で済ませられ、
これによってリード数を低減できる結果、パッケージの
小型化を図ることができる。Similarly, by using the tab 1 as a ground pattern, only one ground lead is required,
As a result, the number of leads can be reduced, so that the package can be downsized.
【００１５】（実施例２）図３は本発明の第２実施例を
示す断面図である。なお、図３においては、図２と同一
であるものには同一引用数字を用いたので、以下におい
ては重複する説明を省略する。(Embodiment 2) FIG. 3 is a sectional view showing a second embodiment of the present invention. Note that, in FIG. 3, the same reference numerals are used for the same elements as those in FIG. 2, and thus duplicated description will be omitted below.
【００１６】本実施例は、前記実施例におけるタブ１と
ほぼ同サイズの絶縁板７上に、半導体チップ２よりやや
大きめのサイズのタブ８を接着等により搭載し、タブ８
の周囲の絶縁板７上に共通電源用のメタル層３を直接に
設けるようにしたところに特徴がある。なお、ボンディ
ングワイヤ６の配線などについては、前記実施例と同一
である。In this embodiment, a tab 8 slightly larger than the semiconductor chip 2 is mounted by adhesion or the like on an insulating plate 7 having substantially the same size as the tab 1 in the above embodiment.
A characteristic is that the metal layer 3 for the common power source is directly provided on the insulating plate 7 around the. The wiring of the bonding wire 6 and the like are the same as in the above embodiment.
【００１７】本実施例は、タブが比較的小さく、半導体
チップ２の周囲に有効なスペースが得られない場合に有
効であり、タブサイズに制限されることなくパッケージ
サイズの小型化を図ることができる。This embodiment is effective when the tab is relatively small and an effective space cannot be obtained around the semiconductor chip 2, and the package size can be reduced without being restricted by the tab size. it can.
【００１８】（実施例３）図４は本発明の第３実施例を
示す平面図である。なお、図４においては、リード、ボ
ンディングワイヤなどについては図示を省略している。(Embodiment 3) FIG. 4 is a plan view showing a third embodiment of the present invention. Note that, in FIG. 4, illustration of the leads, bonding wires, and the like is omitted.
【００１９】前記各実施例がメタル層３を共通電源用に
用いていたため、メタル層３を枠形に形成し、電気的に
は４辺が接続された状態であったのに対し、本実施例は
複数（ここでは４つ）に分割し、各々を異なる目的に使
用するようにしたものである。例えば、異なる電圧や極
性の複数種の電源に用いる事などが可能になる。Since the metal layers 3 are used for the common power source in each of the above-described embodiments, the metal layers 3 are formed in a frame shape and are electrically connected to the four sides. The example is divided into a plurality (here, four) and used for different purposes. For example, it can be used for a plurality of types of power supplies having different voltages and polarities.
【００２０】なお、ここでは４辺にメタル層３を形成す
るものとしたが、少なくとも１辺に設ければよい。ま
た、図５に示すように各辺を更に分割し、用途を増やす
ことも可能である。Although the metal layer 3 is formed on four sides here, it may be provided on at least one side. Further, as shown in FIG. 5, each side can be further divided to increase the applications.
【００２１】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the embodiments and can be variously modified without departing from the scope of the invention. Needless to say.
【００２２】[0022]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.
【００２３】すなわち、タブ上に実装された半導体チッ
プのパッドとリードまたはピンをボンディングワイヤで
接続する半導体装置であって、前記半導体チップの周囲
の前記タブ上に絶縁層を介してメタル層を設け、このメ
タル層に対し前記半導体チップ上の電圧が共通する電源
パッドの各々を接続すると共に、前記タブを共通のグラ
ンドパターンとし、このグランドパターンに前記半導体
チップ上のグランドパッドの各々を接続するようにした
ので、ピン（またはリード）数の低減が可能になり、基
板実装時の基板上配線（パターン）の設計も容易になる
ため、パッケージの小型化が可能になる。That is, in a semiconductor device in which pads or leads or pins of a semiconductor chip mounted on a tab are connected by a bonding wire, a metal layer is provided on the tab around the semiconductor chip via an insulating layer. , Each of the power supply pads having a common voltage on the semiconductor chip is connected to the metal layer, the tab is used as a common ground pattern, and each of the ground pads on the semiconductor chip is connected to the ground pattern. Therefore, the number of pins (or leads) can be reduced, and the design of the wiring (pattern) on the board at the time of mounting on the board is facilitated, so that the package can be downsized.
【図１】本発明による半導体装置の一実施例を示す平面
図である。FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention.
【図２】図１の実施例の断面図である。2 is a cross-sectional view of the embodiment of FIG.
【図３】本発明の第２実施例を示す断面図である。FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】本発明の第３実施例を示す平面図である。FIG. 4 is a plan view showing a third embodiment of the present invention.
【図５】図４の実施例の変形例を示す平面図である。5 is a plan view showing a modification of the embodiment of FIG.
１ タブ ２ 半導体チップ ２ａ パッド ２ｂ 電源用パッド ２ｃ グランド用パッド ３ メタル層 ４ 絶縁層 ５ リード ６ ボンディングワイヤ ７ 絶縁板 ８ タブ 1 tab 2 semiconductor chip 2a pad 2b power supply pad 2c ground pad 3 metal layer 4 insulating layer 5 lead 6 bonding wire 7 insulating plate 8 tab
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高崎 一 秋田県南秋田郡天王町天王字長沼64 アキ タ電子株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hajime Takasaki 64 Naganuma Tenno, Tenno-cho, Minami-Akita-gun, Akita Akita Electronics Co., Ltd.
Claims (5)
ドとリードまたはピンをボンディングワイヤで接続する
半導体装置であって、前記半導体チップの周囲の前記タ
ブ上に絶縁層を介してメタル層を設け、このメタル層に
対し前記半導体チップ上の電圧が共通する電源パッドの
各々を接続すると共に、前記タブを共通のグランドパタ
ーンとし、このグランドパターンに前記半導体チップ上
のグランドパッドの各々を接続することを特徴とする半
導体装置。1. A semiconductor device in which pads or leads or pins of a semiconductor chip mounted on a tab are connected by bonding wires, and a metal layer is provided on the tab around the semiconductor chip via an insulating layer. Connecting each of the power supply pads having a common voltage on the semiconductor chip to the metal layer, using the tab as a common ground pattern, and connecting each of the ground pads on the semiconductor chip to the ground pattern. A semiconductor device characterized by:
ドとリードまたはピンをボンディングワイヤで接続する
半導体装置であって、前記タブの裏面に該タブよりサイ
ズの大きい絶縁板を取り付け、前記メタル層を前記タブ
に代えて前記半導体チップの周囲の前記絶縁板上に形成
することを特徴とする請求項１記載の半導体装置。2. A semiconductor device in which pads or leads or pins of a semiconductor chip mounted on a tab are connected by a bonding wire, and an insulating plate having a size larger than the tab is attached to the back surface of the tab, and the metal layer is formed. 2. The semiconductor device according to claim 1, wherein is formed on the insulating plate around the semiconductor chip instead of the tab.
周するように配設することを特徴とする請求項１または
２記載の半導体装置。3. The metal layer forms the semiconductor chip 1
The semiconductor device according to claim 1, wherein the semiconductor device is arranged so as to surround the semiconductor device.
囲に分割して配設するとともに、その用途が異ることを
特徴とする請求項１または２記載の半導体装置。4. The semiconductor device according to claim 1, wherein the metal layer is divided and arranged around the semiconductor chip and has different uses.
囲の少なくとも１辺に設けることを特徴とする請求項１
または２記載の半導体装置。5. The metal layer is provided on at least one side around the semiconductor chip.
Alternatively, the semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15400193A JP3308047B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15400193A JP3308047B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0730067A true JPH0730067A (en) | 1995-01-31 |
| JP3308047B2 JP3308047B2 (en) | 2002-07-29 |
Family
ID=15574750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15400193A Expired - Lifetime JP3308047B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3308047B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0758798A3 (en) * | 1995-08-14 | 1998-11-11 | Samsung Electronics Co., Ltd. | Semiconductor device with enhanced electrical characteristic |
| US7187065B2 (en) | 2004-09-17 | 2007-03-06 | Fujitsu Limited | Semiconductor device and semiconductor device unit |
| CN110364477A (en) * | 2018-03-26 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Chip structure and forming method thereof |
-
1993
- 1993-06-25 JP JP15400193A patent/JP3308047B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0758798A3 (en) * | 1995-08-14 | 1998-11-11 | Samsung Electronics Co., Ltd. | Semiconductor device with enhanced electrical characteristic |
| US5898225A (en) * | 1995-08-14 | 1999-04-27 | Samsung Electronics Co., Ltd. | Lead frame bonding power distribution systems |
| US6015723A (en) * | 1995-08-14 | 2000-01-18 | Samsung Electronics Co., Ltd. | Lead frame bonding distribution methods |
| US7187065B2 (en) | 2004-09-17 | 2007-03-06 | Fujitsu Limited | Semiconductor device and semiconductor device unit |
| CN110364477A (en) * | 2018-03-26 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Chip structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3308047B2 (en) | 2002-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6501157B1 (en) | Substrate for accepting wire bonded or flip-chip components | |
| US7550842B2 (en) | Integrated circuit assembly | |
| US5841191A (en) | Ball grid array package employing raised metal contact rings | |
| JP2000223653A (en) | Semiconductor device having chip-on-chip structure and semiconductor chip using the same | |
| US5164817A (en) | Distributed clock tree scheme in semiconductor packages | |
| JPH04307943A (en) | Semiconductor device | |
| US5399904A (en) | Array type semiconductor device having insulating circuit board | |
| US6897555B1 (en) | Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die | |
| US5650660A (en) | Circuit pattern for a ball grid array integrated circuit package | |
| JPH1056093A (en) | Semiconductor device and electronic device where the semiconductor device is incorporated | |
| US20070130554A1 (en) | Integrated Circuit With Dual Electrical Attachment Pad Configuration | |
| US6646342B2 (en) | Semiconductor chip and multi-chip module | |
| US20020153619A1 (en) | Semiconductor chip having pads with plural junctions for different assembly methods | |
| JPH0730067A (en) | Semiconductor device | |
| US7279783B1 (en) | Partitioned integrated circuit package with central clock driver | |
| WO1999013509A1 (en) | Semiconductor device | |
| JP2004140169A (en) | Packaged semiconductor device | |
| JPH04349640A (en) | Analog-digital hybrid integrated circuit device package | |
| JP3951788B2 (en) | Surface mount electronic components | |
| JPS62216240A (en) | Package for integrated circuit | |
| JP2003124331A (en) | Semiconductor integrated circuit device | |
| JPH0697666A (en) | Electronic device | |
| JP4229086B2 (en) | Semiconductor device | |
| JPH08204114A (en) | Integrated circuit device | |
| JPH0430541A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080517 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080517 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090517 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100517 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110517 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110517 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120517 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130517 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140517 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term |