JPH08204114A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH08204114A
JPH08204114A JP7030031A JP3003195A JPH08204114A JP H08204114 A JPH08204114 A JP H08204114A JP 7030031 A JP7030031 A JP 7030031A JP 3003195 A JP3003195 A JP 3003195A JP H08204114 A JPH08204114 A JP H08204114A
Authority
JP
Japan
Prior art keywords
wiring board
density
integrated circuits
integrated circuit
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7030031A
Other languages
Japanese (ja)
Inventor
Yoshimi Hirata
芳美 平田
Masayoshi Kanazawa
雅義 金沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7030031A priority Critical patent/JPH08204114A/en
Publication of JPH08204114A publication Critical patent/JPH08204114A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

PURPOSE: To make miniaturization of a high-density multilayer wiring board possible as well as to design optimally characteristics to necessary parts and the sizes of the parts by a method wherein the high-density multilayer wiring board with a minimum necessary area for connecting integrated circuits together, which are required for high-density connection on a board for supporting the whole of an integrated circuit device, is provided on the board. CONSTITUTION: An integrated circuit IC6 provided with several tens of pieces or thereabouts of connection electrodes 17 is provided on the upper half surface of a low- density multilayer printed-wiring board 12 and the electrodes 17 are connected with connection electrodes 15 via bonding wires 6. On the other hand, integrated circuits IC8 , which are respectively provided with about 200 connection electrodes 18, are provided on the upper surface of a high-density wiring board 14 and the electrodes 18 are connected with connection electrodes 16 via bonding wires 6. Moreover, the board 12 is sealed in a molded body 10 excluding the peripheral parts of connection electrodes 13. The board 14 with a minimum necessary area for connecting the integrated circuits IC8 together, which are connected with each other in a high density on the board 12 for supporting the whole of an integrated circuit device, is provided on the board 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は集積回路装置に関し、特
に複数の集積回路のベアチツプを同一基板上に配設して
封止材で封止したマルチチツプモジユールに適用し得
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly, it can be applied to a multi-chip module in which bare chips of a plurality of integrated circuits are arranged on the same substrate and sealed with a sealing material.

【０００２】[0002]

【従来の技術】従来、マルチチツプモジユールにおいて
は、複数のベアチツプを互いに接続する同一の大型の高
密度配線基板を全てのベアチツプの共通支持基板として
も使用していた。図７及び図８に示すように、マルチチ
ツプモジユール１は、複数の外部リード２で囲まれたリ
ードフレームベース３上に高密度多層配線基板４が配設
されている。2. Description of the Related Art Conventionally, in a multi-chip module, the same large high-density wiring board for connecting a plurality of bear chips to each other has been used as a common supporting board for all the bear chips. As shown in FIGS. 7 and 8, in the multi-chip module 1, a high-density multilayer wiring board 4 is arranged on a lead frame base 3 surrounded by a plurality of external leads 2.

【０００３】この高密度多層配線基板４上に、例えば、
４つの集積回路ＩＣ1 〜ＩＣ4 のベアチツプが配設され
ている。それぞれの集積回路ＩＣ1 〜ＩＣ4 の接続用電
極５はボンデイングワイヤ６を介して高密度多層配線基
板４上の接続用電極７に接続されている。因みに、高密
度多層配線基板４は、シリコン等の半導体基板にアルミ
ニウム等の配線８用金属及び絶縁物の膜を積層して形成
される。また高密度多層配線基板４は、接続用電極９が
ボンデイングワイヤ６を介して外部リード２に接続さ
れ、外部リード２と共に、全体がモールド樹脂でなるモ
ールドボデイ１０で封止される。On the high-density multilayer wiring board 4, for example,
Four Beachitsupu integrated circuit IC 1 ~IC 4 is arranged. The connecting electrodes 5 of the integrated circuits IC 1 to IC 4 are connected to the connecting electrodes 7 on the high-density multilayer wiring board 4 via bonding wires 6. Incidentally, the high-density multilayer wiring board 4 is formed by laminating a film of a metal and an insulating material for the wiring 8 such as aluminum on a semiconductor substrate such as silicon. In the high-density multilayer wiring board 4, the connection electrodes 9 are connected to the external leads 2 via the bonding wires 6, and the high-density multilayer wiring board 4 is sealed together with the external leads 2 by a mold body 10 made of a molding resin.

【０００４】[0004]

【発明が解決しようとする課題】ところが、マルチチツ
プモジユールでは、一般にそれぞれの集積回路ＩＣ1 〜
ＩＣ4 の端子数、端子の密度、この端子に接続される配
線の幅等が集積回路ＩＣ1 〜ＩＣ4 の機能に応じて異な
る。このため、高密度多層配線基板４内の配線数、配線
密度、配線幅等は、どの集積回路ＩＣ1 〜ＩＣ4 をどの
ように互いに接続するかに応じて異なることになる。従
つて、それぞれ集積回路ＩＣ1 〜ＩＣ4 の組合せに応じ
た大型で多種類の高密度多層配線基板４を製造する必要
があり煩雑となるという問題点があつた。However, in the multichip module, in general, each integrated circuit IC 1- .
The number of terminals of the IC 4 , the density of the terminals, the width of the wiring connected to the terminals, and the like differ depending on the functions of the integrated circuits IC 1 to IC 4 . Therefore, the number of wirings, the wiring density, the wiring width, etc. in the high-density multilayer wiring board 4 differ depending on which integrated circuits IC 1 to IC 4 are connected to each other and how. Accordance connexion, there has been a problem that each becomes an integrated circuit IC 1 ~IC must manufacture many kinds of high-density multilayer wiring board 4 large in accordance with the combination of 4 complicated.

【０００５】また高密度多層配線基板４の配線特性は、
基本定数が単一である。このため集積回路ＩＣ1 〜ＩＣ
4 をどのように互いに接続するかに応じて異なる広範囲
な特性をカバーするには、製造プロセスを複雑にして対
応する必要があるという欠点もあつた。さらに高密度多
層配線基板４が大型化するに従つて、１枚のウエハから
製造できる高密度多層配線基板４が少なくなると共に、
良品率が低下するという欠点もあつた。The wiring characteristics of the high-density multilayer wiring board 4 are as follows.
There is a single basic constant. Therefore, the integrated circuits IC 1 to IC
It also had the drawback of requiring a complex manufacturing process to cover a wide range of different properties depending on how the four were connected to each other. Further, as the high-density multilayer wiring board 4 becomes larger, the number of high-density multilayer wiring boards 4 that can be manufactured from one wafer decreases,
There was also a drawback that the yield rate was reduced.

【０００６】本発明は以上の点を考慮してなされたもの
で、高密度多層配線基板を小型化し得ると共に、必要な
部分への特性及び大きさを最適に設計し得る集積回路装
置を提案しようとするものである。The present invention has been made in consideration of the above points, and proposes an integrated circuit device capable of miniaturizing a high-density multilayer wiring board and optimally designing characteristics and size of a necessary portion. It is what

【０００７】[0007]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、半導体ベアチツプでなる複数の集
積回路（ＩＣ5 〜ＩＣ8 ）が同一基板（１２）上に配設
され、任意の複数の集積回路（ＩＣ7 及びＩＣ8 ）を電
気的に互いに接続した集積回路装置（１１）において、
接続の際に高密度配線が必要な複数の集積回路（ＩＣ7
及びＩＣ8 ）下に、複数の集積回路（ＩＣ7 及びＩ
Ｃ8 ）同士を接続させるに必要な最小限の面積を基板
（１２）上で占有する高密度多層配線基板（１４）を設
ける。In order to solve such a problem, according to the present invention, a plurality of integrated circuits (IC 5 to IC 8 ) made of semiconductor bare chips are arranged on the same substrate (12), and any desired plurality of integrated circuits are arranged. An integrated circuit device (11) in which the integrated circuits (IC 7 and IC 8 ) are electrically connected to each other,
Multiple integrated circuits (IC 7
And IC 8 ) and a plurality of integrated circuits (IC 7 and I
A high-density multilayer wiring board (14) is provided which occupies the minimum area necessary for connecting C 8 ) on the board (12).

【０００８】また本発明においては，半導体ベアチツプ
でなる複数の集積回路（ＩＣ9 及びＩＣ10）が同一基板
（３）上に配設され、任意の複数の集積回路（ＩＣ9 及
びＩＣ10）を電気的に互いに接続した集積回路装置（２
０）において、基板（３）上に配設され、接続の際に複
数の接続用電極（２２及び２３）で対向する複数の集積
回路（ＩＣ9 及びＩＣ10）を互いに隔てると共に、複数
の集積回路（ＩＣ9 及びＩＣ10）の複数の接続用電極
（２２及び２３）を互いに電気的に接続させる配線基板
（２１）を設ける。Further, according to the present invention, a plurality of integrated circuits (IC 9 and IC 10 ) made of semiconductor bare chips are arranged on the same substrate (3), and an arbitrary plurality of integrated circuits (IC 9 and IC 10 ) can be formed. Integrated circuit devices (2
In (0), a plurality of integrated circuits (IC 9 and IC 10 ) arranged on the substrate (3) and facing each other by a plurality of connection electrodes (22 and 23) at the time of connection are separated from each other, and a plurality of integrated circuits are integrated. A wiring board (21) for electrically connecting a plurality of connection electrodes (22 and 23) of the circuits (IC 9 and IC 10 ) to each other is provided.

【０００９】[0009]

【作用】全体を支持する基板（１２）上で高密度接続を
必要とする集積回路（ＩＣ7 及びＩＣ8 ）同士を接続す
るに必要な最小限の面積だけ高密度多層配線基板（１
４）を配設したことにより、高密度多層配線基板（１
４）を小型化できると共に、必要な部分への特性及び大
きさを最適に設計できる。Function: A high-density multilayer wiring board (1) having a minimum area required for connecting integrated circuits (IC 7 and IC 8 ) which require high-density connection on the board (12) supporting the whole.
By disposing 4), the high-density multilayer wiring board (1
4) can be downsized, and the characteristics and size of the necessary parts can be optimally designed.

【００１０】[0010]

【実施例】以下図面について、本発明の一実施例を詳述
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

【００１１】図７との対応部分に同一符号を付して示す
図１及び図２において、１１は全体としてマルチチツプ
モジユールを示し、外部リード２の下面と低密度多層プ
リント配線基板１２の接続用電極１３の上面とが接続さ
れて、低密度多層プリント配線基板１２を支持してい
る。低密度多層プリント配線基板１２の一方の上半面
は、高密度配線基板１４が配設され、接続用電極１５が
高密度配線基板１４の上面の接続用電極１６とボンデイ
ングワイヤ６で接続されている。In FIGS. 1 and 2 in which parts corresponding to those in FIG. 7 are designated by the same reference numerals, 11 indicates a multi-chip module as a whole, and the lower surface of the external lead 2 and the low-density multilayer printed wiring board 12 are connected. It is connected to the upper surface of the working electrode 13 to support the low-density multilayer printed wiring board 12. The high-density wiring board 14 is disposed on one upper half surface of the low-density multilayer printed wiring board 12, and the connection electrodes 15 are connected to the connection electrodes 16 on the upper surface of the high-density wiring board 14 by the bonding wires 6. .

【００１２】以上の構成において、低密度多層プリント
配線基板１２の他方の上半面は、接続用電極１７が数１
０個程度配設された集積回路ＩＣ5 及びＩＣ6 が配設さ
れ、接続用電極１５及び１７がボンデイングワイヤ６で
接続される。これにより、集積回路ＩＣ5 及びＩＣ6 の
接続には、製造が容易な低密度多層プリント配線基板１
３で十分対応できることになる。In the above structure, the connecting electrode 17 is formed on the other upper half surface of the low-density multilayer printed wiring board 12 by the number 1
About 0 integrated circuits IC 5 and IC 6 are arranged, and the connecting electrodes 15 and 17 are connected by the bonding wire 6. As a result, the low density multilayer printed wiring board 1 which is easy to manufacture is used for connecting the integrated circuits IC 5 and IC 6.
3 will be sufficient.

【００１３】一方、高密度配線基板１４の上面は、接続
用電極１８が２００個程度又はこれ以上配設された集積
回路ＩＣ7 及びＩＣ8 が配設され、接続用電極１６及び
１８がボンデイングワイヤ６で接続される。これによ
り、高密度の配線が必要な集積回路ＩＣ7 及びＩＣ8 同
士の接続に必要な高密度配線基板１４の面積は、従来に
比して半分で済むことになる。因みに、低密度多層プリ
ント配線基板１２は、接続用電極１３が配設された周辺
部を除いて、モールドボデイ１０で封止される。On the other hand, on the upper surface of the high-density wiring board 14, integrated circuits IC 7 and IC 8 having about 200 or more connecting electrodes 18 are arranged, and the connecting electrodes 16 and 18 are bonded wires. Connected at 6. As a result, the area of the high-density wiring board 14 required for connecting the integrated circuits IC 7 and IC 8 that require high-density wiring to each other is half that of the conventional case. Incidentally, the low-density multilayer printed wiring board 12 is sealed with the mold body 10 except for the peripheral portion where the connection electrodes 13 are arranged.

【００１４】以上の構成によれば、全体を支持する低密
度多層プリント配線基板１２上で高密度接続を必要とす
る集積回路ＩＣ7 及びＩＣ8 同士を接続するに必要な最
小限の面積だけ高密度多層配線基板１４を配設したこと
により、高密度多層配線基板１４を小型化できると共
に、必要な部分への特性及び大きさを最適に設計でき
る。According to the above construction, the minimum area required for connecting the integrated circuits IC 7 and IC 8 which require high-density connection on the low-density multilayer printed wiring board 12 supporting the whole is increased. By arranging the density multilayer wiring board 14, the high density multilayer wiring board 14 can be downsized, and the characteristics and size of a necessary portion can be optimally designed.

【００１５】また高密度多層配線基板１４を小型化でき
ることにより、１枚のウエハから製造できる個数を増加
させることができると共に、良品率を向上させることが
できる。Further, since the high-density multilayer wiring board 14 can be miniaturized, the number of wafers that can be manufactured from one wafer can be increased and the yield rate can be improved.

【００１６】なお上述の実施例においては、集積回路Ｉ
Ｃ7 及びＩＣ8 の互いに対向しない接続用電極をも高密
度多層配線基板１４によつて同時に接続する場合につい
て述べたが、本発明はこれに限らず、図３及び図４に示
すように、マルチチツプモジユール２０のリードフレー
ム３上に配設された例えば２つの集積回路ＩＣ9 及びＩ
Ｃ10を互いに対向する接続用電極同士のみで接続する場
合には、ボンデイングワイヤ６での接続を中継する低密
度多層配線リレージヨイントチツプ２１を配設しても良
い。これにより、高密度多層配線基板を使用しないで済
むことになる。In the above embodiment, the integrated circuit I
The case where the connection electrodes of C 7 and IC 8 that do not face each other are simultaneously connected by the high-density multilayer wiring board 14 has been described, but the present invention is not limited to this, and as shown in FIGS. For example, two integrated circuits IC 9 and I arranged on the lead frame 3 of the multichip module 20.
When C 10 is connected only by the connecting electrodes facing each other, a low-density multilayer wiring relay joint chip 21 for relaying the connection by the bonding wire 6 may be provided. As a result, it is not necessary to use a high-density multilayer wiring board.

【００１７】また集積回路ＩＣ9 及びＩＣ10の対向する
接続用電極２２及び２３同士のみで接続することによ
り、集積回路ＩＣ9 及びＩＣ10の周囲の接続用電極を一
旦高密度多層配線基板を介して外部リードに接続する場
合に比して、全体を小型に形成することができる。さら
に低密度多層配線リレージヨイントチツプ２１上の接続
用電極にボンデイングワイヤ６の第２ボンドを打たせる
ことにより、集積回路ＩＣ9 又はＩＣ10上の接続電極に
第２ボンドを打つてボンデイングワイヤ６で直接接続す
る場合に比して、集積回路ＩＣ9 又はＩＣ10に物理的な
損傷を与えることを容易に避けることができる。[0017] By connecting only between the integrated circuit IC 9 and the connection electrodes 22 and 23 opposed to the IC 10, once through a high-density multilayer wiring board around the connecting electrodes of the integrated circuit IC 9, and IC 10 The entire size can be made smaller than that in the case where the external leads are connected. Further, by making a second bond of the bonding wire 6 on the connecting electrode on the low-density multilayer wiring relay joint chip 21, the second bond is made on the connecting electrode on the integrated circuit IC 9 or IC 10. It is possible to easily avoid physical damage to the integrated circuit IC 9 or IC 10 as compared with the case of directly connecting with.

【００１８】また上述の実施例においては、高密度多層
配線基板１４又は低密度多層配線リレージヨイントチツ
プ２１のみを配設する場合について述べたが、本発明は
これに限らず、図５及び図６のマルチチツプモジユール
２５に示すように、高密度多層配線基板２６及び低密度
多層配線リレージヨイントチツプ２７を同時に使用する
場合にも適用できる。これにより高密度多層配線基板、
低密度多層プリント配線基板及び低密度多層配線リレー
ジヨイントチツプを使い分けて設計の自由度を向上させ
ることができる。Further, in the above-described embodiment, the case where only the high-density multilayer wiring board 14 or the low-density multilayer wiring relay joint chip 21 is provided has been described, but the present invention is not limited to this, and FIGS. As shown in the multi-chip module 25 of No. 6, it can be applied to the case where the high-density multilayer wiring board 26 and the low-density multilayer wiring relay chip 27 are used at the same time. This enables high-density multilayer wiring boards,
The low-density multi-layer printed wiring board and the low-density multi-layer wiring relay joint chip can be selectively used to improve the degree of freedom in design.

【００１９】さらに上述の実施例においては、低密度多
層プリント配線基板を使用する場合について述べたが、
本発明はこれに限らず、低密度多層プリント配線基板に
代えて、セラミツク多層配線基板を使用しても良い。Further, in the above-mentioned embodiment, the case of using the low density multilayer printed wiring board has been described.
The present invention is not limited to this, and a ceramic multilayer wiring board may be used instead of the low density multilayer printed wiring board.

【００２０】[0020]

【発明の効果】上述のように本発明によれば、全体を支
持する基板上で高密度接続を必要とする集積回路同士を
接続するに必要な最小限の面積だけ高密度多層配線基板
を配設したことにより、高密度多層配線基板を小型化し
得ると共に、必要な部分への特性及び大きさを最適に設
計し得る集積回路装置を実現できる。As described above, according to the present invention, a high-density multi-layer wiring board is arranged in the minimum area necessary for connecting integrated circuits which require high-density connection on a substrate supporting the whole. By providing the integrated circuit device, it is possible to reduce the size of the high-density multilayer wiring board and to optimally design the characteristics and size of the necessary parts.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による集積回路装置の一実施例を示す平
面図である。FIG. 1 is a plan view showing an embodiment of an integrated circuit device according to the present invention.

【図２】図１の断面図である。FIG. 2 is a cross-sectional view of FIG.

【図３】他の実施例による集積回路装置を示す平面図で
ある。FIG. 3 is a plan view showing an integrated circuit device according to another embodiment.

【図４】図３の断面図である。4 is a cross-sectional view of FIG.

【図５】他の実施例による集積回路装置を示す平面図で
ある。FIG. 5 is a plan view showing an integrated circuit device according to another embodiment.

【図６】図５の断面図である。FIG. 6 is a sectional view of FIG. 5;

【図７】従来の集積回路装置を示す平面図である。FIG. 7 is a plan view showing a conventional integrated circuit device.

【図８】図７の断面図である。8 is a cross-sectional view of FIG.

【符号の説明】[Explanation of symbols]

１、１１、２０、２５……マルチチツプモジユール、２
……外部リード、３……リードフレームベース、４、１
４、２６……高密度多層配線基板、５、７、９、１３、
１５〜１８、２２、２３……接続用電極、６……ボンデ
イングワイヤ、８……配線、１０……モールドボデイ、
１２……低密度多層プリント配線基板、２１、２７……
配線リレージヨイントチツプ。1, 11, 20, 25 ... Multi-chip module, 2
...... External lead, 3 ...... Lead frame base, 4, 1
4, 26 ... High-density multilayer wiring board 5, 7, 9, 13,
15-18, 22, 23 ... Connection electrodes, 6 ... Bonding wire, 8 ... Wiring, 10 ... Mold body,
12 …… Low-density multilayer printed wiring board, 21, 27 ……
Wiring relay joint chip.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】半導体ベアチツプでなる複数の集積回路が
同一基板上に配設され、任意の複数の上記集積回路を電
気的に互いに接続した集積回路装置において、 上記接続の際に高密度配線が必要な上記複数の集積回路
下に、当該複数の集積回路同士を接続させるに必要な最
小限の面積を上記基板上で占有する高密度多層配線基板
を具えることを特徴とする集積回路装置。1. In an integrated circuit device in which a plurality of integrated circuits composed of semiconductor bare chips are arranged on the same substrate, and an arbitrary plurality of the integrated circuits are electrically connected to each other, a high-density wiring is formed during the connection. An integrated circuit device comprising a high-density multilayer wiring board that occupies a minimum area required for connecting the plurality of integrated circuits under the necessary plurality of integrated circuits on the board. 【請求項２】半導体ベアチツプでなる複数の集積回路が
同一基板上に配設され、任意の複数の上記集積回路を電
気的に互いに接続した集積回路装置において、 上記基板上に配設され、上記接続の際に複数の接続用電
極で対向する複数の上記集積回路を互いに隔てると共
に、当該複数の集積回路の上記複数の接続用電極を互い
に電気的に接続させる配線基板を具えることを特徴とす
る集積回路装置。2. In an integrated circuit device in which a plurality of integrated circuits made of semiconductor bare chips are arranged on the same substrate, and an arbitrary plurality of the integrated circuits are electrically connected to each other, the integrated circuit device is arranged on the substrate, When connecting, the plurality of integrated circuits facing each other with a plurality of connecting electrodes are separated from each other, and a wiring board for electrically connecting the plurality of connecting electrodes of the plurality of integrated circuits to each other is provided. Integrated circuit device. 【請求項３】上記配線基板は、多層配線基板でなること
を特徴とする請求項２に記載の集積回路装置。3. The integrated circuit device according to claim 2, wherein the wiring board is a multilayer wiring board.
JP7030031A 1995-01-25 1995-01-25 Integrated circuit device Pending JPH08204114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7030031A JPH08204114A (en) 1995-01-25 1995-01-25 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7030031A JPH08204114A (en) 1995-01-25 1995-01-25 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH08204114A true JPH08204114A (en) 1996-08-09

Family

ID=12292458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7030031A Pending JPH08204114A (en) 1995-01-25 1995-01-25 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH08204114A (en)

Similar Documents

Publication Publication Date Title
US6331939B1 (en) Stackable ball grid array package
US5245215A (en) Multichip packaged semiconductor device and method for manufacturing the same
US6380048B1 (en) Die paddle enhancement for exposed pad in semiconductor packaging
KR20020062820A (en) Semiconductor device having stacked multi chip module structure
JPH07283341A (en) Surface mounting type peripheral lead and ball grid array package
KR20020055603A (en) Dual-die integrated circuit package
JPH05109972A (en) Package assembly of lead frame and integrated circuit chip
JPS6290953A (en) Resin-sealed semiconductor device
US20080274588A1 (en) Semiconductor device and method of fabricating the same, circuit board, and electronic instrument
JPS61117858A (en) Semiconductor device
JPS5994441A (en) Semiconductor device
US20040245651A1 (en) Semiconductor device and method for fabricating the same
JPH1187400A (en) Semiconductor device
US5719748A (en) Semiconductor package with a bridge for chip area connection
KR100207902B1 (en) Multi chip package using lead frame
JPH1093013A (en) Semiconductor device
JPH08204114A (en) Integrated circuit device
JPS617657A (en) Package for multi-chip
JPH0697666A (en) Electronic device
JP3692353B2 (en) Assembling method of semiconductor device
JP2913858B2 (en) Hybrid integrated circuit
JPH0778938A (en) Composite semiconductor device and its manufacture
JPH11111910A (en) Multichip mount semiconductor device and its manufacture
JP2002124597A (en) Method for producing component surrounded with plastic and component surrounded with plastic
JPH0730067A (en) Semiconductor device