JP2003124331A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect a circuit from being deteriorated in performance or broken down due to a current or a voltage generated by electrostatic discharge. SOLUTION: A semiconductor integrated circuit device comprises a first chip 12a, a second chip 12b independent from the first chip 12a electrically, pads 15a and 15b arranged on the first and second chips 12a and 12b, respectively and connected with GND pins, pads 23a and 23b connected with the pads 15a, respectively, a bonding wire 24 for connecting the pads 23a and 23b, and protective circuits 22a and 22b disposed between the pads 15a, 23a and between the pads 15b, 23b, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a plurality of chips are arranged on a bed separated into a plurality of chips and integrated in one envelope.

[0002]

2. Description of the Related Art In recent years, due to improvements in semiconductor integration technology and advances in assembly technology, it has become common to package a plurality of chips into a single package. Further, when a plurality of circuits having different performances are mounted on a chip, in order to avoid interference, the chips having the circuits having different performances are arranged in separate beds. A conventional technique of such a semiconductor integrated circuit device will be described below.

FIG. 9 is a block diagram of a semiconductor integrated circuit device composed of two chips according to the prior art. As shown in FIG. 9, the first bed 11 a and the second bed 11 b are arranged on the substrate 10, respectively.
The first chip 12a and the second chip 12b having different circuit performances are arranged on the a and the second bed 11b, respectively. A first internal circuit portion 13a is provided in the first chip 12a.
Are arranged in the first internal circuit portion 13a.
4a and 15a are respectively connected. The pad 14a is connected to a power supply pin (not shown) by a bonding wire 16a, and the pad 15a is a GN by a bonding wire 18a.
It is connected to the D pin (not shown). Similarly, a second internal circuit portion 13b is arranged in the second chip 12b, and pads 14b and 15b are connected to the second internal circuit portion 13b, respectively. The pad 14b is connected to a power supply pin (not shown) by a bonding wire 16b, and the pad 1
5b is connected to a GND pin (not shown) by a bonding wire 18b. Then, the first chip 12a and the second chip
The pads 20a connected to the first internal circuit section 13a and the pads 20b connected to the second internal circuit section 13b are connected by the bonding wires 21 in order to transmit signals to and from the chip 12b.

[0004]

In the semiconductor integrated circuit device according to the above-mentioned prior art, in order to avoid interference between the chips 12a and 12b, the beds 11a and 11b are separated to divide the plurality of chips 12a and 12b. I placed it. As a result, an electrostatic discharge mode was generated which did not exist in the configuration in which only one chip was arranged in one envelope. In this electrostatic discharge mode, among the multiple chips, the pin that goes out of the envelope connected to the pad in one chip and the pin that goes out of the envelope connected to the pad in another chip That is, electrostatic discharge occurs between them. When such an electrostatic discharge mode occurs, there is a problem in that an instantaneous discharge current or voltage generated by static electricity across chips flows into an internal circuit, causing deterioration or destruction of elements in this circuit.

For example, the pad 1 on the second chip 12b
If electrostatic discharge occurs in the pad 14a connected to the power supply pin of the internal circuit portion 13a in the first chip 12a with reference to the GND pin connected to 5b, the first chip 1
2a and the second chip 12b are connected by the bonding wire 21, so that the instantaneous discharge current or voltage generated in the first chip 12a passes through the path 60 shown in FIG. Will flow into. Then, the current and voltage flowing into the second chip 12b are
There is a problem that the characteristic deterioration or destruction of the circuit element occurs when applied to the internal circuit portion 13b of the chip 12b, that is, the circuit for realizing the circuit function or characteristic required for the semiconductor integrated circuit.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of preventing deterioration and destruction of circuit performance.

[0007]

The present invention uses the following means in order to achieve the above object.

A semiconductor integrated circuit device according to a first aspect of the present invention is a semiconductor integrated circuit device in which a plurality of chips are mounted in one envelope, and the first chip, the first chip and the electrical circuit A second chip disposed independently of each other, a first pad disposed on the first chip and connected to a first GND pin, and a first pad disposed on the first chip,
A second pad connected to the first pad;
A third pad disposed on the second chip and connected to the second GND pin, a fourth pad disposed on the second chip and connected to the third pad, and the second pad. A first connecting member for connecting the fourth pad;
A protection circuit is provided between at least one of the first pad and the second pad and between at least one of the third pad and the fourth pad.

A semiconductor integrated circuit device according to a second aspect of the present invention is a semiconductor integrated circuit device in which a plurality of chips are mounted on one envelope, and these chips are respectively arranged on a bed separated into a plurality of chips. A first bed, a first chip disposed on the first bed, the first bed
A second bed disposed separately from the first bed, a second chip disposed on the second bed, and a first chip disposed on the first chip and connected to the first GND pin.
Pad and the first chip disposed on the first chip
A second pad connected to the pad, a third pad arranged on the second chip and connected to a second GND pin, and a third pad arranged on the second chip and A fourth pad for connection, a first connection member for connecting the second pad and the fourth pad, and the first
And a protection circuit disposed on at least one of the third pad and the fourth pad.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor integrated circuit device according to an embodiment of the present invention is one in which a plurality of chips are arranged on a bed divided into a plurality of pieces and integrated in one envelope. By allowing the instantaneous current and voltage generated by electrostatic discharge to escape via the protection circuit, it is possible to avoid deterioration or destruction of the element.

Embodiments of the present invention will be described below with reference to the drawings. In this description, common reference numerals are given to common portions throughout the drawings.

[First Embodiment] The first embodiment is an example in which a protection circuit is provided on each of a plurality of chips in order to release an instantaneous current or voltage generated by electrostatic discharge.

FIG. 1 is a schematic perspective view of a semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2 is a partially enlarged view of the semiconductor integrated circuit device shown in FIG.

As shown in FIGS. 1 and 2, a first bed 11a and a second bed 11b are arranged on a substrate 10, and the first bed 11a and the second bed 11b are arranged.
A first chip 12a and a second chip 12b having different circuit performances are arranged on the upper side. A first internal circuit section 13a is arranged in the first chip 12a, and pads 14a and 15a are connected to the first internal circuit section 13a. The pad 14a is connected to the power supply pin 17a by the bonding wire 16a, and the pad 15a is connected to the GND pin 19a by the bonding wire 18a. Similarly, in the second chip 12b, the second internal circuit portion 13b is included.
Are arranged in the second internal circuit portion 13b.
4b and 15b are respectively connected. The pad 14b is connected to the power supply pin 17b by a bonding wire 16b,
The pad 15b is connected to the GND pin 19b by a bonding wire 18b.

First chip 12a and second chip 12b
In order to transmit a signal to and from
The pad 20 a connected to a and the pad 20 b connected to the second internal circuit portion 13 b are connected by the bonding wire 21.

First pad 15a of first chip 12a
Is connected to the first protection circuit 22a.
The pad 23a is connected to a. Similarly, the second protection circuit 22b is connected to the pad 15b of the second chip 12b, and the pad 23b is connected to the first protection circuit 22b. Then, the pad 23a and the pad 23b are connected by the bonding wire 24.

Here, the protection circuits 22a and 22b are arranged on the outer peripheral portions of the chips 12a and 12b so as to be arranged outside the internal circuit portions 13a and 13b of the chips 12a and 12b. Further, in order to release the current or voltage due to static electricity using the protection path 25, the resistance in the A region needs to be lower than the resistance in the B region.

In wire bonding, the substrate of each chip is short-circuited to the bed. Therefore, when the beds are not divided into a plurality of beds, the substrates of each chip are electrically short-circuited in the same bed, and the substrate of each chip is short-circuited. Are no longer electrically independent. On the other hand, in the first embodiment of the present invention, separate beds 11a and 11b are provided, and the first and second chips 12 are provided on the beds 11a and 11b.
By arranging a and 12b respectively, the substrates of the first and second chips 12a and 12b are brought into an electrically independent state. In other words, the substrates of the chips 12a and 12b are not directly short-circuited by the electrical wiring. This is because the first and second chips 12a and 12b have different circuit performances as described below, and therefore, a problem due to the difference in the circuit performances is avoided.

For example, the frequencies used by the first chip 12a and the second chip 12b are different. In addition, the first chip 12a has a power supply voltage of 10V and the second chip 12a has a power supply voltage of 100V.
And the power supply voltage value of the second chip 12b differs by at least twice. In addition, the first chip 12a and the second chip 1
The timing of turning on and off the power source is different from that of 2b.
The second chip 12b is turned on or off when the first chip 12a is turned on, and the second chip 12b is turned on or off when the first chip 12a is turned off.
The chip 12b of is turned on. In some cases, one of the first chip 12a and the second chip 12b uses an analog signal and the other of the first chip 12a and the second chip 12b uses a digital signal.

Also, the first and second internal circuit portions 13a, 1
Reference numeral 3b is a circuit that realizes circuit functions and characteristics required for a semiconductor integrated circuit.

3 to 5 are specific block diagrams of the protection circuit according to the first embodiment of the present invention. The protection circuits 22a and 22b may have any of the structures shown in FIGS. 3 to 5, and in order to achieve the purpose,
The structure shown in FIG. 3A or FIG. 4A is preferable.

As shown in FIG. 3A, the protection circuit 22
a and 22b are two diodes 31 connected in parallel,
32 may be included. Further, as shown in FIG. 3B, in the protection circuits 22a and 22b, a plurality of diodes 31 and 33 connected in series and a plurality of diodes 32 and 34 connected in series may be connected in parallel.

As shown in FIG. 4A, the protection circuit 22
a and 22b are a transistor 41 and a resistor 42 connected in series, and a transistor 43 and a resistor 4 connected in series.
4 may be connected in parallel. Further, as shown in FIG. 4B, in the protection circuits 22a and 22b, transistors 41 and 45 and resistors 42 and 46 connected in series and transistors 43 and 47 and resistors 44 and 48 connected in series are connected in parallel. May be connected.

As shown in FIG. 5A, the protection circuit 22
a and 22b are two transistors 5 connected in parallel.
It may be composed of 1, 52. Further, as shown in FIG. 5B, in the protection circuits 22a and 22b, a plurality of transistors 51 and 53 connected in series and a plurality of transistors 52 and 54 connected in series may be connected in parallel.

According to the first embodiment, between the pads 15a and 15b connected to the GND pins 19a and 19b,
Since the first protection circuit 22a, the pad 23a, the bonding wire 24, the pad 23b, and the second protection circuit 22b are arranged, the following effects can be obtained.

For example, when electrostatic discharge occurs in the pad 14a connected to the power supply pin 17a of the internal circuit portion 13a in the first chip 12a, with reference to the pad 15b connected to the GND pin 19b in the second chip 12b. Suppose. In this case, in the first embodiment, since the protection path 25 shown by the broken line in FIG. 2 can be formed, the first chip 12a can be formed.
The current or voltage due to the static electricity generated inside does not flow into the second chip 12b via the bonding wire 21 and passes through the protection path 25 to the GND of the second chip 12b.
It can be released to the pin 19b. That is, the internal circuit portion 13b of the second chip 12b can be discharged to the outside without applying an instantaneous current or voltage.

As described above, in the first embodiment, even when the electrostatic discharge mode across a plurality of chips occurs, it is possible to avoid deterioration or destruction of elements in the internal circuit. Therefore, even when electrostatic discharge occurs, in the manufacturing process of the semiconductor integrated circuit, the manufacturing process of the electric product equipped with the semiconductor integrated circuit, the use of the electric product equipped with the semiconductor integrated circuit, etc. It is possible to avoid the problems of performance deterioration and element destruction of the semiconductor integrated circuit and electrical products equipped with this semiconductor integrated circuit. Therefore, the reliability of the semiconductor integrated circuit device against electrostatic discharge can be improved.

Further, the protection circuits 22a and 22b can be formed with a simple structure as shown in FIGS. 3 to 5, and the protection circuits 22a and 2b can be formed when the protection path 25 is formed.
It does not require the complicated connection of 2b. Therefore, the semiconductor integrated circuit device can be easily manufactured, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

In the first embodiment, the case where two chips are mounted has been described as an example, but two or more chips may be mounted. For example, a first pad for connecting the chips and a second pad connected to the GND pin are provided on each chip, and the first pad of each chip is connected by a bonding wire to form the first pad. A protection circuit may be provided between the second pads. Also in this case, the same effect as that of the first embodiment can be obtained.

[Second Embodiment] In the second embodiment, in the semiconductor integrated circuit device shown in the first embodiment, the protection circuit on one chip is omitted and the protection path is shortened. .

6 and 7 are plan views of a semiconductor integrated circuit device according to the second embodiment of the present invention. Below, the second
The semiconductor integrated circuit device according to the embodiment will be described. In the semiconductor integrated circuit device according to the second embodiment, the description of the same structure as the semiconductor integrated circuit device according to the first embodiment will be omitted, and only the different structure will be described.

First, the structure shown in FIG. 6 has the protection circuit 22a arranged on the first chip 12a in the first embodiment.
Pad 1 connected to GND pin (not shown)
Pad 23a connecting between 5a and chips 12a, 12b
And are directly connected. Therefore, the pad 23a, the bonding wire 24, the pad 23b, and the protection circuit 22b are arranged between the pads 15a and 15b connected to the GND pin.

On the other hand, the structure shown in FIG. 7 has the protection circuit 22b arranged on the second chip 12b in the first embodiment.
Pad 1 connected to GND pin (not shown)
Pad 23b for connecting between 5b and chips 12a, 12b
And are directly connected. Therefore, the protection circuit 22a to the pad 23a to the bonding wire 24 to the pad 23b are arranged between the pads 15a and 15b connected to the GND pin.

According to the second embodiment, the same effect as that of the first embodiment can be obtained.

Further, compared to the first embodiment, the protection path 25 can be formed with a smaller number of protection circuits. For this reason, it becomes easier for the protection path 25 to be discharged, and deterioration and destruction of the circuit element due to electrostatic discharge can be avoided.

In addition, the present invention is not limited to each of the above-described embodiments, and can be variously modified in an implementation stage without departing from the scope of the invention. That is,
In the first and second embodiments, the case where the bonding wires are used for the connection between the pads has been described as an example, but the connecting member is not limited to the bonding wires. For example, the connection between the pads is made by TA using the TAB (Tape Automated Bonding) technique shown in FIGS. 8A and 8B.
The connection may be performed using a B tape or a connecting member using BGA (Ball Grid Array) technology. It is also possible to connect the pads using a wiring board.

Further, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problem described in the section of the problem to be solved by the invention can be solved, and the effect described in the section of the effect of the invention can be solved. When the above is obtained, the configuration in which this constituent element is deleted can be extracted as the invention.

[0038]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device capable of preventing deterioration and destruction of circuit performance.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

2 is a partially enlarged view of the semiconductor integrated circuit device shown in FIG.

FIG. 3 is a circuit diagram showing a specific example of a protection circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a specific example of a protection circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific example of a protection circuit according to the first embodiment of the present invention.

FIG. 6 is a schematic plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a schematic plan view showing another semiconductor integrated circuit device according to the second embodiment of the invention.

8 (a) is a schematic plan view showing a semiconductor integrated circuit device using a TAB according to the first and second embodiments of the present invention, and FIG. 8 (b) is FIG. 8 (a). VIIIb-VI shown in
Sectional drawing of the semiconductor integrated circuit device along the IIb line.

FIG. 9 is a schematic plan view showing a semiconductor integrated circuit device according to a conventional technique.

[Explanation of symbols]

10 ... Board, 11a, 11b ... Bed, 12a, 12b ... Chip, 13a, 13b ... Internal circuit part, 14a, 14b, 15a, 15b, 20a, 20b, 2
3a, 23b ... Pad, 16a, 16b, 18a, 18b, 21, 24 ... Bonding wire, 17a, 17b ... Power supply pin, 19a, 19b ... GND pin, 22a, 22b ... Protect circuit, 25 ... Protect path.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shuichi Sakai             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Ikuo Yoshii             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Kenji Hara             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5F038 BE07 BH02 BH04 BH06 BH13                       CA10 EZ07 EZ20                 5F067 AA02

Claims (12)

[Claims] 1. A semiconductor integrated circuit device in which a plurality of chips are mounted on one envelope, wherein a first chip and a second chip are arranged electrically independent of the first chip. A first pad disposed on the first chip and connected to a first GND pin; a second pad disposed on the first chip and connected to the first pad; A third pad disposed on the second chip and connected to the second GND pin; a fourth pad disposed on the second chip and connected to the third pad; A first connecting pad and the fourth pad
Integrated circuit, and a protection circuit disposed on at least one of the first pad and the second pad and between the third pad and the fourth pad. Circuit device. 2. A plurality of chips are mounted on one envelope,
A semiconductor integrated circuit device in which these chips are respectively arranged on a bed separated into a plurality of, wherein a first bed, a first chip arranged on the first bed, and the first bed A second bed separately disposed, a second chip disposed on the second bed, a first pad disposed on the first chip and connected to a first GND pin A second pad disposed on the first chip and connected to the first pad; a third pad disposed on the second chip and connected to a second GND pin; A fourth pad arranged on a second chip and connected to the third pad; and a first pad connecting the second pad and the fourth pad.
Integrated circuit, and a protection circuit disposed on at least one of the first pad and the second pad and between the third pad and the fourth pad. Circuit device. 3. The frequencies used in the first chip and the second chip are different from each other.
Or the semiconductor integrated circuit device according to 2. 4. The semiconductor integrated circuit device according to claim 1, wherein the first chip and the second chip have different power supply voltage values. 5. The semiconductor integrated circuit device according to claim 1, wherein the first chip and the second chip are different in power supply voltage value by two times or more. 6. The semiconductor integrated circuit device according to claim 1, wherein the first chip and the second chip have different power-on and power-off timings. 7. The one of the first chip and the second chip uses an analog signal, and the other of the first chip and the second chip uses a digital signal. Or the semiconductor integrated circuit device according to 2. 8. The semiconductor integrated circuit device according to claim 1, wherein the first connecting member is any one of a bonding wire, a TAB tape, a connecting member using a BGA technique, and a wiring board. 9. The semiconductor integrated circuit device according to claim 1, wherein the first connecting member is any one of a bonding wire, a TAB tape, and a connecting member using BGA technology. 10. The semiconductor integrated circuit device according to claim 1, wherein the first connecting member is a bonding wire. 11. A fifth pad arranged on the first chip and connected to the second chip, and a sixth pad arranged on the second chip and connected to the first chip. A second pad connecting the fifth pad and the sixth pad
3. The semiconductor integrated circuit device according to claim 1, further comprising: 12. A first internal circuit portion arranged on the first chip and connected to the first pad and the fifth pad; a third internal circuit portion arranged on the second chip; 12. The semiconductor integrated circuit device according to claim 11, further comprising a second internal circuit portion connected to the pad and the sixth pad.