JPS6011462B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6011462B2 JPS6011462B2 JP52009910A JP991077A JPS6011462B2 JP S6011462 B2 JPS6011462 B2 JP S6011462B2 JP 52009910 A JP52009910 A JP 52009910A JP 991077 A JP991077 A JP 991077A JP S6011462 B2 JPS6011462 B2 JP S6011462B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor element
- semiconductor
- wiring
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は半導体素子用パッケージのリード配線部の構
造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a lead wiring portion of a package for a semiconductor element.
半導体素子においては、その素子面積を出来るだけ小さ
くすることは歩留向上の為に最も重要なことである。In semiconductor devices, it is most important to make the device area as small as possible in order to improve yield.
半導体素子の電源線やグランド線は電流許容量、グラン
ド線の低抗による電位の特上り等の制限のため、太い配
線が必要である。例えば、長方形の半導体素子上の一辺
にグランド線のボンディングパッドがあって、その相対
する辺に電流を多く流す回路が存在する場合には、その
電流がその回路からグランドパッドまでの配線抵抗によ
り、その回路のグランド電位を上昇させる値をその回路
が動作上必要とされる値以下に抑えるのに必要なだけ「
グランド配線を太くしてその配線抵抗を下げてやる必
要がある。半導体集積回路装置の大容量化が進み、素子
の大きさが大きくなるに従って、電源線から供給する電
力を消費する回路が素子上の各所に存在することになる
が、それ等の間をつないで、電源線、グランド線をそれ
ぞれボンディングパッドまで、太く配線することになる
。Power supply lines and ground lines for semiconductor devices require thick wiring due to limitations such as current capacity and potential rise due to low resistance of the ground line. For example, if there is a bonding pad for a ground line on one side of a rectangular semiconductor element, and there is a circuit that flows a large amount of current on the opposite side, the current will flow due to the wiring resistance from that circuit to the ground pad. Only the amount necessary to keep the circuit's ground potential raised below the value required for operation of the circuit.
It is necessary to make the ground wiring thicker and lower the wiring resistance. As the capacity of semiconductor integrated circuit devices continues to increase and the size of devices becomes larger, circuits that consume power supplied from the power supply line will be present in various places on the device. , the power supply line, and the ground line must be thickly routed to the bonding pads.
そのため、素子設計が複雑になることもあり、素子寸法
は大きくなり、その分だけ、歩留を悪くする原因となっ
ている。この発明の目的は、半導体集積回路素子の歩蟹
に重大な影響を及ぼす素子寸法を小さくすることが出来
、高歩留り、低価格な半導体集積回路装置の製作を可能
にする新しいパッケージを提供する事にある。この発明
によれば、半導体素子等のパッケージにおいて、同一機
能を有するリード端子が半導体素子を迂回して設けられ
たりード配線と一体に複数個配置され、該複数個あるリ
ード端子から、半導体素子に複数個のボンディングが可
能であり、この発明によるパッケージを用いる事により
、半導体素子内で同一機能を持った配線を不必要に走ら
せる必要がなく、半導体素子の素子寸法を小さくし、素
子設計を容易にする事が出来、高歩蟹り、低価格な半導
体集積回路装置の製作が可能となる。Therefore, the device design may become complicated, and the device dimensions become large, which causes a corresponding decrease in yield. An object of the present invention is to provide a new package that can reduce the element dimensions, which have a significant effect on the growth of semiconductor integrated circuit elements, and that enables the production of high-yield, low-cost semiconductor integrated circuit devices. It is in. According to the present invention, in a package for a semiconductor element, etc., a plurality of lead terminals having the same function are provided bypassing the semiconductor element or are arranged integrally with the lead wiring, and from the plurality of lead terminals, the semiconductor element By using the package according to the present invention, there is no need to unnecessarily run wiring with the same function within the semiconductor element, and the element size of the semiconductor element can be reduced, making it easier to design the element. This makes it possible to easily manufacture semiconductor integrated circuit devices at low cost.
次にこの発明の特徴をより良く理解するために、この発
明の実施例につき、図を用いて説明する。Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.
第１図は、従来使用されている半導体素子等のパッケー
ジを用いた場合の半導体素子を示す。第１図のａ点がグ
ランド電位のボンディングパツドであるが、そのボンデ
ィングパッドから、グランド配線を半導体素子Ｅ上の各
回路に走らせるわけであるが「今、そのグランドパッド
のある辺の反対側の辺に大電流を流す回路Ａが存在する
場合、従来はａから「Ａに太いグランド線を必要とした
。すなわち途中の回路で太いグランド線が必要でなくと
も大電流を流す回路Ａのグランド電位の特上りを回路動
作上必要とされる値以下にするために太い配線をはりめ
ぐらせる必要があるわけである。その結果、素子寸法は
大きくなり、それは歩留の低下をもたらす。第２図はこ
の発明の一実施例を説明するためのＩＪ−ドフレームを
有するパッケージにおいて、リードフレームと半導体素
子との関連のみを示す。つまり、グランド電位のリード
端子を半導体素子の側面を迂回して別の点、この図の例
では、ｂ′点からｃ′点まで延ばし、半導体素子上では
、新たに、ｄ′のボンディングパッドをもうけて、Ａ′
の回路のグランド電位は、このｄ′のパッドから供給す
る。こうすることによって「半導体素子中では、第１図
にある様な太いグランド線に配線する必要がなくなり、
その分だけ、半導体素子寸法を小さくすることが出来る
。以上説明した様に、この発明による半導体素子等のパ
ッケージは従来の半導体素子上の太い配線を少くし、素
子面積を減らし、高歩蟹りの半導体集積回路装置が得ら
れる。もっと具体的に実施例について説明を行う。FIG. 1 shows a semiconductor element using a conventionally used package for semiconductor elements. Point a in Figure 1 is the bonding pad at ground potential, and from that bonding pad, ground wiring is run to each circuit on the semiconductor element E. When there is a circuit A that flows a large current on the side, conventionally, a thick ground wire was required from a to A.In other words, even if a thick ground wire is not required in the middle circuit, it is necessary to connect the circuit A that flows a large current. In order to reduce the rise in the ground potential below the value required for circuit operation, it is necessary to run thick wiring.As a result, the element size increases, which causes a decrease in yield.Second. The figure shows only the relationship between the lead frame and the semiconductor element in a package having an IJ-shaped frame for explaining an embodiment of the present invention.In other words, the lead terminal at ground potential is routed around the side of the semiconductor element. Another point, in the example in this figure, is extended from point b' to point c', and on the semiconductor element, a new bonding pad of d' is created, and A'
The ground potential of the circuit is supplied from this pad d'. By doing this, ``there is no need to wire a thick ground line in the semiconductor element as shown in Figure 1,''
The size of the semiconductor element can be reduced accordingly. As described above, the package for a semiconductor device or the like according to the present invention can reduce the number of thick wirings on a conventional semiconductor device, reduce the device area, and provide an improved semiconductor integrated circuit device. Examples will be explained more specifically.
第２図では樹脂封止パッケージのリードフレームの例で
あるが、半導体素子をのせるアイランド部Ｄと他のボン
ディング端子の間を通って、リード端子が反対側まで伸
びているが、このリード端子に他のボンディング端子ｇ
，ｆ′，ｅ’から出るボンディング線が接触しないよう
に、その区間のリード端子をアイランド部と他の端子の
面より低くする。（第３図）、リード端子のある区間を
他のりード端子やアイランドの面より低くする場合には
、リードフレームをのせる台はその部分に溝を作ってお
けばよい。尚、この発明は、上述の実施例に説明された
範囲に限定されるものではなく、この発明の技術的思想
を逸脱しない範囲で変更可能である。例えばセミラック
基板上に配線を設ける場合においても、その配線の一部
を素子を迂回させて、第２図と同様に構成することもで
きる。Figure 2 shows an example of a lead frame for a resin-sealed package, and the lead terminals pass between the island portion D on which the semiconductor element is mounted and other bonding terminals and extend to the opposite side. to other bonding terminals
, f', and e', the lead terminal in that section is made lower than the surface of the island part and other terminals so that the bonding wires coming out from the terminals do not come into contact with each other. (Fig. 3), if a certain section of the lead terminal is to be lower than other lead terminals or the surface of the island, the table on which the lead frame is placed may have a groove in that part. Note that this invention is not limited to the scope described in the above-mentioned embodiments, and can be modified without departing from the technical idea of this invention. For example, even when wiring is provided on a semirac board, a part of the wiring can be made to bypass the element, and the configuration can be similar to that shown in FIG. 2.
第１図は従来のパッケージにおけるリードフレームの一
例を示す図、第２図は本発明の一実施例におけるリード
フレーム部の平面図、第３図はその側面図を示す。
図において、Ｅは半導体素子、Ｄはアイランド部、ｂ′
，ｃ′，ｇ，ｆ′，ｅ′はリード端子、ａ′，ｄ′はボ
ンディングパッドを示す。
オ′滋
ナ２舷
ガう図FIG. 1 is a diagram showing an example of a lead frame in a conventional package, FIG. 2 is a plan view of a lead frame portion in an embodiment of the present invention, and FIG. 3 is a side view thereof. In the figure, E is a semiconductor element, D is an island part, and b'
, c', g, f', and e' are lead terminals, and a' and d' are bonding pads. Diagram showing the two sides of the ship
Claims (1)
該半導体基板の周辺部に先端部が位置するように配置さ
れ、該先端部と前記ボンデイングパツドとが電気的に接
続される複数の外部導出用リードと、該外部導出用リー
ドの先端部と前記半導体基板との間に前記半導体基板の
周辺に沿って延長する延長部を有し、該延長部は前記外
部導出用リードの先端部が形成する面より低く形成され
ており、かつ前記延長部を含む先端部には前記ボンデイ
ングパツドの複数が電気的に接続されている外部導出用
リードとを有することを特徴とする半導体装置。1. A semiconductor substrate having a plurality of bonding pads;
a plurality of external lead-out leads disposed such that their tips are located at the periphery of the semiconductor substrate, and whose tips are electrically connected to the bonding pad; and the tips of the external lead-out leads; an extension part extending along the periphery of the semiconductor substrate between the semiconductor substrate, the extension part being formed lower than the surface formed by the tip of the lead for external extraction, and the extension part What is claimed is: 1. A semiconductor device comprising: a lead for leading to the outside, to which a plurality of the bonding pads are electrically connected;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52009910A JPS6011462B2 (en) | 1977-01-31 | 1977-01-31 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52009910A JPS6011462B2 (en) | 1977-01-31 | 1977-01-31 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5394875A JPS5394875A (en) | 1978-08-19 |
| JPS6011462B2 true JPS6011462B2 (en) | 1985-03-26 |
Family
ID=11733253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52009910A Expired JPS6011462B2 (en) | 1977-01-31 | 1977-01-31 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6011462B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6232682A (en) * | 1985-08-03 | 1987-02-12 | 株式会社 ニフコ | Improvement in integration density for 3-d circuit structural body |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58110063A (en) * | 1981-12-23 | 1983-06-30 | Nec Corp | Integrated circuit device |
| JPS593960A (en) * | 1982-06-29 | 1984-01-10 | Toshiba Corp | Semiconductor device |
| JPS625649A (en) * | 1985-07-01 | 1987-01-12 | Nec Ic Microcomput Syst Ltd | Package for integrated circuit |
| JPS6314438A (en) * | 1986-07-04 | 1988-01-21 | Mitsubishi Electric Corp | Semiconductor device |
| JP2562773Y2 (en) * | 1989-04-05 | 1998-02-16 | 三洋電機株式会社 | Semiconductor integrated circuit device |
| JPH0760837B2 (en) * | 1990-03-13 | 1995-06-28 | 株式会社東芝 | Resin-sealed semiconductor device |
| JPH0760838B2 (en) * | 1990-11-13 | 1995-06-28 | 株式会社東芝 | Semiconductor device |
| JPH0521691A (en) * | 1991-12-05 | 1993-01-29 | Hitachi Ltd | Semiconductor device and assembling method thereof |
| JP2501382B2 (en) * | 1991-12-05 | 1996-05-29 | 株式会社日立製作所 | Method for assembling semiconductor device |
| JP2614681B2 (en) * | 1991-12-05 | 1997-05-28 | 株式会社 日立製作所 | Semiconductor device |
-
1977
- 1977-01-31 JP JP52009910A patent/JPS6011462B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6232682A (en) * | 1985-08-03 | 1987-02-12 | 株式会社 ニフコ | Improvement in integration density for 3-d circuit structural body |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5394875A (en) | 1978-08-19 |
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