JPS58110063A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS58110063A
JPS58110063A JP20877481A JP20877481A JPS58110063A JP S58110063 A JPS58110063 A JP S58110063A JP 20877481 A JP20877481 A JP 20877481A JP 20877481 A JP20877481 A JP 20877481A JP S58110063 A JPS58110063 A JP S58110063A
Authority
JP
Japan
Prior art keywords
package
integrated circuit
terminals
external connection
outside connecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20877481A
Other languages
Japanese (ja)
Inventor
Kazuo Okano
岡野　一雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP20877481A priority Critical patent/JPS58110063A/en
Publication of JPS58110063A publication Critical patent/JPS58110063A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive to increase electric power supply capacity of the integrated circuit device without enlarging the shape of a package by a method wherein outside connecting terminals for electric power source supply of a minimum small number are used. CONSTITUTION:The outside connecting terminals for electric power source supply are distributed inside of the package, and are connected to inside electrodes of a larger number than the outside terminals. For example, the outside connecting terminals 11, 12 for the highest, the lowest potentials are made respectively as one piece, and are distributed respectively to the plural pieces by metalized wirings 18, 19 inside of the package to be connected to the inside electrodes 14. Or to connect the outside connecting terminal of one piece to the inside electrodes of the large number through a die attaching part is favorable, and at this case, because metal plating is performed to the die attaching part and metal brazing is performed to the IC, electric resistance is reduced remarkably, and dispersion of voltages between the respective inside electrodes is small. Or to distribute and to connect the outside connecting terminal to the inside electrodes of the plural number through a metal part for sealing of the package is also favorable. According to the construction thereof, resistance between the outside connecting terminal and the inside electrode is reduced, and large electric power can be supplied to the IC from the outside terminals of a small number without a hindrance.

Description

【発明の詳細な説明】 本発明は、半導体装慣の構造に関し、特に消費電力の大
きい集積回路装置の構造ｐｃ関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, and particularly to the structure PC of an integrated circuit device that consumes a large amount of power.

近年、集積回路の高集積化に伴って多叙の外部接続端子
を必要とし、かつ大ζ力を陶費する集積回路装置が要求
さｎている。In recent years, as integrated circuits have become more highly integrated, there has been a demand for integrated circuit devices that require multiple external connection terminals and consume a large amount of power.

従来のこの種の集積回路装置においては、集積回路素子
に大電力を供給するために第１図に示すように、集積回
路素子を収納するパッケージにおける電源供給用の外部
接続端子を沙数本にして、電力を供給していた。第１図
において、外部接続端子１．１．２．２．３．３．・・
・・・・の内、外部接続端子１．１は、最高電位の電源
供給用であり、外部接続端子２．２は、最低電位の電源
供給用である。ま良、こｆら以外の○印を付した外部Ｗ
Ａｆａ端子３．３・・・・・・は、信号用の外部接続端
子である。In conventional integrated circuit devices of this type, in order to supply a large amount of power to the integrated circuit elements, as shown in Figure 1, the package that houses the integrated circuit elements has several external connection terminals for power supply. It was supplying electricity. In FIG. 1, external connection terminals 1.1.2.2.3.3.・・・
. . , the external connection terminal 1.1 is for supplying power at the highest potential, and the external connection terminal 2.2 is for supplying power at the lowest potential. External W marked with ○ other than Mara and Kof.
Afa terminals 3.3... are external connection terminals for signals.

こｎらの接続端子は、そｎ−ｒｎ対応するパッケージ内
部電極４，４．５．５、および６．６・・・・・・に配
線７．７・・・・・・によシ接トされている。従って、
集積回路素子には、そｎぞｆ′Ｌ２本の最高電位の内部
電極から電力が供給さｆる構造となっている。These connection terminals are connected to the corresponding package internal electrodes 4, 4, 5.5, and 6.6 through wiring 7.7. has been recorded. Therefore,
The integrated circuit element has a structure in which power is supplied from the two internal electrodes having the highest potential f'L.

しかしながら、このような構造の集積回路素子ＶＣは下
記のような欠点がある。すなわち、上述のように、大電
力を供給すぎために、篭カ供給用の外部接続端子数を増
加させると、信号用の外部接続端子数が減少する。第１
図においては、全外部接続端子数は２０本であり、最高
電位用最低電位用に各２本の電源供給用外部接続端子を
使用しているため、信号用の外部接続端子は１６本とな
っている。さらに大きな′幽、力を供給する際には、最
高電位用、最低電位用をそれぞれ４本づつで、８本の電
力供給用外部接続端子が必要となる。このような場合に
は、信号用の接続端子は１２本となってしまう。そこで
、外部接続端子数を増した大型パッケージを使用しなけ
ｎげならなくなる。このような大型パッケージは、実装
密度、コストの点で小型パッケージより不利なことは明
らかである。However, the integrated circuit element VC having such a structure has the following drawbacks. That is, as described above, if the number of external connection terminals for cage supply is increased because too much power is supplied, the number of external connection terminals for signal use is decreased. 1st
In the figure, the total number of external connection terminals is 20, and two external connection terminals for power supply are used for the highest potential and the lowest potential, so the number of external connection terminals for signals is 16. ing. When supplying even greater force, eight external connection terminals for power supply are required, four for the highest potential and four for the lowest potential. In such a case, the number of signal connection terminals would be 12. Therefore, it becomes necessary to use a large package with an increased number of external connection terminals. It is clear that such a large package is disadvantageous compared to a small package in terms of packaging density and cost.

本発明の目的は、上述のような欠点を除去し、できる限
９少ない′１源供給用の外部接続端子の本数でもって、
パック°−ジ形状を大きくせずに、電力供給耐量を増加
できる集積回路装置を提供することである。The object of the present invention is to eliminate the above-mentioned drawbacks and reduce the number of external connection terminals for power supply to the minimum possible.
An object of the present invention is to provide an integrated circuit device capable of increasing power supply capacity without enlarging the package size.

本発明の集積回路装置では、重連供給用の外部接続端子
をパッケージ内で分配し、外部接続端子よシ多い数の内
部電極に接続した構成を有する。The integrated circuit device of the present invention has a configuration in which external connection terminals for multiple supply are distributed within the package and connected to a larger number of internal electrodes than the external connection terminals.

つぎに本発明を実施例によシ鯖明する。Next, the present invention will be explained with reference to examples.

第２図は本発明の一実施例に係る集積回路用パッケージ
の接続図である。第２図において、最高電位用、最低電
位用の外部接続端子１１．１２をそれぞれ１個とし、パ
ッケージ内のメタライズ配線１８．１９によシそｎぞれ
２本に分配して、最高電位用、最低電位用の内部電極１
４，１４ふ−よび１５．１５にそれぞｆｉ接続している
。FIG. 2 is a connection diagram of an integrated circuit package according to an embodiment of the present invention. In Fig. 2, there is one external connection terminal 11.12 for the highest potential and one for the lowest potential, and they are distributed into two each on the metallized wiring 18.19 in the package. , internal electrode 1 for lowest potential
4, 14 and 15.15, respectively.

このような構造のメタライズ配線は、スルーホールを用
いた多層配線技術により容易に実現することができる。Metallized wiring having such a structure can be easily realized by multilayer wiring technology using through holes.

第２図において、最高電位用の外部接続端子１１は１本
で、該端子は２本に分配さｎｌ　２個の内部電極１４に
接続さｎているが、さらに、　　１本の外部接続端子１
１を４本、８本に分配して、４個、８個の内部電極に接
続することも可能である。また、最高′串位用外部接続
端子を複数本にし、そｎぞｎの端子を複数に分配して多
数の最高′酸位用の内部’［極を設けることも可能であ
る。このような構造は、最低電位用の外部接続端子、内
部ＩＫ檜に対しても同様に適用できる。In FIG. 2, there is one external connection terminal 11 for the highest potential, and this terminal is divided into two terminals, which are connected to two internal electrodes 14, and one external connection terminal 1.
It is also possible to divide 1 into 4 or 8 wires and connect them to 4 or 8 internal electrodes. Furthermore, it is also possible to provide a plurality of external connection terminals for the highest acid level and distribute each n terminal into a plurality of terminals to provide a large number of internal electrodes for the highest acid level. Such a structure can be similarly applied to the external connection terminal for the lowest potential and the internal IK.

上述の第１図の例においては、外部接続端子と内部１！
極間をメタライズ配線により分配、接続しているが、ダ
イアタッチ部を介して１本の外部接続端子を多数個の内
部電極に接続してもよい。この構造を採用すると、メタ
ライズ配線によシ外部接続端子を分配し内部′Ｉｌ極と
接続した場合に比べ、各内部′ｄＬ椿間の電圧のばらつ
きが小さくなる。一般にダイアタッチ部には、集積回路
素子を取付るために金属メッキを施し、１らに、金属ろ
う材料を用いるので、メタライズ配、紛に比べ′醒気抵
抗が著しく小さくなるためである。In the example shown in FIG. 1 above, the external connection terminal and the internal 1!
Although the electrodes are distributed and connected by metallized wiring, one external connection terminal may be connected to a large number of internal electrodes via a die attach portion. When this structure is adopted, the variation in voltage between each internal 'dL' pole becomes smaller compared to the case where the external connection terminals are distributed through metallized wiring and connected to the internal 'Il' pole. Generally, the die attach portion is plated with metal to attach the integrated circuit element, and first, a metal brazing material is used, so that the resistance to air flow is significantly lower than that of a metallized solder.

また、外部接続端子を仲数個の内部′１１極に封止用の
金用部を介（、て分配、接続してもよい。ここで封止用
の金Ｍ部とは、金属ろう材にて封止する構造のバック°
−ジにおいては、パッケージ上のメ５− タライズ部、封止用の金属ろう材、金属キャップ等を意
味し、シームウェルド封止パッケージ＆Ｃついては、シ
ームウェルド用の金−枠体、ψ拭キャップ等を意味する
。このような＋坂によっても、外部接続端子と内部電極
間の抵抗を小ツくシ、少い本数の電源供給用外部端子で
もって、大電力の集積回路に支障なく電力を供給するこ
とができる。In addition, the external connection terminals may be distributed and connected to several internal 11 poles via the sealing metal part.Here, the sealing gold part is the metal brazing material. The back of the structure is sealed with °
For seam-welded package &C, it means the metalized part on the package, metal brazing material for sealing, metal cap, etc., and for seam-weld sealed package &C, it means the metalized part for seam-weld, ψ wiping cap, etc. means. Even with such a + slope, the resistance between the external connection terminal and the internal electrode can be reduced, and power can be supplied to a high-power integrated circuit without any problems with a small number of external power supply terminals. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の集積回路用パッケージ、＃）外部接続端
子とパッケージ内部由′俸間の接＝＝Ｘ　、、第２図は
本発明の一実施例に係る集積回路用パッケージの接続図
である。 １．２，１１．１２・・・・・・Ｍ源供給用外部接ｄ端
子、３．１３・・・・・・信号用外部接＠端子、４．５
゜１４．１５・・・・・・電源供給用外部端子、６．１
６・・・・・・信号用内部電極、７，１８．１９・・・
・・・外部接続端子と内部電極間の配線。 ６−Figure 1 shows a conventional integrated circuit package; be. 1.2, 11.12... External connection d terminal for M source supply, 3.13... External connection @ terminal for signal, 4.5
゜14.15... External terminal for power supply, 6.1
6...Internal electrode for signal, 7,18.19...
...Wiring between external connection terminals and internal electrodes. 6-

Claims (1)

【特許請求の範囲】 １１１　　集積回路素子と、この集積回路素子を搭載す
るパッケージとを備えた集積回路装置において、前記パ
ッケージの１に源供給用外部接続端子が、該接続端子よ
シ多い数のパッケージ内部電極に接続さｎていることを
特徴とする集積回路装置。 （２）前記外部接続端子と前記内部電極とがダイアタッ
チ部を介して接続さｎていることを特徴とする特許請求
の範囲第１項に記載の集積回路装置。 （３）前記外部接続端子とｉＩＩ記内部電極とが封止用
金属部を介して接続さｎていることを特徴とする特許請
求の範囲第１項に記載の集積回路装置。[Claims] 111. In an integrated circuit device comprising an integrated circuit element and a package on which the integrated circuit element is mounted, one of the packages has external connection terminals for power supply, the number of which is greater than the number of connection terminals. An integrated circuit device, characterized in that the integrated circuit device is connected to an internal electrode of a package. (2) The integrated circuit device according to claim 1, wherein the external connection terminal and the internal electrode are connected via a die attach portion. (3) The integrated circuit device according to claim 1, wherein the external connection terminal and the internal electrode are connected via a sealing metal part.
JP20877481A 1981-12-23 1981-12-23 Integrated circuit device Pending JPS58110063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20877481A JPS58110063A (en) 1981-12-23 1981-12-23 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20877481A JPS58110063A (en) 1981-12-23 1981-12-23 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS58110063A true JPS58110063A (en) 1983-06-30

Family

ID=16561867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20877481A Pending JPS58110063A (en) 1981-12-23 1981-12-23 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58110063A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60154646A (en) * 1984-01-25 1985-08-14 Hitachi Micro Comput Eng Ltd Semiconductor device
EP0139364A3 (en) * 1983-09-27 1986-08-13 Trw Inc. Multiple path signal distribution to large scale integration chips
JPS625649A (en) * 1985-07-01 1987-01-12 Nec Ic Microcomput Syst Ltd Package for integrated circuit
US4746966A (en) * 1985-10-21 1988-05-24 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394875A (en) * 1977-01-31 1978-08-19 Nec Corp Package for semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394875A (en) * 1977-01-31 1978-08-19 Nec Corp Package for semiconductor element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139364A3 (en) * 1983-09-27 1986-08-13 Trw Inc. Multiple path signal distribution to large scale integration chips
JPS60154646A (en) * 1984-01-25 1985-08-14 Hitachi Micro Comput Eng Ltd Semiconductor device
JPS625649A (en) * 1985-07-01 1987-01-12 Nec Ic Microcomput Syst Ltd Package for integrated circuit
US4746966A (en) * 1985-10-21 1988-05-24 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits

Similar Documents

Publication Publication Date Title
US5038194A (en) Semiconductor device
JP2003124383A5 (en)
US5455460A (en) Semiconductor device having complimentary bonding pads
US20030183930A1 (en) Semiconductor device and semiconductor module
JP2568748B2 (en) Semiconductor device
CN112885808B (en) Packaging substrate and packaging structure
JPH0870090A (en) Semiconductor integrated circuit
US6574116B2 (en) Inverter capacitor module and inverter
JPS58110063A (en) Integrated circuit device
US5451812A (en) Leadframe for semiconductor devices
CN1316606C (en) Semiconductor device
JPS6020524A (en) Semiconductor integrated circuit device
JPS61287254A (en) Semiconductor device
EP3937225A1 (en) Semiconductor device
EP0527033A2 (en) Semiconductor module
JPS61206269A (en) Semiconductor device
JPS625649A (en) Package for integrated circuit
JPH04267361A (en) Leadless chip carrier
JPH02288292A (en) Semiconductor device
JPS63250850A (en) Semiconductor memory module
JPH02119171A (en) Semiconductor integrated circuit device
JP2919265B2 (en) Semiconductor device
JPS63104434A (en) Semiconductor device
EP0486027A2 (en) Resin sealed semiconductor device
JP2001077230A (en) Lead frame and semiconductor device mounting body using the same