JPS625649A - Package for integrated circuit - Google Patents

Abstract

PURPOSE:To improve the wirings of a signal by providing a plurality of pads at an arbitrary positions of one external connecting terminal, and a plurality of inner terminals connected with one external connecting terminal to wire bond with the pads. CONSTITUTION:Integrated circuit chips 5 placed on a chip placing unit of an integrated circuit package 1 for a sole power source (VCC) with 32 pins are distributed on four sides, only two types of VCC and GND have a plurality of electrodes, inner terminals 2, 2,... of the package 1 corresponding thereto are alternately disposed at the inner terminals of VCC, GND at every two pieces, and the inner terminals are connected with the pads 6 on the chip by bonding wirings 7. Thus, a signal used in an integrated circuit chip can be wire bonded to necessary position.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit package, and in particular to a method for tire bonding between electrodes on an integrated circuit chip (hereinafter referred to as pads) and internal terminals of the integrated circuit package. Regarding placement and wiring.

[Conventional technology]

In conventional integrated circuit packages, the internal terminals for wire bonding, the connected external connection terminals, and the pads on the integrated circuit chip have a one-to-one correspondence, and the arrangement of the external connection terminals is the same as the one on the integrated circuit. It was a row of pads on the chip.

[Problem that the invention seeks to solve]

In the conventional integrated circuit package and integrated circuit chip described above, signals from external connection terminals are connected from the internal terminals of the integrated circuit package to one pad on the integrated circuit chip using bonding wires (thin connection metal wires). The pads are connected to layered wiring within the integrated circuit chip, and the same goes for wiring through which large currents flow, such as power supplies and GND. Therefore, when designing the layout of an integrated circuit chip, wiring for power supply, GND, etc. must be made of metal layer wiring with sufficient capacity in consideration of the flowing current. The mental image is the cross-sectional area that is sufficient to cover the total power generated. Furthermore, since power and GND are supplied to the entire integrated circuit chip, there are many difficulties in routing the wiring.

The design required a lot of effort. In addition, there are also disadvantages in terms of characteristics, such as level fluctuations due to wiring resistance and reduced noise margins at the ends of wiring.

[Means for solving problems]

The integrated circuit package of the present invention has wiring that affects the mask design and performance of the integrated circuit chip, such as power supply and GND.
In order to improve signal wiring, it is now possible to wire bond one external connection terminal to any number of locations within the integrated circuit chip without being restricted by the arrangement of external connection terminals on the integrated circuit package. In order to do so, 1
A plurality of pads are provided at arbitrary locations for one external connection terminal, and a plurality of internal terminals connected to one external connection terminal as described in 11j are provided for this purpose.

〔Example〕

The present invention will now be explained by way of examples.

Fig. 1 is a plan view of an integrated circuit package according to an embodiment of the present invention with an integrated circuit chip mounted thereon, without a camp attached, and Fig. 2 is an enlarged plan view of the integrated circuit chip mounting portion of Fig. 1. be. In these figures, first of all, referring to FIG. 1, an integrated circuit chip 5 mounted on a chip mounting part of an integrated circuit package 1 with 32 pins connected to a single power supply (hereinafter referred to as VCC) has four peripheral It has a plurality of electrodes (pads) distributed in two types, VCC and GND, and the corresponding internal terminals 2, 2, -1 of the package 1 are shown in FIG. Like, VCC
, GND internal terminals 'fr are arranged alternately every second, and these internal terminals and pads 6 on the chip are connected by bonding wires (thin metal wires) 7. These internal terminals 2, 2, -m- are arranged to provide versatility, and it is not necessarily necessary to wire bond all of these internal terminals. Also, in this case, the 16th bin of the external connection terminal is GN
D, and the 32nd bin is VCC, so the GND internal terminal is at the 16th bin, and the VCC internal terminal is at the 3rd bin.
Connect it to pin 2.

〔Effect of the invention〕

As explained above, the present invention provides a method for arranging a plurality of pads and internal terminals at arbitrary locations for a signal to be connected to one external connection terminal. , wire bonding can be done where necessary. Since the signals are connected within the integrated circuit package, they do not need to be connected together within the integrated circuit chip. This is advantageous in building block design because the integrated circuit chip mask design-C allows power supply, GND, etc. to be separated for each functional block.

Furthermore, if this measure is taken for the power supply and GND, it is possible to separate the circuits that generate noise from other circuits from the standpoint of noise countermeasures. Furthermore, fluctuations in voltage levels can be made uniform within the integrated circuit chip and can be suppressed to a lower level than in the past. In addition, even if the integrated circuit chip becomes larger and consumes more power, there is no need to route thick metal layer wiring within the integrated circuit chip, which is necessary to allow all one current to flow, as in the past.

[Brief explanation of drawings]

Figure 1 is a plan view of a package according to an embodiment of the present invention with an integrated circuit chip mounted thereon but without a cap;
The figure is an enlarged plan view of the chip mounting section of FIG. 1. 1°°°゛...Integrated circuit package, 2...Internal terminal, 3...External connection terminal, 5......
Integrated circuit chip, 6... Chip electrode (pad)
, 7...bonding wire. Agent Patent Attorney Uchihara Hajime/Ya. 1. Pa

Claims (1)

[Claims] An integrated circuit comprising a large number of internal terminals arranged around an integrated circuit chip mounting part and connected to pads on an integrated circuit chip mounted on the chip mounting part by thin metal wires, and external terminals connected to the internal terminals. An integrated circuit package characterized in that the chip has at least one internal terminal connected to the same external terminal on each side of the chip.