JPS63104434A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63104434A JPS63104434A JP24971986A JP24971986A JPS63104434A JP S63104434 A JPS63104434 A JP S63104434A JP 24971986 A JP24971986 A JP 24971986A JP 24971986 A JP24971986 A JP 24971986A JP S63104434 A JPS63104434 A JP S63104434A
- Authority
- JP
- Japan
- Prior art keywords
- power
- semiconductor chip
- leads
- lead
- source use
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 229910000679 solder Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
PURPOSE: To expand a lead for signal use in such a way that a lead for power- source use, installed at a package cap, is connected electrically to a semiconductor chip at a protruded electrode.
CONSTITUTION: A semiconductor chip 2 is attached to a package substrate 1. Two or more leads 6 tor power-source use are installed on the surface of a package cap 5 on the side of the semiconductor chip 2; solder bumps (protruding electrodes) 7A are formed at terminals 7 of these leads 6 for power-source use. Then, the package substrate 1 and the package cap 5 are brought close to each other by melting an assembled protruding electrode 8 for power-source use back into contact with the solder bumps 7A so that spacers 4 for sealing use can be attached and sealed hermetically by an adhesive agent or the like. Because it is not required to install the leads 6 for power-source use on the side of the semiconductor chip 2, it is possible to expand the lead for signal use.
COPYRIGHT: (C)1988,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24971986A JPS63104434A (en) | 1986-10-22 | 1986-10-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24971986A JPS63104434A (en) | 1986-10-22 | 1986-10-22 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63104434A true JPS63104434A (en) | 1988-05-09 |
Family
ID=17197179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24971986A Pending JPS63104434A (en) | 1986-10-22 | 1986-10-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63104434A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02192743A (en) * | 1989-01-20 | 1990-07-30 | Fujitsu Ltd | Semiconductor device |
JPH04269842A (en) * | 1991-02-26 | 1992-09-25 | Rohm Co Ltd | Mounting structure of semiconductor device |
-
1986
- 1986-10-22 JP JP24971986A patent/JPS63104434A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02192743A (en) * | 1989-01-20 | 1990-07-30 | Fujitsu Ltd | Semiconductor device |
JPH04269842A (en) * | 1991-02-26 | 1992-09-25 | Rohm Co Ltd | Mounting structure of semiconductor device |
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