US5451812A - Leadframe for semiconductor devices - Google Patents

Leadframe for semiconductor devices Download PDF

Info

Publication number
US5451812A
US5451812A US08/361,010 US36101094A US5451812A US 5451812 A US5451812 A US 5451812A US 36101094 A US36101094 A US 36101094A US 5451812 A US5451812 A US 5451812A
Authority
US
United States
Prior art keywords
leadframe
terminal
chip
lead
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/361,010
Inventor
Yoshihiko Gomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to US08/361,010 priority Critical patent/US5451812A/en
Application granted granted Critical
Publication of US5451812A publication Critical patent/US5451812A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48253—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

  • This invention relates to a leadframe for semiconductor devices.
  • it relates to a leadframe that provides for efficient connections between a semiconductor chip including pads for identical signals, such as power supply signals, and the leads on the leadframe.
  • FIG. 7 shows one-fourth of a unit of a prior art leadframe 37 for a semiconductor device.
  • a semiconductor chip 38 is attached to a die pad 40 on the leadframe.
  • the chip has a plurality of pads 39, some of which are coupled to leads 41 on a one-to-one basis by wires 42. As shown, 10 pads of the chip are coupled to the corresponding 10 leads of the leadframe. There are 5 unused pads on the chip.
  • the number of leads on the leadframe must be the same as or greater than the number of pads on the chip, even if the chip includes a number of pads for coupling to an identical signal, such as a power supply signal of the same voltage level.
  • the number of leads on the leadframe required for coupling to the chip is solely determined by the number of pads on the chip rather than by the types of signals to which a number of the pads may be coupled, such as power supply signals or other signals. This is because each lead on the leadframe can be coupled to at most two pads.
  • the leadframe and the chip have to accommodate one another, causing an increase in the sizes of leadframes and the chips, and an increase in costs as well as complications in the preparation of leadframes.
  • the prior art leadframe described above requires significantly more leads when the chip includes many groups of pads for coupling, respectively, to different types of identical signals, such as high and low voltage pads, and input and output signal pads.
  • the physical size of the manufactured semiconductor devices may be enlarged because chips with a given number of functions may have to be mounted on a much larger leadframe with more leads.
  • the prior art technology goes against the general trend of the industry for light weight and small size. Further, it increases costs and makes the manufactured semiconductor devices significantly less competitive.
  • the present invention is a leadframe that provides for efficient connections between a semiconductor chip including pads for identical signals, such as power supply signal, and the leads on the leadframe.
  • the invention reduces the leads required for attaching to a semiconductor chip on the leadframe to a minimum number.
  • the invention takes into consideration the types of signals to which a number of pads on the chip may be coupled, such as power supply signals of the same levels and the input and output signals of the same types.
  • the leadframe of the present invention is for mounting thereon a semiconductor chip which has a plurality of pads including at least one group of designated pads for communicating an identical signal with external circuits.
  • the leadframe includes a die pad supported on the leadframe for supporting the chip.
  • the leadframe has a plurality of leads for coupling the plurality of pads of the chip to external circuits, with a selected number of the leads supporting the die pad.
  • the leadframe includes at least one terminal which is attached to at least one selected lead and is for coupling to the group of designated pads for communicating the identical signal with the external circuits.
  • the terminal may either receive an identical signal, such as a power supply signal of the same level, from the external circuits, or transmit an identical signal to the external circuits.
  • the terminal and the attached lead may be an integral unit or they may be made of different materials and attached together by conductive adhesive.
  • the leadframe includes a plurality of terminals coupled together by terminal connectors along the die pad, with each terminal for coupling to a corresponding group of designated pads of the chip for communicating a respective identical signal with the external circuits.
  • the terminal connectors may be made of a conductive material or a non-conductive material, or some selected terminal connectors may be made conductive.
  • the terminals can be coupled in various ways for various purposes.
  • a semiconductor chip with a number of functions may be mounted on the leadframe with a given number of leads. Additionally, because the number of leads required for the power supply decreases, wires can be more freely extended from the pads of the chip to the leads. As a result, wires that connect most pads to the assigned leads can be extended substantially in parallel with the leads. Consequently, better electrical connections between the pads and the leads and better support for the wires by the leads can be achieved.
  • FIG. 1 illustrates a portion of a leadframe according to a first embodiment of the invention in which a metal terminal and two leads at its ends are an integral unit;
  • FIG. 2 shows a junction formed by attaching a metal terminal to a lead at its one end using conductive adhesive
  • FIG. 3 illustrates a portion of a leadframe according to a second embodiment of the invention in which a metal terminal and two leads at its ends are attached in the manner shown in FIG. 2;
  • FIG. 4 illustrates a portion of a leadframe according to a third embodiment of the invention in which a metal terminal of a relatively small size is attached to two selected leads;
  • FIG. 5 illustrates a portion of a leadframe according to a fourth embodiment of the invention in which a metal terminal is attached only to a selected lead.
  • FIG. 6A shows a complete unit of a leadframe according to the invention in which four metal terminals are connected together around a die pad by terminal connectors.
  • FIG. 6B shows two complete units of a leadframe according to the invention.
  • FIG. 7 shows a portion of a prior art leadframe.
  • FIG. 1 illustrates one-fourth of a unit of a leadframe 1 for a semiconductor device according to a first embodiment of the invention.
  • a semiconductor chip 2 is attached to a die pad 5 which supports the chip on the leadframe.
  • the chip has eight signal pads 3 coupled to eight corresponding leads 6 on the leadframe via wires 7. Leads 6 are for coupling to external circuits for data communication.
  • the chip also has five power supply pads 4 coupled to a metal terminal 8 positioned between the die pad and the leads on the leadframe via wires 7.
  • the five power supply pads that are coupled to metal terminal 8 are essentially coupled to two leads 51 which are connected to the two ends of metal terminal 8. Leads 51 are for coupling to an external power supply signal of the same level.
  • metal terminal 8 and two leads 51 at its ends are an integral unit, which reduces the manufacturing costs of the leadframe.
  • the metal terminal and the two leads at its ends may be made of different materials and connected together as will described below.
  • FIG. 2 shows a junction formed by connecting a metal terminal 10 to a lead 12 at its one end according to the invention.
  • the metal terminal is attached to the upper surface of the lead by conductive adhesive 11.
  • the lower surface or a side surface of the lead may be used for attaching to the metal terminal.
  • the method of attaching may also be accomplished in other ways, such as resistance welding.
  • FIG. 3 illustrates one-fourth of a unit of a leadframe 13 for a semiconductor device according to a second embodiment of the invention.
  • a semiconductor chip 14 is attached to a die pad 17, which supports the chip on the leadframe.
  • the chip has signal pads 15 coupled to leads 18 which are for coupling to external circuits for data communication.
  • the chip also includes power supply pads 16 coupled to a metal terminal 19 positioned between the die pad and leads 18 via wires 21.
  • the metal terminal is attached to two leads 20 at its two ends. Leads 20 extend farther toward the die pad than leads 18 and are for coupling to an external power supply signal of the same level.
  • This second embodiment is similar to that shown in FIG. 1, except that metal terminal 19 and two leads 20 at its two ends are attached together in the manner shown in FIG. 2.
  • FIG. 4 illustrates one-fourth of a unit of a leadframe 22 according to a third embodiment of the invention.
  • the leadframe includes a die pad 23 for supporting a semiconductor chip thereon and leads 24 for coupling to external circuits for data communication.
  • the leadframe also includes a metal terminal 26 of a relatively small size positioned between the die pad and leads 24.
  • the metal terminal is attached to two selected leads 25 at its two ends. Leads 25 are selected from among leads 24 and are for coupling to an identical signal, such as an external power supply signal of the same level. It is apparent that the metal terminal may be attached to any of leads 24.
  • leads 25 are attached to metal terminal 26 in the manner shown in FIG. 2. However, metal terminal 26 and two leads 25 at its two ends may be an integral unit.
  • FIG. 5 illustrates one-fourth of a unit of a leadframe 27 according to a fourth embodiment of the invention.
  • the leadframe includes a die pad 28 for supporting a semiconductor chip thereon and leads 31 for coupling to external circuits for data communication.
  • the leadframe also includes a metal terminal 29 positioned between the die pad and leads 31.
  • the metal terminal is attached to only one lead, i.e., lead 30.
  • Lead 30 is selected from among leads 31 and is for coupling to an identical signal, such as an external power supply signal of the same level.
  • the metal terminal may be attached to any one of leads 31. Further, the area on the metal terminal on which the lead is attached may be at any desired location.
  • lead 30 is attached to metal terminal 29 in the manner shown in FIG. 2. However, the metal terminal and the connected lead may be an integral unit.
  • FIG. 6A shows a complete unit of a leadframe 32 according to the invention.
  • the leadframe includes a die pad 33 for supporting a semiconductor chip thereon and leads 52 for coupling to external circuits for data communication.
  • the leadframe also includes four metal terminals 34 coupled together along the die pad by terminal connectors, such as plates 36. Each metal terminal is attached to a respective lead 35 at its one end. Each metal terminal and the respective attached lead may be an integral unit. Leads 35 are selected from among leads 52 and are for coupling to respective identical signals, such as external power supply signals of the same levels or other signals of the same types. From FIG. 6, it is apparent that each metal terminal may be attached to any number of leads 52.
  • terminal connectors 36 are made of a conductive material, all metal terminals 34 will be electrically coupled together.
  • terminal connectors 36 are made of a non-conductive material, all metal terminals 34 will be electrically isolated from one another. Further, in other cases only selected terminal connectors may be made of a conductive material. Thus, the metal terminals can be coupled in various ways for various purposes.
  • FIG. 6B shows two complete units of the leadframe according to the invention. Each unit is identical to the one in FIG. 6A.
  • the number of the metal terminals may be more or less than those shown in the drawings.
  • the leads attached to the metal terminals may be more or less than those shown.
  • the metal terminals and the terminal connectors may have different shapes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leadframe for semiconductor devices is disclosed. The leadframe includes a die pad supported on the leadframe. A semiconductor chip is mounted on the die pad. The chip has a plurality of pads including at least one group of designated pads for communicating an identical signal, such as a power supply signal of the same level, with external circuits. A terminal on the leadframe is coupled to the group of designated pads. The terminal is attached to selected one or more leads on the leadframe for communicating the identical signal with the external circuits. The other pads on the chip, such as signal pads, are coupled to the corresponding leads on the leadframe. Thus, the total number of leads on the leadframe is reduced and more leads are available for the signal pads, resulting in efficient connections between the chip pads and the leads. Further, wires can be more freely drawn from the chip pads to the leads, resulting in better connections between the pads and the leads and better support for the wires by the leads.

Description

This is a continuation of copending application Ser. No. 07/954,833 filed Sep. 30, 1992, abandoned.
BACKGROUND OF THE INVENTION
This invention relates to a leadframe for semiconductor devices. In particular, it relates to a leadframe that provides for efficient connections between a semiconductor chip including pads for identical signals, such as power supply signals, and the leads on the leadframe.
FIG. 7 shows one-fourth of a unit of a prior art leadframe 37 for a semiconductor device. A semiconductor chip 38 is attached to a die pad 40 on the leadframe. The chip has a plurality of pads 39, some of which are coupled to leads 41 on a one-to-one basis by wires 42. As shown, 10 pads of the chip are coupled to the corresponding 10 leads of the leadframe. There are 5 unused pads on the chip.
In the prior art described above, to properly mount a semiconductor chip on the leadframe, the number of leads on the leadframe must be the same as or greater than the number of pads on the chip, even if the chip includes a number of pads for coupling to an identical signal, such as a power supply signal of the same voltage level. In other words, the number of leads on the leadframe required for coupling to the chip is solely determined by the number of pads on the chip rather than by the types of signals to which a number of the pads may be coupled, such as power supply signals or other signals. This is because each lead on the leadframe can be coupled to at most two pads. Thus, the leadframe and the chip have to accommodate one another, causing an increase in the sizes of leadframes and the chips, and an increase in costs as well as complications in the preparation of leadframes. Moreover, the prior art leadframe described above requires significantly more leads when the chip includes many groups of pads for coupling, respectively, to different types of identical signals, such as high and low voltage pads, and input and output signal pads. As a result, the physical size of the manufactured semiconductor devices may be enlarged because chips with a given number of functions may have to be mounted on a much larger leadframe with more leads. Thus, the prior art technology goes against the general trend of the industry for light weight and small size. Further, it increases costs and makes the manufactured semiconductor devices significantly less competitive.
SUMMARY OF THE INVENTION
The present invention is a leadframe that provides for efficient connections between a semiconductor chip including pads for identical signals, such as power supply signal, and the leads on the leadframe. The invention reduces the leads required for attaching to a semiconductor chip on the leadframe to a minimum number. The invention takes into consideration the types of signals to which a number of pads on the chip may be coupled, such as power supply signals of the same levels and the input and output signals of the same types.
The leadframe of the present invention is for mounting thereon a semiconductor chip which has a plurality of pads including at least one group of designated pads for communicating an identical signal with external circuits.
According to one aspect of the invention, the leadframe includes a die pad supported on the leadframe for supporting the chip.
According to another aspect of the invention, the leadframe has a plurality of leads for coupling the plurality of pads of the chip to external circuits, with a selected number of the leads supporting the die pad.
According to a further aspect of the invention, the leadframe includes at least one terminal which is attached to at least one selected lead and is for coupling to the group of designated pads for communicating the identical signal with the external circuits. Thus, the terminal may either receive an identical signal, such as a power supply signal of the same level, from the external circuits, or transmit an identical signal to the external circuits. The terminal and the attached lead may be an integral unit or they may be made of different materials and attached together by conductive adhesive.
In an alternative embodiment, the leadframe includes a plurality of terminals coupled together by terminal connectors along the die pad, with each terminal for coupling to a corresponding group of designated pads of the chip for communicating a respective identical signal with the external circuits. The terminal connectors may be made of a conductive material or a non-conductive material, or some selected terminal connectors may be made conductive. Thus, the terminals can be coupled in various ways for various purposes.
Accordingly, a semiconductor chip with a number of functions may be mounted on the leadframe with a given number of leads. Additionally, because the number of leads required for the power supply decreases, wires can be more freely extended from the pads of the chip to the leads. As a result, wires that connect most pads to the assigned leads can be extended substantially in parallel with the leads. Consequently, better electrical connections between the pads and the leads and better support for the wires by the leads can be achieved.
The above and other features and advantages of the invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a portion of a leadframe according to a first embodiment of the invention in which a metal terminal and two leads at its ends are an integral unit;
FIG. 2 shows a junction formed by attaching a metal terminal to a lead at its one end using conductive adhesive;
FIG. 3 illustrates a portion of a leadframe according to a second embodiment of the invention in which a metal terminal and two leads at its ends are attached in the manner shown in FIG. 2;
FIG. 4 illustrates a portion of a leadframe according to a third embodiment of the invention in which a metal terminal of a relatively small size is attached to two selected leads;
FIG. 5 illustrates a portion of a leadframe according to a fourth embodiment of the invention in which a metal terminal is attached only to a selected lead.
FIG. 6A shows a complete unit of a leadframe according to the invention in which four metal terminals are connected together around a die pad by terminal connectors.
FIG. 6B shows two complete units of a leadframe according to the invention.
FIG. 7 shows a portion of a prior art leadframe.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 illustrates one-fourth of a unit of a leadframe 1 for a semiconductor device according to a first embodiment of the invention. A semiconductor chip 2 is attached to a die pad 5 which supports the chip on the leadframe. The chip has eight signal pads 3 coupled to eight corresponding leads 6 on the leadframe via wires 7. Leads 6 are for coupling to external circuits for data communication. The chip also has five power supply pads 4 coupled to a metal terminal 8 positioned between the die pad and the leads on the leadframe via wires 7. The five power supply pads that are coupled to metal terminal 8 are essentially coupled to two leads 51 which are connected to the two ends of metal terminal 8. Leads 51 are for coupling to an external power supply signal of the same level. Thus, the thirteen pads of the chip are coupled to only ten leads, resulting in a reduction of three leads. In this first embodiment, metal terminal 8 and two leads 51 at its ends are an integral unit, which reduces the manufacturing costs of the leadframe. The metal terminal and the two leads at its ends may be made of different materials and connected together as will described below.
FIG. 2 shows a junction formed by connecting a metal terminal 10 to a lead 12 at its one end according to the invention. As shown, the metal terminal is attached to the upper surface of the lead by conductive adhesive 11. Alternatively, the lower surface or a side surface of the lead may be used for attaching to the metal terminal. The method of attaching may also be accomplished in other ways, such as resistance welding.
FIG. 3 illustrates one-fourth of a unit of a leadframe 13 for a semiconductor device according to a second embodiment of the invention. A semiconductor chip 14 is attached to a die pad 17, which supports the chip on the leadframe. The chip has signal pads 15 coupled to leads 18 which are for coupling to external circuits for data communication. The chip also includes power supply pads 16 coupled to a metal terminal 19 positioned between the die pad and leads 18 via wires 21. The metal terminal is attached to two leads 20 at its two ends. Leads 20 extend farther toward the die pad than leads 18 and are for coupling to an external power supply signal of the same level. This second embodiment is similar to that shown in FIG. 1, except that metal terminal 19 and two leads 20 at its two ends are attached together in the manner shown in FIG. 2.
FIG. 4 illustrates one-fourth of a unit of a leadframe 22 according to a third embodiment of the invention. The leadframe includes a die pad 23 for supporting a semiconductor chip thereon and leads 24 for coupling to external circuits for data communication. The leadframe also includes a metal terminal 26 of a relatively small size positioned between the die pad and leads 24. The metal terminal is attached to two selected leads 25 at its two ends. Leads 25 are selected from among leads 24 and are for coupling to an identical signal, such as an external power supply signal of the same level. It is apparent that the metal terminal may be attached to any of leads 24. In FIG. 4, leads 25 are attached to metal terminal 26 in the manner shown in FIG. 2. However, metal terminal 26 and two leads 25 at its two ends may be an integral unit.
FIG. 5 illustrates one-fourth of a unit of a leadframe 27 according to a fourth embodiment of the invention. The leadframe includes a die pad 28 for supporting a semiconductor chip thereon and leads 31 for coupling to external circuits for data communication. The leadframe also includes a metal terminal 29 positioned between the die pad and leads 31. As shown, the metal terminal is attached to only one lead, i.e., lead 30. Lead 30 is selected from among leads 31 and is for coupling to an identical signal, such as an external power supply signal of the same level. As is apparent from FIG. 5, the metal terminal may be attached to any one of leads 31. Further, the area on the metal terminal on which the lead is attached may be at any desired location. In FIG. 5, lead 30 is attached to metal terminal 29 in the manner shown in FIG. 2. However, the metal terminal and the connected lead may be an integral unit.
FIG. 6A shows a complete unit of a leadframe 32 according to the invention. The leadframe includes a die pad 33 for supporting a semiconductor chip thereon and leads 52 for coupling to external circuits for data communication. The leadframe also includes four metal terminals 34 coupled together along the die pad by terminal connectors, such as plates 36. Each metal terminal is attached to a respective lead 35 at its one end. Each metal terminal and the respective attached lead may be an integral unit. Leads 35 are selected from among leads 52 and are for coupling to respective identical signals, such as external power supply signals of the same levels or other signals of the same types. From FIG. 6, it is apparent that each metal terminal may be attached to any number of leads 52. Further, if terminal connectors 36 are made of a conductive material, all metal terminals 34 will be electrically coupled together. On the other hand, if terminal connectors 36 are made of a non-conductive material, all metal terminals 34 will be electrically isolated from one another. Further, in other cases only selected terminal connectors may be made of a conductive material. Thus, the metal terminals can be coupled in various ways for various purposes.
FIG. 6B shows two complete units of the leadframe according to the invention. Each unit is identical to the one in FIG. 6A.
While the invention has been described in conjunction with several specific embodiments of the invention, it is evident to those skilled in the art that many further alternatives, modifications and variations will be apparent in light of the foregoing description. For example, the number of the metal terminals may be more or less than those shown in the drawings. Further, the leads attached to the metal terminals may be more or less than those shown. Additionally, the metal terminals and the terminal connectors may have different shapes. Thus, the invention described herein is intended to embrace all such alternatives, modifications, applications and variations as may fall within the spirit and scope of the appended claims.

Claims (14)

What is claimed is:
1. A leadframe for mounting thereon a semiconductor chip which has a plurality of bonding pad means positioned along at least one side of the chip and including a plurality of groups of designated bonding pad means, with each group of designated bonding pad means for communicating an identical signal with external circuits, the leadframe comprising:
a frame having support means and a plurality of lead means for coupling the plurality of bonding pad means of the chip to the external circuits;
mount means, positioned within said frame and attached to said support means, for supporting the chip; and
a plurality of terminal means, with each terminal means, positioned between one side of said mount means and one end of at least some of said plurality of lead means and attached to at least one selected lead means, for coupling to an associated group of designated bonding pad means of the chip for communicating a respective identical signal with the external circuits through said at least one selected lead means; and
a plurality of terminal connectors coupling said plurality of terminal means together around said mount means;
wherein said plurality of terminal means and said plurality of lead means are comprised of separate layers.
2. The leadframe of claim 1 wherein said support means includes a plurality of lead means, each of which is attached to one end of each of two adjacent terminal means as said selected lead means.
3. The leadframe of claim 1 wherein a selected number of said terminal means are for coupling to the associated groups of designated bonding pad means for receiving the respective identical signals.
4. The leadframe of claim 1 wherein each terminal means is positioned such that there are a first predetermined space between said terminal means and said side of said mount means and a second predetermined space between said terminal means and said end of said at least some lead means.
5. The leadframe of claim 4 wherein each terminal means has a substantially rectangular shape and is substantially parallel to said side of said mount means and said end of said at least some lead means.
6. The leadframe of claim 1 wherein a selected number of said terminal connectors are made of conductive materials for electrically coupling selected terminal means together.
7. The leadframe of claim 1 wherein all of said terminal connectors are made of non-conductive materials for electrically isolating said terminal means from one another.
8. A leadframe for mounting thereon a semiconductor chip which has a plurality of bonding pad means positioned along four sides of the chip and including a plurality of groups of designated bonding pad means, with each group of designated bonding pad means for communicating an identical signal with external circuits, the leadframe comprising:
a frame having support means and a plurality of lead means for coupling the plurality of bonding pad means of the chip to the external circuits;
mount means, positioned within said frame and attached to said support means, for supporting the chip, said mount means having four sides; and
four terminal means, with each terminal means, positioned between one side of said mount means and one end of at least some of said plurality of lead means and attached to at least one selected lead means, for coupling to an associated group of designated bonding pad means of the chip for communicating a respective identical signal with the external circuits through said at least one selected lead means; and
four terminal connectors each coupling two adjacent terminal means together at a corner of said mount means;
wherein said four terminal means and said four lead means are comprised of separate layers.
9. The leadframe of claim 8 wherein said support means includes a plurality of lead means, each of which is attached to one end of each of two adjacent terminal means as said selected lead means.
10. The leadframe of claim 8 wherein a selected number of said terminal means are for coupling to the associated groups of designated bonding pad means for receiving the respective identical signals.
11. The leadframe of claim 8 wherein each terminal means is positioned such that there are a first predetermined space between said terminal means and said side of said mount means and a second predetermined space between said terminal means and said end of said at least some lead means.
12. The leadframe of claim 11 wherein each terminal means has a substantially rectangular shape and is substantially parallel to said side of said mount means and said end of said at least some lead means.
13. The leadframe of claim 8 wherein a selected number of said terminal connectors are made of conductive materials for electrically coupling selected terminal means together.
14. The leadframe of claim 8 wherein all of said terminal connectors are made of non-conductive materials for electrically isolating said terminal means from one another.
US08/361,010 1991-10-02 1994-12-21 Leadframe for semiconductor devices Expired - Lifetime US5451812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/361,010 US5451812A (en) 1991-10-02 1994-12-21 Leadframe for semiconductor devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP3255430A JP2917607B2 (en) 1991-10-02 1991-10-02 Lead frame for semiconductor device
JP3-255430 1991-10-02
US95483392A 1992-09-30 1992-09-30
US08/361,010 US5451812A (en) 1991-10-02 1994-12-21 Leadframe for semiconductor devices

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US95483392A Continuation 1991-10-02 1992-09-30

Publications (1)

Publication Number Publication Date
US5451812A true US5451812A (en) 1995-09-19

Family

ID=17278662

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/361,010 Expired - Lifetime US5451812A (en) 1991-10-02 1994-12-21 Leadframe for semiconductor devices

Country Status (2)

Country Link
US (1) US5451812A (en)
JP (1) JP2917607B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2318683A (en) * 1996-09-05 1998-04-29 Int Rectifier Corp Surface mount semiconductor package
US5859801A (en) * 1997-03-28 1999-01-12 Siemens Aktiengesellschaft Flexible fuse placement in redundant semiconductor memory
US5902119A (en) * 1997-03-12 1999-05-11 Mitsubishi Denki Kabushiki Kaisha Leadframe tip arrangement designing method
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
US6159766A (en) * 1997-08-20 2000-12-12 Mitsubishi Denki Kabushiki Kaisha Designing method of leadframe tip arrangement
US6258629B1 (en) 1999-08-09 2001-07-10 Amkor Technology, Inc. Electronic device package and leadframe and method for making the package
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
US7166905B1 (en) 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
US9997438B2 (en) 2015-04-24 2018-06-12 Stmicroelectronics S.R.L. Leads frames with crossing leads

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005026520A (en) * 2003-07-03 2005-01-27 Matsushita Electric Ind Co Ltd Lead frame and semiconductor device using it

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3698082A (en) * 1966-04-25 1972-10-17 Texas Instruments Inc Complex circuit array method
US4027326A (en) * 1974-04-20 1977-05-31 W. C. Heraeus Gmbh Metallic support carrier for semiconductor elements
US4092664A (en) * 1976-02-17 1978-05-30 Hughes Aircraft Company Carrier for mounting a semiconductor chip
US4403240A (en) * 1979-10-26 1983-09-06 Hitachi, Ltd. Integrated circuit with at least three ground pads
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS61148854A (en) * 1984-12-24 1986-07-07 Hitachi Ltd Lead frame
JPS6464347A (en) * 1987-09-04 1989-03-10 Nec Corp Semiconductor integrated circuit
US4979016A (en) * 1988-05-16 1990-12-18 Dallas Semiconductor Corporation Split lead package
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5115298A (en) * 1990-01-26 1992-05-19 Texas Instruments Incorporated Packaged integrated circuit with encapsulated electronic devices
US5168368A (en) * 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
US5196725A (en) * 1990-06-11 1993-03-23 Hitachi Cable Limited High pin count and multi-layer wiring lead frame
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
JPH0666351A (en) * 1992-08-20 1994-03-08 Toyota Motor Corp Backlash shim selecting method for differential device

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3698082A (en) * 1966-04-25 1972-10-17 Texas Instruments Inc Complex circuit array method
US4027326A (en) * 1974-04-20 1977-05-31 W. C. Heraeus Gmbh Metallic support carrier for semiconductor elements
US4092664A (en) * 1976-02-17 1978-05-30 Hughes Aircraft Company Carrier for mounting a semiconductor chip
US4403240A (en) * 1979-10-26 1983-09-06 Hitachi, Ltd. Integrated circuit with at least three ground pads
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS61148854A (en) * 1984-12-24 1986-07-07 Hitachi Ltd Lead frame
JPS6464347A (en) * 1987-09-04 1989-03-10 Nec Corp Semiconductor integrated circuit
US4979016A (en) * 1988-05-16 1990-12-18 Dallas Semiconductor Corporation Split lead package
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5115298A (en) * 1990-01-26 1992-05-19 Texas Instruments Incorporated Packaged integrated circuit with encapsulated electronic devices
US5196725A (en) * 1990-06-11 1993-03-23 Hitachi Cable Limited High pin count and multi-layer wiring lead frame
US5168368A (en) * 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
JPH0666351A (en) * 1992-08-20 1994-03-08 Toyota Motor Corp Backlash shim selecting method for differential device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2318683B (en) * 1996-09-05 2001-08-22 Int Rectifier Corp Improved Surface Mount High Power Semiconductor Package and Method of Manufacture
US6204554B1 (en) * 1996-09-05 2001-03-20 International Rectifier Corporation Surface mount semiconductor package
GB2318683A (en) * 1996-09-05 1998-04-29 Int Rectifier Corp Surface mount semiconductor package
US5939775A (en) * 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
US5902119A (en) * 1997-03-12 1999-05-11 Mitsubishi Denki Kabushiki Kaisha Leadframe tip arrangement designing method
US5859801A (en) * 1997-03-28 1999-01-12 Siemens Aktiengesellschaft Flexible fuse placement in redundant semiconductor memory
US6159766A (en) * 1997-08-20 2000-12-12 Mitsubishi Denki Kabushiki Kaisha Designing method of leadframe tip arrangement
US6258629B1 (en) 1999-08-09 2001-07-10 Amkor Technology, Inc. Electronic device package and leadframe and method for making the package
US6339252B1 (en) * 1999-08-09 2002-01-15 Amkor Technology, Inc. Electronic device package and leadframe
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
US7166905B1 (en) 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
US9997438B2 (en) 2015-04-24 2018-06-12 Stmicroelectronics S.R.L. Leads frames with crossing leads
US10074596B2 (en) 2015-04-24 2018-09-11 Stmicroelectronics S.R.L. Method of fabricating a lead frame by additive process

Also Published As

Publication number Publication date
JP2917607B2 (en) 1999-07-12
JPH0595069A (en) 1993-04-16

Similar Documents

Publication Publication Date Title
US5473514A (en) Semiconductor device having an interconnecting circuit board
KR101062260B1 (en) Integrated circuit assembly
US5841191A (en) Ball grid array package employing raised metal contact rings
US5648679A (en) Tape ball lead integrated circuit package
US7112878B2 (en) Die stacking scheme
US6583503B2 (en) Semiconductor package with stacked substrates and multiple semiconductor dice
US6291881B1 (en) Dual silicon chip package
US5789816A (en) Multiple-chip integrated circuit package including a dummy chip
US5227995A (en) High density semiconductor memory module using split finger lead frame
EP0329317A2 (en) Semiconductor device having an insulating sheet
EP1264347A2 (en) Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
US5451812A (en) Leadframe for semiconductor devices
US5641978A (en) Input/output buffer layout having overlapping buffers for reducing die area of pad-limited integrated circuit
US5569955A (en) High density integrated circuit assembly combining leadframe leads with conductive traces
EP0590915A1 (en) Chip on board assembly
EP0447922B1 (en) Resin seal type semiconductor device
US5801927A (en) Ceramic package used for semiconductor chips different in layout of bonding pads
US6376903B1 (en) Semiconductor chip package with multilevel leads
JPS6020524A (en) Semiconductor integrated circuit device
JPH01144664A (en) Integrated circuit device for semiconductor memory
JPH03166756A (en) Lead frame for semiconductor integrated circuit
US6495910B1 (en) Package structure for accommodating thicker semiconductor unit
US6281580B1 (en) LSI package and inner lead wiring method for same
JPS629654A (en) Mounting package for ic device
KR20000019885A (en) Semiconductor device with plural bonding pad set

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12