JP2001077230A - Lead frame and semiconductor device mounting body using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise without increasing the number of external terminals. SOLUTION: A land 200 for a power source is formed on the side of a die pad 101 for supporting a chip 100. The land 200, which is formed of a band- shaped pattern of a conductor layer, having a configuration for surrounding the periphery of a region to which the chip 100 is secured. Using the land 200, a plurality of GND pads 202 are connected to the land 200 with metallic wires 204 based on a wire bonding method, and the inner lead portion of one of leads 206 which is coupled to an external terminal for a GND voltage is connected to the land 200 by a metallic wire 208, based on the wire bonding method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor device package using the same.

[0002]

2. Description of the Related Art FIG. 1 schematically shows a conventional semiconductor device package. The lead frame includes a die pad 101 that supports a semiconductor chip (hereinafter, simply referred to as a chip) 100 and leads 102 that are arranged around the chip 100 supported by the die pad 101. The chip 100 is fixed and supported on the die pad 101, and the lead 102 and the pad 103 of the chip 100 are connected by a metal wire 104 such as gold by a wire bonding method. 105
Is a sealing resin, except for a part of the lead 102 which is led to the outside, and the chip 100, the lead frames 101, 1
02 and the wire 104 are sealed and sealed off from the outside.

Conventionally, as a countermeasure against noise in a semiconductor device, increasing the number of power supply terminals has been adopted as a simple and reliable method. For example, in a semiconductor device in which simultaneous switching of a data bus or the like is performed, a signal terminal which changes simultaneously is used. The method of adding a power supply terminal in between has become mainstream.

However, as is apparent from the structure of the lead frame shown in FIG. 1, the pads 103 correspond to the external terminals of this package on a one-to-one basis. Not only does the arrangement change, but also the number of external terminals increases, and even the package is forced to change due to the limitation of the number.

As a general conventional technique, there is a method called double bonding as a method of supplying power to a plurality of power supply pads without increasing the number of external terminals. This has a drawback that power can not be supplied to a free position only by arranging a plurality of power supply pads to be supplied. Several proposals have been made to solve such a problem. One of the methods is to form a decoupling capacitor on a lead frame and to embed the decoupling capacitor inside a mounting body to absorb electric noise (see Japanese Patent Application Laid-Open No. 6-216309).

Another method is to divide a die pad and supply a power supply voltage Vcc and a ground voltage (GND) Vss to each of the divided regions in order to reduce noise by reducing the inductance component of the lead frame. See JP-A-8-70059).

Still another method is to provide a bonding pad for supplying power to a circuit in which noise is hardly emitted, in order to reduce power supply noise caused by noise generated from a noise source circuit and improve noise immunity. This method is to reduce the noise by increasing the inductance by increasing the bonding distance between the inner lead bonded to the inner lead and the inner lead bonded to the bonding pad that supplies power to a circuit where noise is likely to occur ( See JP-A-10-256457).

Still another method is to dispose a dummy metal piece for noise reduction between signal leads in order to alleviate restrictions on the arrangement of leads and reduce malfunctions due to noise (Japanese Patent Laid-Open No. Hei 11 (1999)). -40721).

[0009]

These proposals are effective methods for achieving the object of reducing noise, but all have the major drawback that the position of the power supply terminal is fixed for each lead frame. is there. This is disadvantageous in terms of versatility of the lead frame.
In addition, if a conventional semiconductor device package using a general-purpose lead frame has to be redesigned to improve noise resistance, it is necessary to increase the number of terminals in order to increase the number of power supplies, This not only requires changing the arrangement of the terminals, but also changing the package itself.

In a terminal group in which signals change simultaneously with the increase in the speed of the system, the occurrence of power supply noise due to so-called simultaneous switching of a data bus or the like is taken up as a major problem. To solve this problem, increasing the number of power supply terminals has been adopted as a simple and reliable method. However, with the complexity of today's systems, the bit width of data buses and the like tends to increase. In such a case, there is a demand to reduce the size of the package from the viewpoint of miniaturization of the system, and it is not preferable to increase the number of terminals. For products such as general-purpose products, for which the package and its terminal arrangement have already been determined, it may not be possible to rearrange the terminals, or even increase the number of power terminals for noise suppression. Many. SUMMARY OF THE INVENTION It is an object of the present invention to address the above problem without increasing the number of external terminals by using a lead frame having a new structure.

[0011]

A lead frame according to the present invention is a lead frame provided with a die pad for supporting a chip, the die pad being provided on a peripheral portion of a region for supporting the chip on a side supporting the chip. A low-resistance land connected to the power supply lead and the power supply pad of the chip is provided. Here, the power supply is used to include not only the power supply on the high voltage side such as Vcc, but also the power supply on the low voltage side such as ground (hereinafter referred to as GND).

Further, a semiconductor device package of the present invention is one in which a chip is sealed using the above-described lead frame of the present invention. That is, in the semiconductor device package of the present invention, the leads arranged around the chip to be mounted and the low-resistance land are provided on the side supporting the chip to be mounted on the periphery of the region supporting the chip. Frame provided with a die pad, a chip fixedly supported on the die pad of the lead frame, connection between the pad of the chip and a corresponding lead of the lead frame, and a land and a predetermined power supply lead and power supply A metal wire for connection with the pad for use, and a sealing member for sealing each of the leads except for a portion led to the outside by blocking them from the outside air.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS When only one type of GND voltage is provided, the entire die pad can be used as a land. However, one example of a preferred land is
It is composed of a conductor layer formed on the die pad by patterning via an insulating layer. In this case, two lands for a high-voltage power supply and a low-voltage power supply formed separately from each other may be provided, or more lands may be formed.

[0014]

FIG. 2 shows a lead frame according to an embodiment. The lead frame has a die pad 101 and leads 102. The chip 100 is fixed and supported on the die pad 101. A base end portion (inner lead portion) of the lead 102 is arranged around the chip 100, and a tip end portion (outer lead portion) of the lead 102 projects outside the sealing resin 105 after sealing to form a terminal for external connection. Become.

On the die pad 101, on the side on which the chip 100 is supported, a power supply land 200 is formed by a strip-shaped pattern of a conductive layer so as to surround the periphery of the region where the chip 100 is fixed. The base material of the die pad 101 is the same as the lead 102 and is formed simultaneously with the lead 102. The surface of the base material of the die pad 101 is covered with an insulating layer.
0 is fixed. The land 200 is formed by patterning a conductive layer such as tin formed by plating on the insulating layer on the die pad 101 by etching or the like.

The land 200 is connected to the power supply voltage (V
cc) and two lands are desirably formed for each of the low voltage side (GND voltage side).
In this embodiment, only one is provided for the purpose of reinforcing either the Vcc side or the GND side. Chip 100
When the number of power supplies used is three or more, lands of the number of power supplies can be provided according to each power supply.

FIG. 3 schematically shows a state in which a chip is mounted using this lead frame. Now, it is assumed that the land 200 is used for a GND power supply. A chip 100 is fixed and supported on the die pad 101, and the signal pad 103 and the lead 1 of the chip 100 are provided.
02 are connected by a metal wire 104. Of the pads, a GND power supply pad 202 is connected to a land 200 by a metal wire 204, and
A metal wiring 208 connects between 0 and an inner lead portion of a lead 206 serving as an external terminal for GND. In the figure, only one GND pad 202 is shown.
Are connected to the lands 200 by the respective metal wires 204. The metal wires 104, 204, and 208 are all connected by a wire bonding method using a gold wire. FIG. 3 shows only a connection with some pads and some leads, but after all necessary connections between pads and leads are made, the package is sealed with a sealing resin 105.

FIG. 4 shows how noise is generated by simultaneous switching. (A) shows one of the output buffer circuits, and a terminal 34 serving as a pad is provided on the output side of an output buffer circuit of a CMOS inverter including a P-channel MOS transistor 30 and an N-channel MOS transistor 32. I have. The output buffer has a parasitic inductance 36, and the output line has a parasitic capacitance 38. For n data buses, n such output buffer circuits are provided.

As shown in (B), the output of the bus is instantaneously changed from the "H" level output to the "L" level output, and the inductance parasitic on the power supply line (here, the GND line) is changed. 36, a back electromotive force is generated, and noise is added to the power supply line. It is easy to guess that reducing this inductance 36 reduces noise, but it is well known that increasing the number of power supplies near the current source, here the bus output, is most effective. It is known as a fact that at the design stage, buses are sandwiched between power supply terminals, or buses are divided into several units and sandwiched between power supply terminals, etc. I am taking it.

FIG. 5 shows an example of such a chip 1 having an arrangement of signal pads 103 as shown in FIG.
As shown in FIG. 2B, a predetermined number of signal pads 103 are sandwiched between GND pads 202 as shown in FIG. However, considering a lead frame corresponding to this, the signal terminals and the GND terminals are sandwiched, which is different from the terminal arrangement before the measures. This also means an increase in the number of terminals, which leads to a change in the package. If the terminal arrangement and the number of terminals cannot be changed, this measure cannot be taken.Therefore, it is necessary to redesign in the direction to lower the chip performance, such as reducing the noise by lowering the switching speed. Was gone.

FIG. 6 shows an example in which the present invention is applied so as not to increase the number of external terminals even when the number of power supply pads increases. Using the land 200, multiple GND
A pad 202 and a land 200 are connected by a metal wire 204 by a wire bonding method, and an inner lead portion of one lead 206 connected to an external terminal for GND voltage is connected to the land 200 by a metal wiring 208 by a wire bonding method. I do.

As the above-mentioned countermeasure, there has been the most basic and reliable method of sandwiching the bus between the power supply terminals. However, in this case, the current is supplied to the power supply pads arranged as necessary on the chip without increasing the number of external terminals. Can be supplied. That is, first, the lands are charged to a power level (GND level in the example of FIG. 6) with a low impedance by connecting the lead of the power terminal and the land with a metal wire. Further, only the power supply pad (GND pad in this case) is wired with a metal line to the land on the die pad. This means that all the power pads placed within the permissible range on the area within the chip can be connected without increasing external terminals. This makes it possible to provide a semiconductor device that suppresses the occurrence of simultaneous switching noise of the chip and satisfies the desired number of terminals and terminal arrangement. On the other hand, it is also possible to provide a semiconductor device which can be realized only by securing the minimum number of external power supply terminals (one or more) that can be arranged at an arbitrary position, which enables a reduction in the size of a package and the present semiconductor device. Can be configured to be small.

[0023]

By using the lead frame of the present invention, it is possible to reduce the number of power supply terminals required conventionally, and to further reduce the size of the package. When redesigning to improve the noise resistance of the chip,
By using the present lead frame, it is possible to easily improve the noise resistance without changing the terminal arrangement and without reducing the performance of the chip. By using a semiconductor device mounted using the lead frame, sufficient noise resistance can be obtained by the semiconductor device itself, eliminating the need to take noise countermeasures on the conventional board, and reducing costs. Also leads.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a conventional semiconductor device package.

FIG. 2 is a schematic plan view showing a lead frame of one embodiment.

FIG. 3 is a schematic plan view showing a semiconductor device package according to one embodiment.

4A and 4B are diagrams illustrating how noise is generated by simultaneous switching. FIG. 4A is a circuit diagram illustrating one of output buffer circuits, and FIG. 4B is a waveform diagram.

FIG. 5 is a diagram for explaining an example of noise resistance measures;
(A) is a plan view showing an original signal pad arrangement, (B)
FIG. 3 is a plan view showing a state in which a predetermined number of the signal pads are sandwiched by GND pads.

FIG. 6 is a schematic plan view showing a semiconductor device mounted body to which the present invention is applied to the chip shown in FIG. 5B in which power supply pads are increased.

[Explanation of symbols]

 101 die pad 100 chip 102 lead 103 signal pad 104, 204, 208 metal wire 200 land 202 GND pad 206 lead to be an external terminal for GND

Claims (4)

[Claims] 1. A lead frame provided with a lead arranged around a semiconductor chip to be mounted and connected to a pad of the semiconductor chip by a metal wire, and a die pad for supporting the semiconductor chip to be mounted, wherein the die pad includes a semiconductor. A lead frame, comprising: a power supply lead and a low-resistance land connected to a power supply pad of the semiconductor chip in a peripheral portion of a region supporting the semiconductor chip on a side supporting the chip. 2. The lead frame according to claim 1, wherein said lands are made of a conductor layer formed on a die pad by patterning via an insulating layer. 3. The lead frame according to claim 2, wherein the lands include two high voltage power supplies and two low voltage power supplies formed separately from each other. 4. A die pad provided with leads arranged around a semiconductor chip to be mounted and low-resistance lands on a side supporting the semiconductor chip to be mounted on a periphery of a region supporting the semiconductor chip. A semiconductor chip fixedly supported on a die pad of the lead frame, a connection between the pad of the semiconductor chip and a corresponding lead of the lead frame, and the land and a predetermined power supply lead. A semiconductor device mounting, comprising: a metal wire for connection to a power supply pad; and a sealing member for sealing off each of the members except for a portion of the lead that is led to the outside, from outside air. body.