JP2003124333A - Semiconductor ic chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed operable semiconductor IC chip in which a parasitic capacitance is reduced between a pad/chip core connection line and a power supply line. SOLUTION: The semiconductor IC chip (40) comprises a chip core (12) having a semiconductor integrated circuit, a pad (34) arranged in proximity to the outside of the chip core as an electrical connection terminal between the chip core and the outside, and a power supply line (16) and a ground line (18) arranged on the outside of the pad in order to supply power to the chip core wherein a pad/chip core connection line (35) does not overlap the power supply line and the ground line.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor IC chip, and more particularly to a semiconductor IC chip having pads arranged inside a power supply line.

2. Description of the Related Art FIG. 1 shows an example of a conventional semiconductor IC chip. The semiconductor IC chip 10 has a chip core portion 12 in the center thereof, and transistors forming a semiconductor circuit are integrated therein. A power supply line 16 is provided along the outer periphery of the chip core portion 12, and power is supplied to the chip core portion from there. A ground line 18 is provided outside the power supply line 16, and ground power is supplied from there to the chip core portion. A plurality of pads 14 are arranged outside the ground line 18. The chip core portion 12 and the pad 14 are electrically connected by a pad-chip core portion connecting line 15 (see FIG. 2). The pad and the external lead (not shown) are electrically connected by wire bonding before sealing. An electric signal from the outside enters the gate of the transistor inside the chip core portion via the pad. The input gate breakdown voltage of the internal transistor is several volts, which is very weak.
High voltage (eg, 1000 volts) due to electrostatic charge stored on the leads, for example by touching the external leads, may be applied to the gate of the internal transistor, which may destroy the transistor. In order to release an abnormal steep voltage such as a surge of static electricity applied to the pad to the power supply line or the ground line, the electrostatic protection circuit 2 is usually used.
0 is set. The electrostatic protection circuit 20 can release charges on the pad to the power supply line or the ground by using, for example, a diode. In this way, the transistor input gate in the chip core section can be protected from the static electricity generated on the pad. Power is supplied to the protection circuit from a power line and a ground line. The conventional problems will be described with reference to FIG. The connection line 15 between the pad and the chip core portion must be wide in order to pass a large current. Since this connection line 15 crosses over the power supply line and the ground line,
A parasitic capacitance 30 is generated between them, which is not preferable in operation. In particular, when the connection line 15 is widened due to a large current, the parasitic capacitance becomes large, which is not particularly preferable for high-speed operation. Therefore, an object of the present invention is to provide a semiconductor IC chip which has a small parasitic capacitance between a pad / chip core connection line and a power supply line and which can operate at high speed.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a semiconductor IC chip 40 which is an embodiment of the present invention. At the center of the semiconductor IC chip 40, there is a chip core portion 12, in which transistors that form a semiconductor circuit are integrated. The pads 34 are arranged outside the chip core portion 12. The power supply line 16 is provided outside the pad 34, and power is supplied to the chip core portion from the power supply line 16 (not shown). A ground line 18 is provided outside the power supply line 16, and ground power is supplied from the ground line 18 to the chip core portion (not shown). Chip core portion 12 and pad 34
Are electrically connected to each other by a pad / chip core portion connection line 35. The pad and the external lead (not shown) are electrically connected by wire bonding before sealing. The pad / chip core section connection line 35 is widened for a large current, but since it does not intersect with the power supply line or the ground line, there is no problem due to the parasitic capacitance between them. Also, a short wiring is sufficient between the pad and the chip core portion. The electrostatic protection circuit 20 can be provided in the vicinity of the power supply line in order to release an abnormal steep voltage such as a surge of static electricity applied to the pad to the power supply line or the ground line. The electrostatic protection circuit 20 releases the charge on the pad to the power supply line or the ground by using, for example, a diode. Power is supplied to the protection circuit 20 from a power supply line and a ground line. The line 36 that connects the pad and the electrostatic protection circuit does not need to carry a large current, so that it can be made thin and the cross-sectional area 60 between the pad and the power supply line can be made small, resulting in a small parasitic capacitance. It is possible to It is possible to place all of the multiple pads inside the power supply line, or place only the pads that require high speed or large current inside the power supply line,
It is also possible to arrange other pads outside the power supply line.

Since the embodiment of the present invention is constructed as described above, the problem of the parasitic capacitance between the pad and the power supply line is solved and high speed operation is possible. The pad can be arranged at various positions according to the application of the pad by applying it to an analog-digital mixed IC.

[Brief description of drawings]

FIG. 1 shows a part of a conventional semiconductor IC chip.

FIG. 2 is a partially enlarged detailed view of the semiconductor IC chip of FIG.

FIG. 3 is a partially enlarged detailed view of a semiconductor IC chip according to an embodiment of the present invention.

[Explanation of symbols]

40 Semiconductor IC chip 12 Chip core part 34 pads 16 power lines 18 Grand Line 35 Connection line between pad and chip core 20 Electrostatic protection circuit 36 Pad-electrostatic protection circuit connection line

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F038 BE07 BH04 BH13 CA09 CA10                       CD02 DF12 EZ20                 5F064 CC01 CC21 DD14 DD42 EE09                       EE17 EE52 EE53

Claims (2)

[Claims] 1. A semiconductor IC chip (40) comprising: a chip core portion (12) having a semiconductor integrated circuit; arranged near the outside of the chip core portion and electrically connecting the chip core portion to the outside. A pad (34) as a terminal for the power supply; and a power supply line (16) and a ground line (1) arranged outside the pad and supplying power to the chip core portion
8); and the semiconductor chip that is characterized in that the pad / chip core part connection line (35) does not overlap the power supply line and the ground line. 2. The semiconductor IC chip according to claim 1, further comprising: an electrostatic protection circuit (20) arranged in the vicinity of a power supply line and a ground line; and a pad.
A semiconductor IC chip comprising an electrostatic protection circuit connection line (36); and reducing the area where the pad-electrostatic protection circuit connection line (36) and the power supply line and the ground line overlap.