JPH0629395A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0629395A
JPH0629395A JP4061601A JP6160192A JPH0629395A JP H0629395 A JPH0629395 A JP H0629395A JP 4061601 A JP4061601 A JP 4061601A JP 6160192 A JP6160192 A JP 6160192A JP H0629395 A JPH0629395 A JP H0629395A
Authority
JP
Japan
Prior art keywords
power supply
power
wirings
circuit block
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4061601A
Other languages
Japanese (ja)
Inventor
Yuji Koizumi
雄二 小泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4061601A priority Critical patent/JPH0629395A/en
Publication of JPH0629395A publication Critical patent/JPH0629395A/en
Withdrawn legal-status Critical Current

Links

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a chip size, by providing an additional power connecting wiring as well as a power connecting wiring between first and second power wirings. CONSTITUTION:First power wirings 1 and 2 are provided around an inner circuit block 9 in a semiconductor chip. On the other hand, second power wirings 3 and 4 are provided on an outer circuit block 10 formed at a peripheral part of the first power wirings 1 and 2 so that the second power wirings 3 and 4 are formed around the first power wirings 1 and 2. Power connecting wirings 5 and 6 for supplying power to the first and second power wirings (1, 2) and (3, 4) is connected to a power-supply pad 11 formed at a peripheral part of the outer circuit block 10. Moreover, additional power connecting wirings 7 and 8 in a region other than the power connecting wirings 5 and 6 are provided to connect the first power wirings (1, 2) with the second power wirings (3, 4). Consequently, the wiring width of the first power wirings 1 and 2 for supplying power to the inner circuit block 9 with high power consumption can be reduced, and the chip size can be made small.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路装置に関
し、特に半導体チップ上の電源配線に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to power supply wiring on a semiconductor chip.

【0002】[0002]

【従来の技術】従来の半導体集積回路装置は、図2に示
すように、半導体チップ上に設けた内部回路ブロック9
の周囲に設けた第1の電源配線1,2(但し電源配線1
はVDD用,電源配線2はGND用)と、第1の電源配線
1,2の外周に設けた外部回路ブロック10と、外部回
路プロック10の上に設けて第1の電源配線1,2の外
周に設けた第2の電源配線3,4(但し電源配線3はG
ND用,電源配線4はVDD用)と、外部回路ブロック1
0の外周に設けたVDD用電源用パッド11及びGND用
電源パッド12に接続して第1の電源配線1,2及び第
2の電源配線3,4のVDD用とGND用のそれぞれを接
続する電源接続配線5,6とを有して構成される。ここ
で、電源接続配線5,6はコンタクトホール14を介し
て第1及び第2の電源配線1,2,3,4と接続され、
外部回路ブロック10の外周には電源用バッド11,1
2以外に外部回路プロック10と接続される信号用のパ
ッド15及び空きパッド16が配置される。
2. Description of the Related Art A conventional semiconductor integrated circuit device, as shown in FIG. 2, has an internal circuit block 9 provided on a semiconductor chip.
The first power supply wirings 1 and 2 provided around the
Is for V DD , the power supply wiring 2 is for GND), the external circuit block 10 is provided on the outer periphery of the first power supply wirings 1, 2, and the first power supply wirings 1, 2 provided on the external circuit block 10. The second power supply wirings 3 and 4 provided on the outer periphery of the
ND, power supply wiring 4 is for V DD ) and external circuit block 1
The power supply pad 11 for V DD and the power supply pad 12 for GND provided on the outer periphery of 0 are connected to the first power supply wirings 1 and 2 and the second power supply wirings 3 and 4 for V DD and GND, respectively. Power supply connection wirings 5 and 6 for connection are provided. Here, the power supply connection wirings 5, 6 are connected to the first and second power supply wirings 1, 2, 3, 4 through the contact holes 14,
A power supply pad 11, 1 is provided on the outer periphery of the external circuit block 10.
In addition to 2, pad 15 for signals and empty pad 16 connected to external circuit block 10 are arranged.

【0003】なお、第1の電源配線1,2と第2の電源
配線3,4とを電気的に分離することにより、内部回路
ブロック9と外部回路ブロック10とをそれぞれ異なる
電源で駆動することもできる。
By electrically separating the first power supply wirings 1 and 2 from the second power supply wirings 3 and 4, the internal circuit block 9 and the external circuit block 10 are driven by different power supplies. You can also

【0004】[0004]

【発明が解決しようとする課題】この従来の半導体集積
回路装置は、第1の電源配線と第2の電源配線を電源接
続配線により接続して内部回路ブロックと外部回路プロ
ックを共通電位で駆動するためには、消費電力の大きい
内部ブロックに電力を供給する第1の電源配線の電流容
量を増大させるために配線幅を広げる必要があり、チッ
プサイズが大きくなるという問題点があった。
In this conventional semiconductor integrated circuit device, the first power source wiring and the second power source wiring are connected by the power source connecting wiring to drive the internal circuit block and the external circuit block at a common potential. Therefore, it is necessary to widen the wiring width in order to increase the current capacity of the first power supply wiring that supplies power to the internal block that consumes a large amount of power, and there is a problem that the chip size becomes large.

【0005】[0005]

【課題を解決するための手段】本発明の半導体集積回路
装置は、半導体チップ上に設けた内部回路ブロックと、
前記内部回路ブロックの周囲を取囲んで設けた第1の電
源配線と、前記第1の電源配線の外周に配置して設けた
外部回路ブロックと、前記外部回路ブロックの上に設け
且つ前記第1の電源配線の外周を取囲んで設けた第2の
電源配線と、前記外部回路ブロックの外周に設けた電源
用パッドに接続して前記第1及び第2の電源配線に電力
を供給するための電源接続配線と、前記電源接続配線以
外の領域に設けて前記第1及び第2の電源配線間を接続
する付加電源接続配線とを備えている。
A semiconductor integrated circuit device according to the present invention comprises an internal circuit block provided on a semiconductor chip,
A first power supply wiring provided around the internal circuit block, an external circuit block arranged on the outer periphery of the first power supply wiring, and a first power supply wiring provided on the external circuit block. For supplying power to the first and second power supply wirings by connecting to a second power supply wiring provided around the outer circumference of the power supply wiring and a power supply pad provided on the outer circumference of the external circuit block. Power supply connection wirings and additional power supply connection wirings that are provided in regions other than the power supply connection wirings and connect the first and second power supply wirings are provided.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0007】図1は本発明の一実施例を示すレイアウト
図である。
FIG. 1 is a layout diagram showing an embodiment of the present invention.

【0008】図1に示すように、半導体チップ上に設け
た内部回路ブロック9と、内部回路プロック9の周囲を
取囲んで設けた第1の電源配線1,2(但し電源配線1
はVDD用,電源配線2はGND用)と、第1の電源配線
1,2の外周に設けた外部回路ブロック10と、外部回
路ブロック10の上に設け、且つ第1の電源配線1,2
の外周に設けた第2の電源配線3,4(但し電源配線3
はGND用,電源配線4はVDD用)と、外部回路ブロッ
ク10の外周に設けたVDD用電極パッド11及びGND
用電源パッド12と、VDD用電源パッド11に接続して
第1及び第2の電源配線1,4にコンタクトホール14
を介して接続した電源接続配線5及びGND用電源パッ
ド12に接続して第1及び第2の電源配線2,3にコン
タクトホール14を介して接続した電源接続配線6と、
外部回路ブロック10の外周に設けて外部回路ブロック
10と接続する信号用パッド15と、どこにも電気的に
接続しない空きパッド16と、空きパッド16の位置で
第1及び第2の電源配線間をコンタクトホール14を介
して接続する付加電源接続配線17,18とを備えて構
成される。
As shown in FIG. 1, the internal circuit block 9 provided on the semiconductor chip and the first power supply wirings 1 and 2 provided around the internal circuit block 9 (however, the power supply wiring 1
Is for V DD , the power supply wiring 2 is for GND), the external circuit block 10 is provided on the outer periphery of the first power supply wirings 1 and 2, and the first power supply wiring 1 is provided on the external circuit block 10. Two
The second power supply wirings 3 and 4 provided on the outer periphery of the
Is for GND, the power supply wiring 4 is for V DD ), and the V DD electrode pad 11 and GND provided on the outer periphery of the external circuit block 10.
For connecting the power supply pad 12 for power supply and the power supply pad 11 for V DD to the first and second power supply wirings 1 and 4
A power supply connection wiring 5 and a power supply connection wire 12 for GND, which are connected via the contact hole 14 to the first and second power supply wirings 2 and 3;
The signal pad 15 provided on the outer periphery of the external circuit block 10 and connected to the external circuit block 10, the empty pad 16 not electrically connected to anywhere, and the empty pad 16 between the first and second power supply wirings Additional power supply connection wirings 17 and 18 connected through the contact holes 14 are provided.

【0009】なお、付加電源接続配線7,8の数を増や
すことにより第1の電源配線の電流容量、即ち配線幅を
更に細くすることができると共に付加電源接続配線の線
幅も細くすることができる利点がある。
By increasing the number of the additional power supply connection wires 7 and 8, the current capacity of the first power supply wire, that is, the wiring width can be further reduced, and the line width of the additional power supply connection wiring can be reduced. There are advantages.

【0010】[0010]

【発明の効果】以上説明したように本発明は、第1の電
源配線と第2の電源配線間を接続する電源接続配線以外
に付加電源接続配線を設けることにより消費電力の大き
い内部回路ブロックへ電力を供給する第1の電源配線の
配線幅を細くすることができ、チップサイズを小さくす
ることができるという効果を有する。
As described above, according to the present invention, an additional power supply connection wiring is provided in addition to the power supply connection wiring for connecting the first power supply wiring and the second power supply wiring to the internal circuit block consuming large power. The width of the first power supply line for supplying electric power can be reduced, and the chip size can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すレイアウト図。FIG. 1 is a layout diagram showing an embodiment of the present invention.

【図2】従来の半導体集積回路装置の一例を示すレイア
ウト図。
FIG. 2 is a layout diagram showing an example of a conventional semiconductor integrated circuit device.

【符号の説明】[Explanation of symbols]

1,2 第1の電源配線 3,4 第2の電源配線 5,6 電源接続配線 7,8 付加電源接続配線 9 内部回路ブロック 10 外部回路ブロック 11 VDD用電源パッド 12 GND用電源パッド 14 コンタクトホール 15 信号用パッド 16 空きパッド1, 2 First power supply wiring 3, 4 Second power supply wiring 5, 6 Power supply connection wiring 7, 8 Additional power supply connection wiring 9 Internal circuit block 10 External circuit block 11 V DD power supply pad 12 GND power supply pad 14 Contacts Hall 15 Signal pad 16 Empty pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ上に設けた内部回路ブロッ
クと、前記内部回路ブロックの周囲を取囲んで設けた第
1の電源配線と、前記第1の電源配線の外周に配置して
設けた外部回路ブロックと、前記外部回路ブロックの上
に設け且つ前記第1の電源配線の外周を取囲んで設けた
第2の電源配線と、前記外部回路ブロックの外周に設け
た電源用パッドに接続して前記第1及び第2の電源配線
に電力を供給するための電源接続配線と、前記電源接続
配線以外の領域に設けて前記第1及び第2の電源配線間
を接続する付加電源接続配線とを備えたことを特徴とす
る半導体集積回路装置。
1. An internal circuit block provided on a semiconductor chip, a first power supply wiring provided around the internal circuit block, and an external device arranged on the outer periphery of the first power supply wiring. A circuit block, a second power supply wiring provided on the external circuit block and surrounding the outer periphery of the first power supply wiring, and a power supply pad provided on the outer periphery of the external circuit block. A power supply connection wiring for supplying electric power to the first and second power supply wirings, and an additional power supply connection wiring provided in a region other than the power supply connection wiring and connecting the first and second power supply wirings. A semiconductor integrated circuit device characterized by comprising.
【請求項2】 付加電源接続配線が外部回路ブロックの
外周に設けた空パッドの位置に配置された請求項1記載
の半導体集積回路装置。
2. The semiconductor integrated circuit device according to claim 1, wherein the additional power supply connection wiring is arranged at a position of an empty pad provided on the outer periphery of the external circuit block.
JP4061601A 1992-03-18 1992-03-18 Semiconductor integrated circuit device Withdrawn JPH0629395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4061601A JPH0629395A (en) 1992-03-18 1992-03-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4061601A JPH0629395A (en) 1992-03-18 1992-03-18 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0629395A true JPH0629395A (en) 1994-02-04

Family

ID=13175854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4061601A Withdrawn JPH0629395A (en) 1992-03-18 1992-03-18 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0629395A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU705476B1 (en) * 1997-10-22 1999-05-20 Casio Computer Co., Ltd. Contact charging member, image forming unit including the contact charging member and electrophotographic image forming apparatus including the image forming unit
JP2002299452A (en) * 2001-03-30 2002-10-11 Fujitsu Ltd Semiconductor integrated circuit and method for designing layout of power source
JP2003289104A (en) * 2002-03-28 2003-10-10 Ricoh Co Ltd Protection circuit for semiconductor device and the semiconductor device
JP2005217314A (en) * 2004-01-30 2005-08-11 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
JP2006245596A (en) * 2006-04-03 2006-09-14 Ricoh Co Ltd Semiconductor device
KR101330683B1 (en) * 2008-05-23 2013-11-18 미쓰미덴기가부시기가이샤 Semiconductor device and semiconductor integrated circuit device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139702A (en) * 1984-12-12 1986-06-27 Nec Corp Angle detection element
JPH034805A (en) * 1989-05-23 1991-01-10 Kishun Shu Electrically-heated eyelash curler

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139702A (en) * 1984-12-12 1986-06-27 Nec Corp Angle detection element
JPH034805A (en) * 1989-05-23 1991-01-10 Kishun Shu Electrically-heated eyelash curler

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU705476B1 (en) * 1997-10-22 1999-05-20 Casio Computer Co., Ltd. Contact charging member, image forming unit including the contact charging member and electrophotographic image forming apparatus including the image forming unit
JP2002299452A (en) * 2001-03-30 2002-10-11 Fujitsu Ltd Semiconductor integrated circuit and method for designing layout of power source
JP2003289104A (en) * 2002-03-28 2003-10-10 Ricoh Co Ltd Protection circuit for semiconductor device and the semiconductor device
JP2005217314A (en) * 2004-01-30 2005-08-11 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
JP2006245596A (en) * 2006-04-03 2006-09-14 Ricoh Co Ltd Semiconductor device
KR101330683B1 (en) * 2008-05-23 2013-11-18 미쓰미덴기가부시기가이샤 Semiconductor device and semiconductor integrated circuit device

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518