JP2006245596A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an area occupied by a protection circuit, without increasing the number of manufacturing processes for a semiconductor device. <P>SOLUTION: In the formation region of an electrode pad 7, N+ diffusion regions 19a, 19b, and 19c are formed on the surface of a P type semiconductor substrate 3 so as to be separated from each other by a field oxide film 21. Lower layer metal wiring layers 25a, 25b, and 25c are formed on the field oxide film 21 and an insulating film 23. Furthermore, a Vcc line 13a, a GND line 13b, and a metal wiring layer 13c are formed via an inter-layer insulating layer 27 on this. The Vcc line 13a and the GND line 13b are formed continuously across the formation region of a plurality of electrode pads 7. Moreover, the electrode pad 7 is formed via an inter-layer insulating film 29 on this. The Vcc line 13a and the N+ diffusion region 19a, the GND line 13b and the N+ diffusion region 19b, and the electrode pad 7 and the N+ diffusion region 19c are electrically connected to each other. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a protection circuit for preventing destruction of an internal circuit due to an excessive input voltage from an electrode pad.

10A and 10B are plan views showing a conventional semiconductor device, in which FIG. 10A shows the whole and FIG. 10B shows an enlarged part of the periphery of a power supply pad and a GND pad.
For example, the inner core region 5 is formed in the central portion of the semiconductor device 46 made of the P-type semiconductor substrate 3. An internal circuit is formed in the internal core region 5 by a plurality of semiconductor elements.
A plurality of electrode pads 7 are formed on the periphery of the semiconductor device 46. An I / O cell 47 is provided for each electrode pad 7 on the semiconductor substrate 3 between the inner core region 5 and the electrode pad 7.

  Between the internal core region 5 and the I / O cell 47, an internal core region Vcc line 11a and an internal core region GND (ground) line 11b made of a metal wiring layer are provided so as to surround the internal core region 5. Is formed. An I / O cell Vcc line 49 a and an I / O cell GND line 49 b made of a metal wiring layer are formed continuously over the plurality of I / O cells 47.

  The internal core region Vcc line 11a is electrically connected to the metal wiring layer 51a electrically connected to the power supply electrode pad 7a via the connection hole 11c and the I / O cell Vcc line 49a is electrically connected to the power supply electrode pad 7a. It is connected to the. The internal core area GND line 11b is connected to the metal wiring layer 51b electrically connected to the GND electrode pad 7b via the connection hole 11d and the I / O cell GND line 49b connection hole is connected to the GND electrode pad 7b. Electrically connected. The internal core region Vcc line 11a is electrically connected to the metal wiring layer 53a extending toward the internal core region 5 through the connection hole 11e. The inner core region GND line 11b is electrically connected to the metal wiring layer 53b extending to the inner core region 5 side through the connection hole 11f.

FIG. 11 is a plan view showing an example of the configuration of the electrode pad 7 and the I / O cell 47. FIG. 12 is an equivalent circuit thereof.
Each I / O cell 47 includes a protection circuit 55 and an input buffer 17. The protection circuit 55 includes a diode-connected P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor, hereinafter referred to as MOS transistor) Tr5, a diode-connected N-channel MOS transistor Tr6, and a resistor R.

The MOS transistor Tr5 is formed in a Pch region of an N-well (N-WELL) formed on a P-type semiconductor substrate, and the source and drain of the MOS transistor Tr5 are formed by a P + diffusion layer (P +) formed in the N-well. The gate electrode is constituted by a polysilicon gate electrode 55. The area necessary for forming the MOS transistor Tr5 is about 1800 μm ² .
The MOS transistor Tr6 is formed in the Nch region of the P-type semiconductor substrate, the source and drain of the MOS transistor Tr6 are configured by N + diffusion layers (N +) formed in the P-type semiconductor substrate, and the gate electrode is formed by the polysilicon gate electrode 57. Composed. The area necessary for forming the MOS transistor Tr6 is about 1000 μm ² .

  The polysilicon gate electrode 55 and the source of the MOS transistor Tr5 are connected to the power supply Vcc. The drain of the MOS transistor Tr5 and the drain of the MOS transistor Tr6 are connected to each other and connected to the electrode pad 7. The polysilicon gate electrode 57 and the source of the MOS transistor Tr6 are connected to GND. One end of a resistor R is connected to a connection point between the drain of the MOS transistor Tr5 and the drain of the MOS transistor Tr6.

The input buffer 17 is composed of an inverter circuit composed of a P-channel MOS transistor Tr3 and an N-channel MOS transistor Tr4.
The MOS transistor Tr3 is formed in a Pch region of an N-well (N-WELL) formed on a P-type semiconductor substrate, and the source and drain of the MOS transistor Tr3 are formed by a P + diffusion layer (P +) formed in the N-well. The gate electrode is composed of a polysilicon gate electrode 59. The MOS transistor Tr4 is formed in the Nch region of the P-type semiconductor substrate, the source and drain of the MOS transistor Tr4 are configured by an N + diffusion layer (N +) formed in the P-type semiconductor substrate, and the gate electrode is formed by the polysilicon gate electrode 61. Composed.

  The source of the MOS transistor Tr3 is connected to the power supply Vcc. The source of the MOS transistor Tr4 is connected to GND. The drains of the MOS transistor Tr3 and the MOS transistor Tr4 are connected to each other and led to the internal core region 5. The polysilicon gate electrode 59 of the MOS transistor Tr3 and the polysilicon gate electrode 61 of the MOS transistor Tr4 are connected to each other and connected to the other end of the resistor R.

  As shown in FIGS. 10 to 12, conventionally, no circuit is formed on the semiconductor substrate 3 in the formation region of the electrode pad 7. This is because, in the assembling process of the semiconductor device, a metal wiring layer constituting the electrode pad 7 may be penetrated during wire bonding in which the electrode pad 7 and an external terminal are electrically connected through a bonding wire. This is because. As a countermeasure, a well or the like has been formed in the semiconductor substrate 3 in the formation region of the electrode pad 7.

With recent miniaturization, downsizing (shrinking) for reducing the cost of semiconductor products is progressing.
On the other hand, with respect to the I / O cell, a protection circuit is generally provided to prevent destruction of the internal circuit due to an excessive input voltage from the electrode pad. Since the area occupied by the protection circuit cannot be reduced, the shrinkage is hindered.

In addition, with the miniaturization, the inner core region becomes smaller, and the ratio of the I / O cell to the semiconductor device increases. In proceeding with shrinking, it is urgent to reduce the area occupied by the I / O cell in the semiconductor device. It has become. Moreover, as shown in FIG. 11, the ratio occupied by the formation region of the electrode pad 7 is high.
Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing the area of the semiconductor device.

  A semiconductor device according to the present invention includes a plurality of electrode pads for electrical connection to the outside, and a protection circuit for each of the electrode pads. An internal core region is provided as a power line and a GND line. A power line for I / O cells and a GND line for I / O cells are provided in addition to the power line for internal use and the GND line for internal core area. It is characterized by being formed continuously across regions.

The power line for I / O cells and the GND line for I / O cells can be configured by a metal wiring layer or a polysilicon wiring layer.
Further, five or more metal wiring layers may be formed in a layer between the semiconductor substrate and the electrode pad.
In the present specification, the first conductivity type means a P-type or N-type conductivity type, and the second conductivity type means an N-type or P-type opposite to the first conductivity type. The word “power supply potential” includes both a high potential side potential such as VDD and Vcc and a low potential side potential such as VSS and GND. The term MOS transistor includes a field transistor.

  In the semiconductor device according to the present invention, the I / O cell power line and the I / O cell GND line, which are conventionally formed in a region different from the electrode pad formation region, are continuously formed across the electrode pad formation region. As a result, the area of the semiconductor device can be reduced.

  If a metal wiring layer or a polysilicon wiring layer is used as the power line for I / O cells and the GND line for I / O cells, the power supply for I / O cells is continuously provided across a plurality of electrode pad formation regions. Lines and GND lines for I / O cells can be formed.

  In addition, if five or more metal wiring layers are formed between the semiconductor substrate and the electrode pad, the adverse effect caused by wire bonding can be reduced in the protection circuit.

  1A and 1B are diagrams illustrating a peripheral portion of a protection circuit according to an embodiment of a semiconductor device, in which FIG. 1A is a cross-sectional view, FIG. 1B is a plan view at the position A-A in FIG. It is a top view in the BB position of A). (A) is sectional drawing in CC position of (B) and (C). 2A and 2B are plan views showing this embodiment, in which FIG. 2A shows the whole, and FIG. 2B shows an enlarged portion surrounded by a circle in FIG.

For example, the inner core region 5 is formed in the central portion of the semiconductor device 1 made of the P-type semiconductor substrate 3. An internal circuit is formed in the internal core region 5 by a plurality of semiconductor elements.
A plurality of electrode pads 7 are formed on the periphery of the semiconductor device 1. An I / O cell 9 is provided for each electrode pad 7 on the semiconductor substrate 3 including the formation region of the electrode pad 7.

  Between the internal core region 5 and the I / O cell 9, an internal core region Vcc line 11a and an internal core region GND line 11b made of a metal wiring layer are formed so as to surround the internal core region 5. Yes. An I / O cell Vcc line 13a and an I / O cell GND line 13b made of a metal wiring layer are formed continuously over a region where the plurality of electrode pads 7 are formed. Here, Vcc is the high potential side potential of the power supply potential, and GND is the low potential side potential of the power supply potential.

The internal core region Vcc line 11a and the I / O cell Vcc line 13a are composed of metal wiring below the electrode pad 7, and a metal wiring layer formed in the same layer as the electrode pad 7 (not shown). Is electrically connected to the electrode pad 7 for power supply.
The internal core region GND line 11b and the I / O cell GND line 13b are composed of metal wiring below the electrode pad 7, and are formed on the same layer as the electrode pad 7 (not shown). Is electrically connected to the electrode pad 7 for GND.

FIG. 3 is an equivalent circuit showing an example of the configuration of the electrode pad 7 and the I / O cell 9.
Each I / O cell 9 includes a protection circuit 15 and an input buffer 17. The protection circuit 15 includes an N-channel field transistor Tr1, an N-channel field transistor Tr2, and a resistor R made of a diffusion layer. Here, the resistor R is formed of a diffusion layer, but the present invention is not limited to this, and may be a resistor made of a polysilicon film or a metal thin film.

  The drain of the field transistor Tr1 is connected to the power supply Vcc. The source of the field transistor Tr1 and the drain of the field transistor Tr2 are connected to each other and connected to the electrode pad 7. The gate electrode of the field transistor Tr1 and the gate electrode of the field transistor Tr2 are connected to each other and connected to the electrode pad 7. One end of a resistor R is connected to a connection point between the source of the field transistor Tr1 and the drain of the field transistor Tr2.

  The input buffer 17 is composed of an inverter circuit composed of a P-channel MOS transistor Tr3 and an N-channel MOS transistor Tr4. The source of the MOS transistor Tr3 is connected to the power supply Vcc. The source of the MOS transistor Tr4 is connected to GND. The drains of the MOS transistor Tr3 and the MOS transistor Tr4 are connected to each other and led to the internal core region 5. The gate electrode of the MOS transistor Tr3 and the gate electrode of the MOS transistor Tr4 are connected to each other and connected to the other end of the resistor R.

  The MOS transistors Tr3 and Tr4 and the diffused resistor R are not shown, but are P-type between the electrode pad 7 in the formation region of the I / O cell 9 and the Vcc line 11a for the internal core region shown in FIG. It is formed on the semiconductor substrate 3.

The configuration of the protection circuit 15 will be described with reference to FIG. In FIG. 1, the resistor R is not shown.
N + diffusion regions 19a, 19b, 19c are formed on the surface of a P-type semiconductor substrate (P-substrate) 3. N + diffusion regions 19a, 19b, 19c are separated from each other by field oxide film 21. The N + diffusion region 19a is formed with an interval from the N + diffusion region 19c. The N + diffusion region 19b is formed on the opposite side of the N + diffusion region 19a with respect to the N + diffusion region 19c with a space from the N + diffusion region 19c. Here, the N + diffusion region 19a constitutes a second diffusion region constituting the protection circuit of the semiconductor device of the present invention, the N + diffusion region 19b constitutes a third diffusion region, and the N + diffusion region 19c constitutes the first diffusion region. Constitute.

  The N + diffusion region 19a corresponds to the drain of the field transistor Tr1 in FIG. 3, the N + diffusion region 19b corresponds to the source of the field transistor Tr2 in FIG. 3, and the N + diffusion region 19c corresponds to the source and field transistor of the field transistor Tr1 in FIG. It corresponds to the drain of Tr2.

  Insulating films 23 are formed on the surfaces of the N + diffusion regions 19a, 19b, and 19c, respectively. Lower metal wiring layers 25a, 25b, and 25c are formed on field oxide film 21 and insulating film 23 so as to be separated from each other. Lower metal wiring layer 25a is electrically connected to N + diffusion region 19a through a connection hole formed in insulating film 23. Lower metal wiring layer 25 b is electrically connected to N + diffusion region 19 b through a connection hole formed in insulating film 23. Lower metal wiring layer 25 c is electrically connected to N + diffusion region 19 c through a connection hole formed in insulating film 23. Lower metal interconnection layer 25c is formed to extend from field oxide film 21 between N + diffusion regions 19a and 19c to field oxide film 21 between N + diffusion regions 19b and 19c. The metal wiring layer 25c corresponds to the gate electrodes of the field transistors Tr1 and Tr2 in FIG.

  An interlayer insulating layer 27 is formed on the field oxide film 21, the insulating film 23, and the lower metal wiring layers 25a, 25b, and 25c. Further, an I / O cell Vcc line 13a, I / O comprising a metal wiring layer is formed thereon. An O cell GND line 13b and a metal wiring layer 13c are formed. As shown in FIG. 2, the I / O cell Vcc line 13 a and the I / O cell GND line 13 b are continuously formed across the formation regions of the plurality of electrode pads 7.

  In the interlayer insulating layer 27, a connection hole for electrically connecting the lower metal wiring layer 25a and the I / O cell Vcc line 13a, and the lower metal wiring layer 25b and the I / O cell GND line 13b are electrically connected. A connection hole for connection and a connection hole for electrically connecting the lower metal wiring layer 25c and the metal wiring layer 13c are formed.

  An interlayer insulating layer 29 is formed on the interlayer insulating layer 27, the I / O cell Vcc line 13a, the I / O cell GND line 13b, and the metal wiring layer 13c. A pad 7 is formed. A passivation film 31 is formed on the interlayer insulating layer 29 and the electrode pad 7. In the passivation film 31, a pad opening is formed on the electrode pad 7. In the interlayer insulating layer 29, a connection hole for electrically connecting the metal wiring layer 13c and the electrode pad 7 is formed.

  Any one of the electrode pads 7 on the semiconductor device 1 is used as a Vcc electrode pad 7a as shown in FIG. In the formation region of the Vcc electrode pad 7a, a connection hole for electrically connecting the Vcc electrode pad 7a and the I / O cell Vcc line 13a is formed in the interlayer insulating film 29.

  Further, any electrode pad 7 on the semiconductor device 1 different from the Vcc electrode pad 7a is used as the GND electrode pad 7b as shown in FIG. In the formation region of the GND electrode pad 7 b, a connection hole for electrically connecting the GND electrode pad 7 b and the I / O cell GND line 13 b is formed in the interlayer insulating film 29.

An example of the operation of the protection circuit 15 will be described with reference to FIG.

  In Table 1, “surge applied voltage” means an excessive input voltage applied to the electrode pad 7. Generally, the surge test is performed by a method called HBM (Human Body Model), and the voltage applied at that time is as shown in Table 1.

When a voltage of +2 kV (kilovolt) is applied to the electrode pad 7 with respect to the power supply Vcc, the field transistor Tr1 is turned on, and the surge applied voltage is extracted to the power supply Vcc by the on-current (see (1) in Table 1) ).
When a voltage of -2 kV is applied to the electrode pad 7 with respect to the power supply Vcc, a punch-through current flows through the field transistor Tr1, and the surge applied voltage is extracted to the power supply Vcc (see (2) in Table 1).

When a voltage of +2 kV with respect to GND is applied to the electrode pad 7, the field transistor Tr2 is turned on, and the surge application voltage is extracted to GND by the on-current (see (1) in Table 1).
When a voltage of −2 kV with respect to GND is applied to the electrode pad 7, a punch-through current flows through the field transistor Tr2, and the surge applied voltage is extracted to GND (see (2) in Table 1).
In this way, even if an excessive input voltage is applied to the electrode pad 7, the MOS transistors Tr3 and Tr4 constituting the input buffer 17 can be protected.

  In this embodiment, since the field transistors Tr1 and Tr2 constituting the protection circuit 15 are formed in the formation region of the electrode pad 7, the area of the semiconductor device 1 can be reduced. Furthermore, since the I / O cell Vcc line 13a and the I / O cell GND line 13b are formed in the formation region of the electrode pad 7, the area of the semiconductor device 1 can be reduced.

  It should be noted that in the region where the electrode pad 7 is formed, the wire bonding damage in the assembly process is not zero. Therefore, in order to place the semiconductor element constituting the internal core region 5 in the region where the electrode pad 7 is formed, the damage Since changes in characteristics cannot be ignored, it is not possible to place a semiconductor element that is designed by simulation based on basic characteristics. However, the protection circuit is not usually simulated and only needs to function, so a delicate design is not usually required. Therefore, there is no problem even if the field transistors Tr1 and Tr2 constituting the protection circuit 15 are formed in the formation region of the electrode pad 7.

  This embodiment has a three-layer metal wiring structure as shown in FIG. 1A, but the present invention is not limited to this, and a one-layer metal wiring structure, a two-layer metal wiring structure, or 4 It can be applied to a semiconductor device having a metal wiring structure of more than one layer. However, in the case of a one-layer metal wiring structure, the power supply line and the GND line are formed in a region different from the electrode pad formation region.

  When the design rule is around half a micron, the three-layer metal wiring structure as shown in FIG. In FIG. 1A, for example, lower metal wiring layers 25a, 25b, 25c, I / O cell Vcc line 13a, I / O cell GND line 13b, metal wiring layer 13c and electrodes in the formation region of electrode pad 7 The film thickness of the pad 7 is about 700 nm (nanometers), and the film thickness of the interlayer insulating layers 27 and 29 is about 800 nm. Therefore, in the three-layer metal wiring structure, the film thickness from the surface of the field oxide film 21 to the surface of the electrode pad 7 is about 3700 nm.

  In recent years, design rules are becoming quarter micron or sub-quarter micron. In a semiconductor device using these design rules, for example, a six-layer metal wiring structure is used.

FIG. 5 is a cross-sectional view showing a protection circuit of an embodiment applied to a six-layer metal wiring structure. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
N + diffusion regions 19a, 19b, and 19c are formed on the surface of the P-type semiconductor substrate 3 by being separated by the field oxide film 21. Insulating films 23 are respectively formed on the surfaces of the N + diffusion regions 19a, 19b, and 19c. Lower metal wiring layers 25a, 25b, and 25c are formed on field oxide film 21 and insulating film 23 so as to be separated from each other. The lower metal wiring layer 25a and the N + diffusion region 19a, the lower metal wiring layer 25b and the N + diffusion region 19b, and the lower metal wiring layer 25c and the N + diffusion region 19c are electrically connected through connection holes formed in the insulating film 23, respectively. It is connected.

  An interlayer insulating layer 27 is formed on the field oxide film 21, the insulating film 23, and the lower metal wiring layers 25a, 25b, and 25c, and second metal wiring layers 33a, 33b, and 33c separated from each other are formed on the interlayer insulating layer 27. The insulating film 35, the third metal wiring layers 37a, 37b, and 37c separated from each other, the interlayer insulating film 38, and the fourth metal wiring layers 39a, 39b, and 39c separated from each other are sequentially stacked. Connection holes are formed at predetermined positions in the interlayer insulating layers 27, 35, and 38. The lower metal wiring layer 25a, the second metal wiring layer 33a, the third metal wiring layer 37a, and the fourth metal wiring layer 39a are electrically connected. The lower metal wiring layer 25b, the second metal wiring layer 33b, the third metal wiring layer 37b, and the fourth metal wiring layer 39b are electrically connected, and the lower metal wiring layer 25c and the second metal wiring layer 33c are connected. The third metal wiring layer 37c and the fourth metal wiring layer 39c are electrically connected.

  An interlayer insulating layer 40 is formed on the interlayer insulating layer 38 and on the fourth metal wiring layers 39a, 39b, 39c, and further on the I / O cell Vcc line 13a, I / O comprising the fifth metal wiring layer. An O cell GND line 13b and a metal wiring layer 13c are formed. Similar to the embodiment shown in FIG. 2, the I / O cell Vcc line 13a and the I / O cell GND line 13b are continuously formed across the formation regions of the plurality of electrode pads 7. An interlayer insulating layer 29 is formed on the interlayer insulating layer 40, the I / O cell Vcc line 13a, the I / O cell GND line 13b, and the metal wiring layer 13c, and further includes a top metal wiring layer thereon. An electrode pad 7 is formed. A passivation film 31 is formed on the interlayer insulating layer 29 and the electrode pad 7. In the passivation film 31, a pad opening is formed on the electrode pad 7.

  In the formation region of the electrode pad 7 of this embodiment, the lower metal wiring layers 25a, 25b, 25c, the second metal wiring layers 33a, 33b, 33c, the third metal wiring layers 37a, 37b, 37c, and the fourth metal wiring layer 39a. 39b, 39c, the I / O cell Vcc line 13a, the I / O cell GND line 13b, the metal wiring layer 13c, and the electrode pad 7 have a thickness of about 700 nm. The film thickness of the insulating layers 27, 35, 38, 40, 29 between the metal layers is about 700 nm. Therefore, the film thickness from the surface of the field oxide film 21 to the surface of the electrode pad 7 is about 7700 nm.

  Thus, since the film thickness in the formation region of the electrode pad 7 is thicker in the 6-layer metal wiring structure than in the 3-layer metal wiring structure, damage applied to the semiconductor substrate 3 during wire bonding can be reduced. Thus, it is possible to prevent the field transistors constituting the protection circuit from being damaged.

  In the above embodiment, the field transistor is used as the protection element of the protection circuit. However, the present invention is not limited to this, and a MOS transistor having a polysilicon gate may be used as the protection element of the protection circuit. .

  6A and 6B are diagrams showing a peripheral portion of a protection circuit of an embodiment using a MOS transistor having a polysilicon gate as a protection element of the protection circuit. FIG. 6A is a cross-sectional view, and FIG. The top view in A position, (C) is a top view in the BB position of (A). Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. An example of an equivalent circuit of the I / O cell of this embodiment is shown in FIG. The plan view of this embodiment is the same as FIG.

  N + diffusion regions 19a, 19b, 19c are formed on the surface of the P-type semiconductor substrate 3. N + diffusion regions 19 a, 19 b and 19 c are formed in a region surrounded by field oxide film 41. The N + diffusion region 19a is formed with a space from the N + diffusion region 19c, and the N + diffusion region 19b is formed with a space from the N + diffusion region 19c on the opposite side of the N + diffusion region 19a.

  An insulating film 43 is formed on the surface of the semiconductor substrate 3 surrounded by the field oxide film 41, including the surfaces of the N + diffusion regions 19a, 19b, and 19c. Polysilicon gate 22a is formed on insulating film 43 between N + diffusion regions 19a and 19c. Polysilicon gate 22b is formed on insulating film 43 between N + diffusion regions 19b and 19c. An insulating film is formed on the surfaces of the polysilicon gates 22a and 22b.

  Lower metal wiring layers 26a, 26b and 26c are formed on the insulating film 43 and the polysilicon gates 22a and 22b so as to be separated from each other. The lower metal wiring layer 26b is formed across the polysilicon gate 22b and the N + diffusion region 19b. The lower metal wiring layer 26c is formed across the polysilicon gate 22a and the N + diffusion region 19c.

  Lower metal wiring layer 26 a is electrically connected to N + diffusion region 19 a through a connection hole formed in insulating film 43. Lower metal wiring layer 26b is electrically connected to N + diffusion region 19b through a connection hole formed in insulating film 43, and is also electrically connected to polysilicon gate 22b through the connection hole. Lower metal wiring layer 26c is electrically connected to N + diffusion region 19c through a connection hole formed in insulating film 43, and is also electrically connected to polysilicon gate 22a through the connection hole.

An interlayer insulating layer 27 is formed on the field oxide film 21, the insulating film 43, the polysilicon gates 22a and 22b, and the lower metal wiring layers 26a, 26b and 26c, and the I / O cell Vcc line 13a is further formed thereon. The I / O cell GND line 13b and the metal wiring layer 13c are formed. As shown in FIG. 2, the I / O cell Vcc line 13 a and the I / O cell GND line 13 b are continuously formed across the formation regions of the plurality of electrode pads 7.
An interlayer insulating layer 29 is formed on the interlayer insulating layer 27, on the I / O cell Vcc line 13a, on the I / O cell GND line 13b, and on the metal wiring layer 13c, and further on the electrode pad 7 and the passivation film. 31 is formed.

  In this embodiment, when an excessive input voltage is applied to the electrode pad 7, the MOS transistor is constituted by the N + diffusion regions 19a and 19c and the polysilicon gate 22a or is constituted by the N + diffusion regions 19b and 19c and the polysilicon gate 22b. An excessive input voltage at the electrode pad 7 is drawn to the power supply Vcc or GND by the ON current or punch-through current of the MOS transistor.

  FIGS. 8A and 8B are diagrams showing a peripheral portion of a protective circuit according to another embodiment using a field transistor as a protective element of the protective circuit. FIG. 8A is a cross-sectional view, and FIG. 8B is a position AA in FIG. (C) is a top view in the BB position of (A). Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. An example of an equivalent circuit of the I / O cell of this embodiment is shown in FIG. The plan view of this embodiment is the same as FIG.

  N + diffusion regions 19a, 19b, 19c are formed on the surface of the P-type semiconductor substrate 3. N + diffusion regions 19a, 19b and 19c are separated from each other by field oxide film 21. The N + diffusion region 19a is formed with a space from the N + diffusion region 19c, and the N + diffusion region 19b is formed with a space from the N + diffusion region 19c on the opposite side of the N + diffusion region 19a.

  An insulating film 23 is formed on the surfaces of the N + diffusion regions 19a, 19b, and 19c. Lower metal wiring layers 45a, 45b and 45c are formed on insulating film 23 so as to be separated from each other. Lower metal interconnection layer 45a is electrically connected to N + diffusion region 19a through a connection hole formed in insulating film 23. Lower metal wiring layer 45b is electrically connected to N + diffusion region 19b through a connection hole formed in insulating film 23. Lower metal wiring layer 45c is electrically connected to N + diffusion region 19c through a connection hole formed in insulating film 23. The metal wiring layer 45 c is not formed on the field oxide film 21.

An interlayer insulating layer 27 is formed on the field oxide film 21, the insulating film 23, and the lower metal wiring layers 45a, 45b, and 45c. Further, an I / O cell Vcc line 13a and an I / O cell GND line are formed thereon. 13b and a metal wiring layer 13c are formed. As shown in FIG. 2, the I / O cell Vcc line 13 a and the I / O cell GND line 13 b are continuously formed across the formation regions of the plurality of electrode pads 7.
An interlayer insulating layer 29 is formed on the interlayer insulating layer 27, on the I / O cell Vcc line 13a, on the I / O cell GND line 13b, and on the metal wiring layer 13c, and further on the electrode pad 7 and the passivation film. 31 is formed.

  In this embodiment, when an excessive input voltage is applied to the electrode pad 7, a field transistor composed of the P-type semiconductor substrate 3 and the N + diffusion regions 19a and 19c, or the P-type semiconductor substrate 3 and the N + diffusion region 19b, An excessive input voltage at the electrode pad 7 is drawn to the power supply Vcc or GND by the punch-through current of the field transistor constituted by 19c.

  In the embodiment shown in FIGS. 1 to 9, the N + diffusion region 19c as the first diffusion region, the N + diffusion region 19a as the second diffusion region, and the N + diffusion region 19b as the third diffusion region are used. Although there is a portion formed outside the formation region, the present invention is not limited to this, and all of the first diffusion region, the second diffusion region, and the third diffusion region are within the formation region of the electrode pad 7. It may be formed.

  Further, a part of the N + diffusion region 19c, the N + diffusion region 19a, and the N + diffusion region 19b is arranged in the formation region of the electrode pad 7, but the present invention is not limited to this. Instead, any configuration may be used as long as a part or all of the diffusion region constituting the protection element of the protection circuit is arranged in the formation region of the electrode pad 7 and the size of the semiconductor device can be reduced. .

  In this embodiment, the I / O cell Vcc line 13a and the I / O cell GND line 13b as the power supply lines are formed by the metal wiring layer, but the present invention is not limited to this. For example, it may be formed of a polysilicon film whose resistance is reduced by silicidation.

  In the equivalent circuit shown in FIG. 3, the I / O cell provided with the input buffer 17 is described. However, the present invention is not limited to this, and the output buffer is replaced with the input buffer 17. The protection circuit for a semiconductor device and the semiconductor device of the present invention can also be applied to an I / O cell including the above.

  In the above embodiment, the protection circuit is formed on the P-type semiconductor substrate. However, the present invention is not limited to this, and the protection circuit may be formed on the P-type well, or the N-type semiconductor substrate. Alternatively, it may be formed in an N-type well. When the protection circuit is formed on the N-type semiconductor substrate or the N-type well, the diffusion region is formed by a P-type diffusion region. Further, the diffusion region is not limited to a single-layer diffusion region, and may be composed of a multilayer diffusion region.

  Further, the dimensions, numerical values, shapes, and arrangements shown in the above-described embodiments are merely examples, and the present invention is not limited to these embodiments, and various modifications can be made within the scope of the present invention described in the claims. Can be changed.

It is a figure which shows the protection circuit periphery part of one Example of a semiconductor device, (A) is sectional drawing, (B) is a top view in the AA position of (A), (C) is B of (A). It is a top view in -B position, (A) is sectional drawing in CC position of (B) and (C). It is a top view which shows the Example, (A) shows the whole, (B) expands and shows the part enclosed by the circle of (A). It is an equivalent circuit which shows an example of a structure of the electrode pad and I / O cell of the Example. (A) is sectional drawing of the peripheral part of the electrode pad for Vcc of the Example, (B) is sectional drawing of the peripheral part of the electrode pad for GND of the Example. It is sectional drawing which shows the Example of the protection circuit applied to the 6-layer metal wiring structure. It is a figure which shows the protection circuit periphery part of the Example using the MOS transistor which has a polysilicon gate as a protection element of a protection circuit, (A) is sectional drawing, (B) is in the AA position of (A). A top view and (C) are top views in the BB position of (A). It is an equivalent circuit which shows an example of a structure of the electrode pad and I / O cell of the Example. It is a figure which shows the protection circuit periphery part of the other Example using the field transistor as a protection element of a protection circuit, (A) is sectional drawing, (B) is a top view in the AA position of (A), (C) is a top view in the BB position of (A). It is an equivalent circuit which shows an example of a structure of the electrode pad and I / O cell of the Example. It is a top view which shows the conventional semiconductor device, (A) shows the whole, (B) expands and shows a part of periphery of a power supply pad and a GND pad. It is a top view which shows an example of a structure of an electrode pad and an I / O cell. 12 is an equivalent circuit of the electrode pad and I / O cell of FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 P-type semiconductor substrate 5 Internal core area | region 7 Electrode pad 9 I / O cell 11a Vcc line for internal core area | region 11b GND line for internal core area | region 13a Vcc line for I / O cell 13b GND line for I / O cell 13c metal wiring layer 15 protection circuit Tr1, Tr2 field transistor 17 input buffer Tr3, Tr4 MOS transistor Vcc power supply GND ground 19a, 19b, 19c N + diffusion region 21 field oxide film 23 insulating films 25a, 25b, 25c lower metal wiring layer 27, 29 Interlayer insulation layer 31 Passivation film

Claims (3)

In a semiconductor device in which a plurality of electrode pads for electrically connecting a semiconductor device to the outside are disposed, and a protection circuit is provided for each of the electrode pads,
As the power supply line and the GND line, in addition to the power supply line for the internal core region and the GND line for the internal core region, the power supply line for the I / O cell and the GND line for the I / O cell are provided.
2. The semiconductor device according to claim 1, wherein the I / O cell power line and the I / O cell GND line are continuously formed across the electrode pad formation region. 2. The semiconductor device according to claim 1, wherein the power line for I / O cell and the GND line for I / O cell are configured by a metal wiring layer or a polysilicon wiring layer. The semiconductor device according to claim 1, wherein five or more metal wiring layers are formed in a layer between a semiconductor substrate and the electrode pad.

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