JPH07245380A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent breakdown of an N-channel MOS transistor of a latchup prevention circuit even when a surge exceeding a breakdown voltage is applied. CONSTITUTION:An N-channel transistor 103 is connected between a ground terminal 101 and a power supply terminal 102. A source and a gate are connected to the ground terminal 101 and a drain is connected to the power supply terminal 102 through a resistor 104. Here, the drain and the resistor 104 are connected without a metallic wiring. When a surge is applied to the power supply terminal 102, breakdown of the transistor 103 is prevented by absorption of applied energy in the resistor. Simultaneously, surge is absorbed by operation of the transistor 103 and latchup is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a protection circuit for preventing latch-up.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a parasitic transistor is formed by its device structure in addition to a design circuit formed inside. These parasitic transistors operate due to power supply voltage fluctuations, surges, etc., causing a latch-up phenomenon in which a large current continues to flow. This phenomenon may cause the wiring to be blown, the protective diode to be broken, or the like, resulting in device failure. Therefore, in order to prevent the latch-up phenomenon, a latch-up prevention circuit is generally added between the power supply terminal and the ground terminal.

A conventional latch-up prevention circuit will be described below. FIG. 4 is a diagram illustrating a conventional latch-up prevention circuit. 401 is a ground terminal, 402 is a power supply terminal, and an N-channel transistor 403 is connected between the ground terminal 401 and the power supply terminal 402. N
S, D, and G of the channel transistor 403 are sources,
The drain and gate. N-channel transistor 40
The source and gate of 3 are connected to the ground terminal 401,
The drain is connected to the power supply terminal 402. The operation of the latch-up prevention circuit will be described below. Power supply terminal 4
When a positive high voltage due to a fluctuation of the power supply voltage or a surge is applied to 02, a current flows between the power supply terminal 402 and the ground terminal 401 by the bipolar operation between the source and the drain of the N-channel transistor 403, and the high voltage is absorbed. To be done. Therefore, high voltage is not applied to the parasitic transistor of the internal circuit (not shown), and latch-up is prevented.

[0004]

However, in the above structure, when a surge exceeding the withstand voltage of the N-channel transistor 403 is applied to the power supply terminal 402, the N-channel transistor 403 for preventing latch-up is destroyed. It had a problem that

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a latch-up prevention circuit which is not destroyed even when a surge exceeding a withstand voltage is applied to a power supply terminal.

[0006]

In order to solve the above-mentioned problems, a semiconductor device of the present invention comprises a first conductivity type substrate,
In a circuit including a first power supply terminal, a second power supply terminal, and a second conductivity type transistor having a source and a gate connected to the first power supply terminal and a drain connected to the second power supply terminal, A resistance using a second conductivity type well is connected between a power supply terminal and the drain of the second conductivity type transistor.

Further, in the semiconductor device of the present invention, in the N-type substrate, a first power supply terminal, a second power supply terminal having a lower potential than the first power supply terminal, a source and a gate are connected to the first power supply terminal, In a circuit including a P-channel transistor having a drain connected to the second power supply terminal, a resistance using a P-well is connected between the second power supply terminal and the drain of the P-channel transistor. It is a thing.

In the semiconductor device of the present invention, in the first conductivity type substrate, a first power supply terminal, a second power supply terminal, a source and a gate are connected to the first power supply terminal, and a drain is connected to the second power supply terminal. In a circuit having a second conductivity type transistor connected via a resistance using a second conductivity type well, the current direction of the resistance using the second conductivity type well and the current direction of the second conductivity type transistor. And a resistor using the well of the second conductivity type and the transistor of the second conductivity type are arranged so that and are parallel and on the same straight line.

[0009]

The present invention has the above-described structure and solves the problem by the operation described below. When a surge higher than the breakdown voltage of the transistor in the latch-up prevention circuit is applied to the power supply terminal, the surge is applied to the transistor via the well resistance. At that time, the well resistance absorbs the applied energy, and the energy applied to the transistor decreases. Therefore, destruction of the transistor is prevented. At the same time, due to the bipolar operation between the source and drain of the transistor, a current flows between the power supply terminal and the ground terminal, and the surge is absorbed. Therefore, no high voltage is applied to the parasitic transistor of the internal circuit, and latch-up is prevented.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 shows a latch-up prevention circuit according to a first embodiment of the present invention.
FIG. 1A is an equivalent circuit diagram and FIG. 1B is a sectional structure diagram. In FIG. 1A, 101 is a ground terminal, 102 is a power supply terminal, and an N-channel transistor 103 is connected between the ground terminal 101 and the power supply terminal 102. S, D, and G are the source, drain, and gate of the N-channel transistor 103. The source and gate are connected to the ground terminal 101, and the drain is connected to the power supply terminal 102 via the resistor 104.
Further, in FIG. 1B, the N-channel transistor 103 is formed on the P-type semiconductor substrate 111.
S, D, and G are the source, drain, and gate of the N-channel transistor 103. The source and the gate are connected to a ground terminal (not shown) by a metal wiring 115,
The drain is connected to a power supply terminal (not shown) via the resistor 104 and the metal wiring 116. The resistor 104 is the n + diffusion layer 11 in the N well 112 on the P-type semiconductor substrate 111.
3 and element isolation 114.

The operation will be described below. Power terminal 10
When a surge higher than the withstand voltage of the N-channel transistor 103 is applied to 2, the surge is applied to the N-channel transistor 103 via the resistor 104. At that time, the applied energy is absorbed by the resistor 104, and the energy applied to the N-channel transistor 103 decreases. Therefore, the breakdown of the N-channel transistor 103 is prevented. At the same time, due to the bipolar operation between the source and drain of the N-channel transistor 103,
A current flows between the power supply terminal 102 and the ground terminal 101, and the surge is absorbed. Therefore, a high voltage is not applied to the parasitic transistor (not shown) of the internal circuit, and latch-up is prevented.

By thus forming the N well resistor 104 between the power supply terminal 102 and the drain of the N channel transistor 103, the N channel transistor 10 is formed.
3 is prevented from being destroyed, and the surge withstand voltage of the latch-up prevention circuit is improved. In addition, n in the N well resistor 104
The area can be reduced by connecting the + diffusion layer and the n + diffusion layer of the drain of the N-channel transistor 103 without using a metal wiring.

Although the N-channel transistor and the N-well resistor on the P-type semiconductor substrate have been described in this embodiment, the same effect can be obtained for the P-channel transistor and the P-well on the N-type semiconductor substrate.

(Embodiment 2) FIG. 2 shows a latch-up prevention circuit according to a second embodiment of the present invention.
2A is an equivalent circuit diagram, FIG. 2B is a sectional structure diagram, and FIG.
(C) shows a circuit layout diagram. In FIG. 2A, 201 is a ground terminal, 202 is a power supply terminal, and an N-channel transistor 203 is connected between the ground terminal 201 and the power supply terminal 202. S, D,
G is a source, a drain, and a gate of the N-channel transistor 203. Source and gate are ground terminals 2
01, and the drain is connected to the power supply terminal 202 via the resistor 204. In addition, in FIG.
An N-channel transistor 203 is formed on the P-type semiconductor substrate 211. S, D, and G are the source, drain, and gate of the N-channel transistor 203. The source and gate are connected to a ground terminal (not shown) by a metal wiring 215, and the drain is connected to a power supply terminal (not shown) via a resistor 204 and a metal wiring 216. The resistor 204 is formed in the N well 212 on the P-type semiconductor substrate 211 by the n + diffusion layer 213 and the element isolation 214. Further, in FIG. 2C, the N-channel transistor 203 is formed on the P-type semiconductor substrate. S, D, and G are N-channel transistors 203
Of the source, drain and gate. The source and gate are connected to a ground terminal (not shown) by a metal wiring (not shown), and the drain is a resistor 204 and a metal wiring 22.
It is connected to the power supply terminal 202 via 5. Resistance 20
4 is an element isolation 2 in the N well 222 on the P-type semiconductor substrate.
24 and an n + diffusion layer 223 sandwiching the element isolation 224. Further, the element isolation 224 sandwiched between the n + diffusion layers 223 and the gate of the N-channel transistor 203 are
They are arranged in parallel and face each other.

The operation will be described below. Power terminal 20
When a surge higher than the withstand voltage of the N-channel transistor 203 is applied to No. 2, the surge is applied to the N-channel transistor 203 via the resistor 204. At that time, the applied energy is absorbed by the resistor 204, and the energy applied to the N-channel transistor 203 decreases. Therefore, destruction of the N-channel transistor 203 is prevented. At the same time, due to the bipolar operation between the source and drain of the N-channel transistor 203,
A current flows between the power supply terminal 202 and the ground terminal 201, and the surge is absorbed. Therefore, a high voltage is not applied to the parasitic transistor (not shown) of the internal circuit, and latch-up is prevented.

As described above, by forming the N well resistor 204 between the power supply terminal 202 and the drain of the N channel transistor 203, the N channel transistor 20 is formed.
3 is prevented from being destroyed, and the surge withstand voltage of the latch-up prevention circuit is improved. In addition, n in the N well resistor 204
The area can be reduced by connecting the + diffusion layer and the n + diffusion layer of the drain of the N-channel transistor 203 without using a metal wiring. Further, the element isolation 224 sandwiched between the n + diffusion layers 223 of the N well resistor 204
And the gate of the N-channel transistor 203 are arranged so as to be parallel and face each other, the bias of the current at the drain of the N-channel transistor 203 does not occur, and the breakdown voltage of the N-channel transistor 203 is improved.

In this embodiment, the N-channel transistor and the N-well resistance on the P-type semiconductor substrate have been described, but the same effect can be obtained for the P-channel transistor and the P-well on the N-type semiconductor substrate.

(Third Embodiment) FIG. 3 shows a latch-up prevention circuit according to a third embodiment of the present invention.
3A is an equivalent circuit diagram, FIG. 3B is a sectional structure diagram, and FIG.
(C) shows a circuit layout diagram. In FIG. 3A, 301 is a ground terminal, 302 is a power supply terminal, and the first terminal is provided between the ground terminal 301 and the power supply terminal 302.
N-channel transistor 303 is connected.
S, D, and G are the first N-channel transistor 303
Of the source, drain and gate. The source and gate are connected to the ground terminal 301, and the drain is connected to the power supply terminal 302 via the first resistor 304. In addition, the second N-channel transistor 305 and the second resistor 306, which have the same size as the first N-channel transistor 303 and the first resistor 304, respectively, are the same as the first N-channel transistor 303 and the first resistor 304. The ground terminal 301 and the power supply terminal 3 have the same configuration and are parallel to them.
It is connected between 02.

Further, in FIG. 3B, a first N-channel transistor 303 is formed on the P-type semiconductor substrate 311. S, D, and G are the source, drain, and gate of the first N-channel transistor 303.
The source and the gate are connected to the ground terminal (not shown) by the metal wiring 315, and the drain is the first resistor 304.
And a metal wiring 316 to connect to a power supply terminal (not shown). The first resistor 304 is a P-type semiconductor substrate 311.
In the upper N well 312, an n + diffusion layer 313 and an element isolation 3 are formed.
It is formed with 14. Also, centering on the N well,
A similar second well resistance and a second transistor are formed on the opposite side in the same configuration (not shown).

Further, in FIG. 3C, the first N-channel transistor 303 is formed on the P-type semiconductor substrate. S, D, and G are the source, drain, and gate of the first N-channel transistor 303. The source and the gate are connected to a ground terminal (not shown) by a metal wiring (not shown), and the drain is the first resistor 304.
Is connected to the power supply terminal 302 via a metal wiring 325. The first resistor 304 is an element isolation 324 in the N well 322 on the P-type semiconductor substrate and n + which sandwiches the element isolation 324.
And the diffusion layer 223. In addition, the n + diffusion layer 3
The element isolation 324 sandwiched by 23 and the gate of the first N-channel transistor 303 are arranged parallel to each other and facing each other. Further, the second well resistor 30 of the same size is symmetrically arranged on the opposite side with the N well 322 as the center.
6 and the second transistor 305 are formed.

The operation will be described below. Power terminal 30
When a surge higher than the withstand voltage of the first N-channel transistor 303 is applied to 2, the surge is applied to the first N-channel transistor 303 via the first resistor 304. At that time, the applied energy is absorbed by the first resistor 304, and the first N-channel transistor 3
The energy applied to 03 is reduced. Therefore, destruction of the first N-channel transistor 303 is prevented. And at the same time, the first N-channel transistor 303
Due to the bipolar operation between the source and the drain, current flows between the power supply terminal 202 and the ground terminal 201, and the surge is absorbed. Therefore, a high voltage is not applied to the parasitic transistor (not shown) of the internal circuit, and latch-up is prevented. The above description is based on the first resistor 304.
The first N-channel transistor 303 has been described above, but the second well resistor 306 and the second transistor 305 of the same size, which are symmetrically arranged, also operate in the same manner.

As described above, by forming the N well resistors 304 and 306 between the power supply terminal 302 and the drains of the N channel transistors 303 and 305, destruction of the N channel transistors 303 and 305 is prevented, and latch-up occurs. The surge withstand voltage as a protection circuit is improved. Also,
The area can be reduced by connecting the n + diffusion layers in the N-well resistors 304 and 306 and the n + diffusion layers of the drains of the N-channel transistors 303 and 305 without using metal wiring. In addition, N well resistors 304 and 3
By arranging the element isolation sandwiched between the n + diffusion layers of 06 and the gates of the N-channel transistors 303 and 305 so as to be parallel and face each other, the bias of the currents at the drains of the N-channel transistors 303 and 305 occurs. Therefore, the breakdown voltage of the N-channel transistors 303 and 305 is improved. In addition, the area can be reduced by providing two N-channel transistor regions with respect to one region of the N well 322.

In this embodiment, one N well region is provided with two N-channel transistor regions, but the same effect can be obtained with three or more N-channel transistor regions. Further, in the present embodiment, the N well region is described as one location, but the same effect can be obtained even if the N well region is provided at two or more locations. Although the N-channel transistor and the N-well resistor on the P-type semiconductor substrate are described in the present embodiment, the same effect can be obtained for the P-channel transistor and the P-well on the N-type semiconductor substrate.

[0025]

As described above, the present invention realizes a latch-up prevention circuit having a high breakdown voltage against surges by forming a well resistance between the power supply terminal and the drain of the transistor.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a latch-up prevention circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a latch-up prevention circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a latch-up prevention circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a latch-up prevention circuit in a conventional example.

[Explanation of symbols]

 101 ground terminal 102 power supply terminal 103 N-channel transistor 104 resistance 111 P-type semiconductor substrate 112 N well 113 n + diffusion layer 114 metal wiring 115 metal wiring 116 metal wiring 117 insulating film 118 protective film 201 ground terminal 202 power supply terminal 203 N-channel transistor 204 resistance 211 P type semiconductor substrate 212 N well 213 n + diffusion layer 214 metal wiring 215 metal wiring 216 metal wiring 217 insulating film 218 protective film 222 N well 223 n + diffusion layer 224 element isolation 225 metal wiring 226 contact hole 301 ground terminal 302 power supply terminal 303 first N-channel transistor 304 first resistance 305 second N-channel transistor 306 second resistance 311 P-type semiconductor substrate 312 N well 3 3 n + diffusion layer 314 isolation 315 metal wires 316 metal wiring 317 insulating film 318 protective film 322 N-well 323 n + diffusion layer 324 isolation 325 metal wires 326 contact holes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H01L 21/822 29/78

Claims (10)

[Claims] 1. In a P-type substrate, a first power supply terminal, a second power supply terminal having a potential higher than that of the first power supply terminal, a source and a gate are connected to the first power supply terminal, and the second power supply terminal is connected to the second power supply terminal. In a circuit including an N-channel transistor having a drain connected to the semiconductor device, a resistor using an N-well is connected between the second power supply terminal and the drain of the N-channel transistor. 2. A semiconductor device according to claim 1, wherein the resistance using the N well and the drain of the N channel transistor are connected without a metal wiring. 3. A semiconductor device according to claim 2, wherein the resistance using the N well and the drain of the N channel transistor are connected by an n + diffusion layer. 4. An N-type substrate, wherein a first power supply terminal, a second power supply terminal having a lower potential than the first power supply terminal, a source and a gate are connected to the first power supply terminal, and the second power supply terminal is connected to the second power supply terminal. A semiconductor device comprising a P-channel transistor having a drain connected thereto, wherein a resistor using a P-well is connected between the second power supply terminal and the drain of the P-channel transistor. 5. The semiconductor device according to claim 4, wherein the resistance using the P well and the drain of the P channel transistor are connected without a metal wiring. 6. The semiconductor device according to claim 5, wherein the resistance using the P well and the drain of the P channel transistor are connected by a p + diffusion layer. 7. A first conductivity type substrate, a first power source terminal, a second power source terminal, a source and a gate are connected to the first power source terminal, and a drain is a second conductivity type well in the second power source terminal. In a circuit including a second conductivity type transistor connected via a resistor using the second conductivity type transistor, a current direction of the resistance using the second conductivity type well and a current direction of the second conductivity type transistor are parallel and in the same straight line. A semiconductor device in which a resistance using the well of the second conductivity type and the transistor of the second conductivity type are arranged as shown on a line. 8. A region n of a second conductivity type well,
8. The semiconductor device according to claim 7, wherein there are 2n or more regions of the second conductivity type transistor. 9. The semiconductor device according to claim 7, wherein the resistance using the second conductivity type well and the second conductivity type transistor are connected without a metal wiring. 10. The semiconductor device according to claim 9, wherein the resistance using the second conductivity type well and the second conductivity type transistor are connected by a second conductivity type diffusion layer.